PCA9549 Octal bus switch with individually I2C-bus controlled enables Rev. 02 — 13 July 2009 Product data sheet 1. General description The PCA9549 provides eight bits of high speed TTL-compatible bus switching controlled by the I2C-bus. The low ON-state resistance of the switch allows connections to be made with minimal propagation delay. Any individual A to B channel or combination of channels can be selected via the I2C-bus, determined by the contents of the programmable Control register. When the I2C-bus bit is HIGH (logic 1), the switch is on and data can flow from Port A to Port B, or vice versa. When the I2C-bus bit is LOW (logic 0), the switch is open, creating a high-impedance state between the two ports, which stops the data flow. An active LOW reset input (RESET) allows the PCA9549 to recover from a situation where the I2C-bus is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-bus state machine and causes all the bits to be open, as does the internal power-on reset function. Three address pins allow up to eight devices on the same bus. 2. Features n n n n n n n n n n n n n n n 8-bit bus switch (CBT) 5 Ω switch connection between two ports I2C-bus interface logic; compatible with SMBus standards Active LOW RESET input 3 address pins allowing up to 8 devices on the I2C-bus Bit selection via I2C-bus, in any combination Power-up with all bits deselected Low Ron switches No glitch on power-up Supports hot insertion Low standby current Operating power supply voltage range of 2.3 V to 5.5 V 5 V tolerant inputs 0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 n Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA n Packages offered: SO24, TSSOP24, HVQFN24 PCA9549 NXP Semiconductors Octal bus switch with individually I2C-bus controlled enables 3. Ordering information Table 1. Ordering information Type number Package Name Description Version PCA9549D SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 PCA9549PW TSSOP24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1 PCA9549BS HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 × 4 × 0.85 mm SOT616-1 3.1 Ordering options Table 2. Ordering options Type number Topside mark Temperature range PCA9549D PCA9549D −40 °C to +85 °C PCA9549PW PCA9549 −40 °C to +85 °C PCA9549BS 9549 −40 °C to +85 °C 4. Block diagram PCA9549 1A 1B 2A 2B 3A 3B 4A 4B 5A 5B 6A 6B 7A 7B 8A 8B VSS SWITCH CONTROL LOGIC VDD RESET CIRCUIT RESET SCL INPUT FILTER SDA A0 I2C-BUS CONTROL A1 A2 002aaa991 Fig 1. Block diagram PCA9549_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 July 2009 2 of 25 PCA9549 NXP Semiconductors Octal bus switch with individually I2C-bus controlled enables 5. Pinning information 5.1 Pinning A0 1 24 VDD A0 1 A1 2 23 SDA A1 2 24 VDD 23 SDA RESET 3 22 SCL RESET 3 22 SCL 1A 4 21 A2 1A 4 21 A2 1B 5 20 8A 1B 5 20 8A 2A 6 19 8B 2A 6 2B 7 18 7A 2B 7 3A 8 17 7B 3A 8 17 7B 3B 9 16 6A 3B 9 16 6A 4A 10 15 6B 4A 10 15 6B 4B 11 14 5A 4B 11 14 5A VSS 12 13 5B VSS 12 13 5B PCA9549D PCA9549PW 002aaa992 18 7A 002aaa993 Pin configuration of TSSOP24 19 SCL 20 SDA 21 VDD 22 A0 terminal 1 index area 23 A1 Fig 3. 24 RESET Pin configuration of SO24 1A 1 18 A2 1B 2 17 8A 2A 3 2B 4 3A 5 14 7B 3B 6 13 6A 16 8B 15 7A 6B 12 9 VSS 5A 11 8 5B 10 7 4B PCA9549BS 4A Fig 2. 19 8B 002aaa994 Transparent top view Fig 4. Pin configuration of HVQFN24 (transparent top view) PCA9549_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 July 2009 3 of 25 PCA9549 NXP Semiconductors Octal bus switch with individually I2C-bus controlled enables 5.2 Pin description Table 3. Symbol A0 Pin description Pin Description SO24, TSSOP24 HVQFN24 1 22 A1 2 23 address input 1 RESET 3 24 active LOW reset input 1A 4 1 input 1B 5 2 output 2A 6 3 input 2B 7 4 output 3A 8 5 input 3B 9 6 output 4A 10 7 input 4B 11 8 output VSS 12 9[1] supply ground 5B 13 10 output 5A 14 11 input 6B 15 12 output 6A 16 13 input 7B 17 14 output 7A 18 15 input 8B 19 16 output 8A 20 17 input A2 21 18 address input 2 SCL 22 19 serial clock line SDA 23 20 serial data line VDD 24 21 supply voltage [1] HVQFN24 package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region. PCA9549_2 Product data sheet address input 0 © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 July 2009 4 of 25 PCA9549 NXP Semiconductors Octal bus switch with individually I2C-bus controlled enables 6. Functional description 6.1 Device addressing Following a START condition, the bus master must output the address of the slave it is accessing. The address of the PCA9549 is shown in Figure 5. To conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW. 1 1 1 0 A2 fixed A1 A0 R/W hardware selectable 002aaa962 Fig 5. Slave address The last bit of the slave address defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation. 6.2 Control register Following the successful acknowledgement of the slave address, the bus master will send a byte to the PCA9549, which will be stored in the Control register. If multiple bytes are received by the PCA9549, it will save the last byte received. This register can be written and read via the I2C-bus. channel selection bits (read/write) 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 B1 B0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 002aab254 Fig 6. Control register 6.2.1 Control register definition One or several bits are selected by the contents of the Control register. This register is written after the PCA9549 has been addressed. The entire control byte is used to determine which bit is to be selected. When a bit is selected to close, the bit will close after the Acknowledge has been placed on the I2C-bus. PCA9549_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 July 2009 5 of 25 PCA9549 NXP Semiconductors Octal bus switch with individually I2C-bus controlled enables Table 4. Control register Write = channel selection; read = channel status. B7 B6 B5 B4 B3 B2 B1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 [1] 0 1 X 0 0 1 B0 0 bit 1 disabled 1 bit 1 enabled X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 1 Command bit 2 disabled bit 2 enabled bit 3 disabled bit 3 enabled bit 4 disabled bit 4 enabled bit 5 disabled bit 5 enabled bit 6 disabled bit 6 enabled bit 7 disabled bit 7 enabled bit 8 disabled bit 8 enabled Several bits can be enabled at the same time. For example, B7 = 0, B6 = 1, B5 = 0, B4 = 0, B3 = 1, B2 = 1, B1 = 0, B0 = 0, means that bit 8, bit 6, bit 5, bit 2, and bit 1 are disabled and bit 7, bit 4, and bit 3 are enabled. 6.3 RESET input The RESET input is an active LOW signal which may be used to recover from a bus fault condition. By asserting this signal LOW for a minimum of tw(rst)L, the PCA9549 will reset its registers and I2C-bus state machine and will open all bits. The RESET input must be connected to VDD through a pull-up resistor. 6.4 Power-on reset When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9549 in a reset state until VDD has reached VPOR. At this point, the reset condition is released and the PCA9549 registers and I2C-bus state machine are initialized to their default states, all zeroes causing all the bits to be open (high-impedance state). 6.5 CBT characteristic over VDD range The bus switch is optimized at 5.0 V but can operate over the entire supply range with lower Vo(sw) voltage and higher gate resistance. PCA9549_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 July 2009 6 of 25 PCA9549 NXP Semiconductors Octal bus switch with individually I2C-bus controlled enables 002aaa964 5.0 Vo(sw) (V) 4.0 (1) (2) 3.0 (3) 2.0 1.0 2.0 2.5 3.0 3.5 4.0 4.5 5.5 5.0 VDD (V) (1) maximum. (2) typical. (3) minimum. Fig 7. Vo(sw) voltage versus VDD Figure 7 shows the voltage characteristics of the pass gate transistors (note that the PCA9549 is only tested at the points specified in Section 9 “Static characteristics”). In order for the PCA9549 to act as a voltage translator, the Vo(sw) voltage should be equal to, or lower than the lowest bus voltage. For example, if the main bus was running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vo(sw) should be equal to or below 2.7 V to effectively clamp the downstream bus voltages. Looking at Figure 7, we see that Vo(sw) (maximum) will be at 2.7 V when the PCA9549 supply voltage is 3.5 V or lower so the PCA9549 supply voltage could be set to 3.3 V. Pull-up resistors can then be used to bring the bus voltages to their appropriate levels (see Figure 16). PCA9549_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 July 2009 7 of 25 PCA9549 NXP Semiconductors Octal bus switch with individually I2C-bus controlled enables 7. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. 7.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 8). SDA SCL data line stable; data valid Fig 8. change of data allowed mba607 Bit transfer 7.1.1 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 9). SDA SCL S P START condition STOP condition mba608 Fig 9. Definition of START and STOP conditions 7.2 System configuration A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 10). PCA9549_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 July 2009 8 of 25 PCA9549 NXP Semiconductors Octal bus switch with individually I2C-bus controlled enables SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C-BUS MULTIPLEXER SLAVE 002aaa966 Fig 10. System configuration 7.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master 1 S START condition 2 8 9 clock pulse for acknowledgement 002aaa987 Fig 11. Acknowledgement on the I2C-bus PCA9549_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 July 2009 9 of 25 PCA9549 NXP Semiconductors Octal bus switch with individually I2C-bus controlled enables 7.4 Bus transactions Data is transmitted to the PCA9549 control register using the Write mode as shown in Figure 12. slave address SDA S 1 1 1 0 A2 control register A1 A0 START condition 0 R/W A B7 B6 B5 B4 B3 B2 acknowledge from slave B1 B0 A P acknowledge from slave STOP condition 002aac430 Fig 12. Write control register Data is read from the PCA9549 using the Read mode as shown in Figure 13. slave address SDA S 1 1 1 0 A2 START condition last byte control register A1 A0 1 R/W A B7 B6 B5 B4 B3 acknowledge from slave B2 B1 B0 A P no acknowledge from master STOP condition 002aac431 Fig 13. Read control register 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter VDD Min Max Unit supply voltage −0.5 +7.0 V VI input voltage −0.5 +7.0 V II input current −20 +20 mA IO output current −25 +25 mA IDD supply current −100 +100 mA ISS ground supply current −100 +100 mA Ptot total power dissipation - 400 mW Tstg storage temperature −60 +150 °C Tamb ambient temperature −40 +85 °C [1] Conditions operating The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 125 °C. PCA9549_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 July 2009 10 of 25 PCA9549 NXP Semiconductors Octal bus switch with individually I2C-bus controlled enables 9. Static characteristics Table 6. Static characteristics at VDD = 2.3 V to 3.6 V VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. See Table 7 on page 12 for VDD = 4.5 V to 5.5 V[1]. Symbol Parameter Conditions Min Typ Max Unit Supply VDD supply voltage 2.3 - 3.6 V IDD supply current Operating mode; VDD = 3.6 V; no load; VI = VDD or VSS; fSCL = 100 kHz - 20 50 µA Istb standby current Standby mode; VDD = 3.6 V; no load; VI = VDD or VSS - 0.1 1 µA VPOR power-on reset voltage no load; VI = VDD or VSS - 1.6 2.1 V −0.5 - +0.3VDD V [2] Input SCL; input/output SDA VIL LOW-level input voltage VIH HIGH-level input voltage IOL LOW-level output current 0.7VDD - 6 V VOL = 0.4 V 3 - - mA VOL = 0.6 V 6 - - mA IL leakage current VI = VDD or VSS −1 - +1 µA Ci input capacitance VI = VSS - 6 21 pF Select inputs A0 to A2, RESET VIL LOW-level input voltage −0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - VDD + 0.5 V ILI input leakage current pin at VDD or VSS −1 - +1 µA Ci input capacitance VI = VSS - 2 5 pF ON-state resistance VDD = 3.0 V to 3.6 V; VO = 0.4 V; IO = 15 mA - 7 12 Ω VDD = 2.3 V to 2.7 V; VO = 0.4 V; IO = 10 mA - 8 15 Ω Vi(sw) = VDD = 3.3 V; Io(sw) = −100 µA - 1.9 - V Vi(sw) = VDD = 3.0 V to 3.6 V; Io(sw) = −100 µA 1.6 - 2.8 V Vi(sw) = VDD = 2.5 V; Io(sw) = −100 µA - 1.5 - V Vi(sw) = VDD = 2.3 V to 2.7 V; Io(sw) = −100 µA 1.0 - 2.0 V Pass gate Ron Vo(sw) switch output voltage IL leakage current VI = VDD or VSS −1 - +1 µA Cio input/output capacitance VI = VSS - 3 5 pF [1] For operation between published voltage ranges, refer to the worst-case parameters in both ranges. [2] VDD must be lowered to 0.2 V in order to reset part. PCA9549_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 July 2009 11 of 25 PCA9549 NXP Semiconductors Octal bus switch with individually I2C-bus controlled enables Table 7. Static characteristics at VDD = 4.5 V to 5.5 V VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. See Table 6 on page 11 for VDD = 2.3 V to 3.6 V[1]. Symbol Parameter Conditions Min Typ Max Unit 4.5 - 5.5 V Supply VDD supply voltage IDD supply current Operating mode; VDD = 5.5 V; no load; VI = VDD or VSS; fSCL = 100 kHz - 65 100 µA Istb standby current Standby mode; VDD = 5.5 V; no load; VI = VDD or VSS - 0.6 2 µA VPOR power-on reset voltage no load; VI = VDD or VSS - 1.7 2.1 V [2] Input SCL; input/output SDA VIL LOW-level input voltage −0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 6 V IOL LOW-level output current VOL = 0.4 V 3 - - mA VOL = 0.6 V 6 - - mA IIL LOW-level input current VI = VSS 1 - 1 µA IIH HIGH-level input current VI = VSS 1 - 1 µA Ci input capacitance VI = VSS - 6 21 pF Select inputs A0 to A2, RESET VIL LOW-level input voltage −0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - VDD + 0.5 V ILI input leakage current pin at VDD or VSS −1 - +50 µA Ci input capacitance VI = VSS - 2 5 pF Ron ON-state resistance VDD = 4.5 V to 5.5 V; VO = 0.4 V; IO = 15 mA - 5 8 Ω Vo(sw) switch output voltage Vi(sw) = VDD = 5.0 V; Io(sw) = −100 µA - 3.6 - V Vi(sw) = VDD = 4.5 V to 5.5 V; Io(sw) = −100 µA 2.6 - 4.5 V Pass gate IL leakage current VI = VDD or VSS −10 - +10 µA Cio input/output capacitance VI = VSS - 3 5 pF [1] For operation between published voltage ranges, refer to the worst-case parameters in both ranges. [2] VDD must be lowered to 0.2 V in order to reset part. PCA9549_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 July 2009 12 of 25 PCA9549 NXP Semiconductors Octal bus switch with individually I2C-bus controlled enables 10. Dynamic characteristics Table 8. Dynamic characteristics Symbol Parameter Conditions Standard-mode I2C-bus A to B; VDD = 4.5 V to 5.5 V Fast-mode I2C-bus Unit Min Max Min - 0.25[1] Max - 0 100 0 400 4.7 - 1.3 - µs 4.0 - 0.6 - µs 0.25[1] ns tPD propagation delay fSCL SCL clock frequency tBUF bus free time between a STOP and START condition tHD;STA hold time (repeated) START condition tLOW LOW period of the SCL clock 4.7 - 1.3 - µs tHIGH HIGH period of the SCL clock 4.0 - 0.6 - µs tSU;STA set-up time for a repeated START condition 4.7 - 0.6 - µs tSU;STO set-up time for STOP condition 4.0 - 0.6 - µs tHD;DAT data hold time 0[3] 3.45 0[3] 0.9 µs [2] kHz tSU;DAT data set-up time 250 - 100 - ns tr rise time of both SDA and SCL signals - 1000 20 + 0.1Cb[4] 300 ns tf fall time of both SDA and SCL signals - 300 20 + 0.1Cb[4] 300 ns Cb capacitive load for each bus line - 400 - 400 pF tSP pulse width of spikes that must be suppressed by the input filter - 50 - 50 ns tVD;DAT data valid time HIGH-to-LOW - 1 - 1 µs LOW-to-HIGH - 0.6 - 0.6 µs tVD;ACK data valid acknowledge time - 1 - 1 µs tw(rst)L LOW-level reset time 4 - 4 - ns trst reset time 500 - 500 - ns tREC;STA recovery time to START condition 0 - 0 - ns RESET SDA clear [1] Pass gate propagation delay is calculated from the 6 Ω typical Ron and the 50 pF load capacitance. [2] After this period, the first clock pulse is generated. [3] A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. [4] Cb = total capacitance of one bus line in pF. PCA9549_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 July 2009 13 of 25 PCA9549 NXP Semiconductors Octal bus switch with individually I2C-bus controlled enables SDA tr tBUF tf tHD;STA tSP tLOW SCL tHD;STA P tSU;STA tHD;DAT S tHIGH tSU;DAT tSU;STO Sr P 002aaa986 Fig 14. Definition of timing on the I2C-bus ACK or read cycle START SCL 70 % SDA trst RESET 50 % 50 % trec(rst) 50 % tw(rst)L 002aac314 Fig 15. Definition of RESET timing PCA9549_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 July 2009 14 of 25 PCA9549 NXP Semiconductors Octal bus switch with individually I2C-bus controlled enables 11. Application information VDD = 5.0 V VDD = 5.0 V I2C-bus/SMBus MASTER SDA SDA 1A SCL SCL 1B RESET bit 1 2A bit 2 2B 3A bit 3 3B PCA9549 4A bit 4 4B 5A bit 5 5B 6A bit 6 6B 7A bit 7 7B A2 A1 A0 8A VSS 8B bit 8 002aaa995 Remark: B can also be input and A can also be output as shown in bit 8. Fig 16. Typical application A B C D E SCL SDA RESET A B C D E 002aac279 Fig 17. Custom multiplexer or demultiplexer application PCA9549_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 July 2009 15 of 25 PCA9549 NXP Semiconductors Octal bus switch with individually I2C-bus controlled enables AA AB AC AD BA BB BC BD SCL SDA RESET A B 002aac280 Fig 18. 2 channel 4-to-1 multiplexer or demultiplexer 12. Test information 2VDD VDD RL VO PULSE GENERATOR DUT CL 50 pF RT 002aac315 CL = load capacitance includes jig and probe capacitance. RL = load resistance. RT = termination resistance; should be equal to Zo of pulse generator. Fig 19. Test circuit PCA9549_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 July 2009 16 of 25 PCA9549 NXP Semiconductors Octal bus switch with individually I2C-bus controlled enables 13. Package outline SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E A X c HE y v M A Z 24 13 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.61 0.60 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT137-1 075E05 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 20. SO24 package outline (SOT137-1) PCA9549_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 July 2009 17 of 25 PCA9549 NXP Semiconductors Octal bus switch with individually I2C-bus controlled enables TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm D SOT355-1 E A X c HE y v M A Z 13 24 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 12 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 7.9 7.7 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT355-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 21. TSSOP24 package outline (SOT355-1) PCA9549_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 July 2009 18 of 25 PCA9549 NXP Semiconductors Octal bus switch with individually I2C-bus controlled enables HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm A B D SOT616-1 terminal 1 index area A A1 E c detail X e1 C 1/2 e e 12 y y1 C v M C A B w M C b 7 L 13 6 e e2 Eh 1/2 e 1 18 terminal 1 index area 24 19 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 e2 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 4.1 3.9 2.25 1.95 4.1 3.9 2.25 1.95 0.5 2.5 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT616-1 --- MO-220 --- EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-22 Fig 22. HVQFN24 package outline (SOT616-1) PCA9549_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 July 2009 19 of 25 PCA9549 NXP Semiconductors Octal bus switch with individually I2C-bus controlled enables 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 14.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities PCA9549_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 July 2009 20 of 25 PCA9549 NXP Semiconductors Octal bus switch with individually I2C-bus controlled enables 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 23) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 9 and 10 Table 9. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 10. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 23. PCA9549_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 July 2009 21 of 25 PCA9549 NXP Semiconductors Octal bus switch with individually I2C-bus controlled enables maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 23. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 15. Abbreviations Table 11. Abbreviations Acronym Description CBT Cross Bar Technology CDM Charged-Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model I2C-bus Inter-Integrated Circuit bus MM Machine Model PCB Printed-Circuit Board SMBus System Management Bus TTL Transistor-Transistor Logic PCA9549_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 July 2009 22 of 25 PCA9549 NXP Semiconductors Octal bus switch with individually I2C-bus controlled enables 16. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9549_2 20090713 Product data sheet - PCA9549_1 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Table 8 “Dynamic characteristics”: – Symbol tf: changed Unit from “µs” to “ns”. – Symbol Cb: changed Unit from “µs” to “pF”. • PCA9549_1 Updated soldering information. 20060711 Product data sheet PCA9549_2 Product data sheet - - © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 July 2009 23 of 25 PCA9549 NXP Semiconductors Octal bus switch with individually I2C-bus controlled enables 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PCA9549_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 13 July 2009 24 of 25 PCA9549 NXP Semiconductors Octal bus switch with individually I2C-bus controlled enables 19. Contents 1 2 3 3.1 4 5 5.1 5.2 6 6.1 6.2 6.2.1 6.3 6.4 6.5 7 7.1 7.1.1 7.2 7.3 7.4 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Device addressing . . . . . . . . . . . . . . . . . . . . . . 5 Control register . . . . . . . . . . . . . . . . . . . . . . . . . 5 Control register definition . . . . . . . . . . . . . . . . . 5 RESET input . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 6 CBT characteristic over VDD range . . . . . . . . . . 6 Characteristics of the I2C-bus. . . . . . . . . . . . . . 8 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 START and STOP conditions . . . . . . . . . . . . . . 8 System configuration . . . . . . . . . . . . . . . . . . . . 8 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 10 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10 Static characteristics. . . . . . . . . . . . . . . . . . . . 11 Dynamic characteristics . . . . . . . . . . . . . . . . . 13 Application information. . . . . . . . . . . . . . . . . . 15 Test information . . . . . . . . . . . . . . . . . . . . . . . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 Soldering of SMD packages . . . . . . . . . . . . . . 20 Introduction to soldering . . . . . . . . . . . . . . . . . 20 Wave and reflow soldering . . . . . . . . . . . . . . . 20 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 20 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 21 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 23 Legal information. . . . . . . . . . . . . . . . . . . . . . . 24 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 24 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Contact information. . . . . . . . . . . . . . . . . . . . . 24 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 13 July 2009 Document identifier: PCA9549_2