PCA9543A/43B/43C 2-channel I2C-bus switch with interrupt logic and reset Rev. 05 — 17 November 2008 Product data sheet 1. General description The PCA9543A/43B/43C is a bidirectional translating switch, controlled by the I2C-bus. The SCL/SDA upstream pair fans out to two downstream pairs, or channels. Any individual SCx/SDx channels or combination of channels can be selected, determined by the contents of the programmable control register. Two interrupt inputs, INT0 and INT1, one for each of the downstream pairs, are provided. One interrupt output, INT, which acts as an AND of the two interrupt inputs, is provided. An active LOW reset input allows the PCA9543X to recover from a situation where one of the downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-bus state machine and causes all the channels to be deselected, as does the internal power-on reset function. The pass gates of the switches are constructed such that the VDD pin can be used to limit the maximum high voltage which will be passed by the PCA9543X. This allows the use of different bus voltages on each SCx/SDx pair, so that 1.8 V, 2.5 V, or 3.3 V parts can communicate with 5 V parts without any additional protection. External pull-up resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5 V tolerant. The PCA9543A, PCA9543B and PCA9543C are identical except for the fixed portion of the slave address. 2. Features n n n n n n n n n n n n n n n 1-of-2 bidirectional translating switches I2C-bus interface logic; compatible with SMBus standards 2 active LOW interrupt inputs Active LOW interrupt output Active LOW reset input 2 address pins allowing up to 4 devices on the I2C-bus Alternate address versions A, B and C allow up to a total of 12 devices on the bus for larger systems or to resolve address conflicts Channel selection via I2C-bus, in any combination Power-up with all switch channels deselected Low Ron switches Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses No glitch on power-up Supports hot insertion Low standby current Operating power supply voltage range of 2.3 V to 5.5 V PCA9543A/43B/43C NXP Semiconductors 2-channel I2C-bus switch with interrupt logic and reset n 5 V tolerant inputs n 0 Hz to 400 kHz clock frequency n ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 n Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA n Packages offered: SO14, TSSOP14 3. Ordering information Table 1. Ordering information Type number Package Name Description Version PCA9543AD SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 PCA9543APW TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 PCA9543BPW PCA9543CPW 3.1 Ordering options Table 2. Ordering options Type number Topside mark Temperature range (Tamb) PCA9543AD PCA9543AD Tamb = −40 °C to +85 °C PCA9543APW PA9543A Tamb = −40 °C to +85 °C PCA9543BPW PA9543B Tamb = −40 °C to +85 °C PCA9543CPW PA9543C Tamb = −40 °C to +85 °C PCA9543A_43B_43C_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 17 November 2008 2 of 23 PCA9543A/43B/43C NXP Semiconductors 2-channel I2C-bus switch with interrupt logic and reset 4. Block diagram PCA9543A/43B/43C SC0 SC1 SD0 SD1 VSS VDD RESET SCL SDA SWITCH CONTROL LOGIC POWER-ON RESET INPUT FILTER INT0 to INT1 A0 I2C-BUS CONTROL A1 INT INTERRUPT LOGIC 002aab180 Fig 1. Block diagram of PCA9543A/43B/43C PCA9543A_43B_43C_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 17 November 2008 3 of 23 PCA9543A/43B/43C NXP Semiconductors 2-channel I2C-bus switch with interrupt logic and reset 5. Pinning information 5.1 Pinning A0 1 14 VDD A1 2 13 SDA RESET 3 12 SCL INT0 SD0 PCA9543AD 11 INT 4 1 A1 2 RESET 3 INT0 4 SD0 5 SC0 6 9 SD1 VSS 7 8 INT1 10 SC1 5 SC0 6 9 SD1 VSS 7 8 INT1 13 SDA PCA9543APW PCA9543BPW PCA9543CPW 12 SCL 11 INT 10 SC1 002aab179 002aab178 Fig 2. 14 VDD A0 Pin configuration for SO14 Fig 3. Pin configuration for TSSOP14 5.2 Pin description Table 3. Pin description Symbol Pin Description A0 1 address input 0 A1 2 address input 1 RESET 3 active LOW reset input INT0 4 active LOW interrupt input 0 SD0 5 serial data 0 SC0 6 serial clock 0 VSS 7 supply ground INT1 8 active LOW interrupt input 1 SD1 9 serial data 1 SC1 10 serial clock 1 INT 11 active LOW interrupt output SCL 12 serial clock line SDA 13 serial data line VDD 14 supply voltage PCA9543A_43B_43C_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 17 November 2008 4 of 23 PCA9543A/43B/43C NXP Semiconductors 2-channel I2C-bus switch with interrupt logic and reset 6. Functional description Refer to Figure 1 “Block diagram of PCA9543A/43B/43C”. 6.1 Device address Following a START condition, the bus master must output the address of the slave it is accessing. The address of the PCA9543A is shown in Figure 4. To conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW. 1 1 1 0 0 fixed A1 A0 R/W hardware selectable 002aab169 Fig 4. Slave address PCA9543A The last bit of the slave address defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation. The PCA9543B and PCA9543C are alternate address versions if needed for larger systems or to resolve address conflicts. The data sheet will reference the PCA9543A, but the PCA9543B and PCA9543C function identically except for the slave address. 1 1 1 1 0 fixed A1 A0 R/W 0 1 1 hardware selectable 0 fixed 002aab799 Fig 5. 0 A1 A0 R/W hardware selectable 002aab800 Slave address PCA9543B Fig 6. Slave address PCA9543C 6.2 Control register Following the successful acknowledgement of the slave address, the bus master will send a byte to the PCA9543A, which will be stored in the control register. If multiple bytes are received by the PCA9543A, it will save the last byte received. This register can be written and read via the I2C-bus. channel selection bits (read/write) interrupt bits (read only) 7 6 X X 5 4 INT INT 1 0 3 2 1 0 X X B1 B0 channel 0 channel 1 INT0 INT1 002aab181 Fig 7. Control register PCA9543A_43B_43C_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 17 November 2008 5 of 23 PCA9543A/43B/43C NXP Semiconductors 2-channel I2C-bus switch with interrupt logic and reset 6.2.1 Control register definition One or several SCx/SDx downstream pair, or channel, is selected by the contents of the control register. This register is written after the PCA9543A has been addressed. The 2 LSBs of the control byte are used to determine which channel is to be selected. When a channel is selected, the channel will become active after a STOP condition has been placed on the I2C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when the channel is made active, so that no false conditions are generated at the time of connection. Table 4. Control register: Write—channel selection; Read—channel status D7 D6 INT1 INT0 D3 D2 B1 X X X X X X X X X X X X X 0 0 0 0 0 0 0 1 0 B0 Command 0 channel 0 disabled 1 channel 0 enabled X 0 channel 1 disabled channel 1 enabled no channel selected; power-up/reset default state Remark: Channel 0 and channel 1 can be enabled at the same time. Care should be taken not to exceed the maximum bus capacitance. 6.2.2 Interrupt handling The PCA9543A provides 2 interrupt inputs, one for each channel, and one open-drain interrupt output. When an interrupt is generated by any device, it will be detected by the PCA9543A and the interrupt output will be driven LOW. The channel need not be active for detection of the interrupt. A bit is also set in the control register. Bit 4 and bit 5 of the control register corresponds to the INT0 and INT1 inputs of the PCA9543A, respectively. Therefore, if an interrupt is generated by any device connected to channel 1, the state of the interrupt inputs is loaded into the control register when a read is accomplished. Likewise, an interrupt on any device connected to channel 0 would cause bit 4 of the control register to be set on the read. The master can then address the PCA9543A and read the contents of the control register to determine which channel contains the device generating the interrupt. The master can then reconfigure the PCA9543A to select this channel, and locate the device generating the interrupt and clear it. It should be noted that more than one device can provide an interrupt on a channel, so it is up to the master to ensure that all devices on a channel are interrogated for an interrupt. The interrupt inputs may be used as general purpose inputs if the interrupt function is not required. If unused, interrupt input(s) must be connected to VDD through a pull-up resistor. Table 5. Control register: Read—interrupt 7 6 INT1 X X X X X 0 1 INT0 0 1 X 3 2 B1 B0 X X X X X X X X PCA9543A_43B_43C_5 Product data sheet Command no interrupt on channel 0 interrupt on channel 0 no interrupt on channel 1 interrupt on channel 1 © NXP B.V. 2008. All rights reserved. Rev. 05 — 17 November 2008 6 of 23 PCA9543A/43B/43C NXP Semiconductors 2-channel I2C-bus switch with interrupt logic and reset Remark: Two interrupts can be active at the same time. 6.3 RESET input The RESET input is an active LOW signal which may be used to recover from a bus fault condition. By asserting this signal LOW for a minimum of tw(rst)L, the PCA9543A will reset its registers and I2C-bus state machine and will deselect all channels. The RESET input must be connected to VDD through a pull-up resistor. 6.4 Power-on reset When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9543A in a reset condition until VDD has reached VPOR. At this point, the reset condition is released and the PCA9543A registers and I2C-bus state machine are initialized to their default states (all zeroes) causing all the channels to be deselected. Thereafter, VDD must be lowered below 0.2 V to reset the device. 6.5 Voltage translation The pass gate transistors of the PCA9543A are constructed such that the VDD voltage can be used to limit the maximum voltage that will be passed from one I2C-bus to another. 002aaa964 5.0 Vo(sw) (V) 4.0 (1) (2) 3.0 (3) 2.0 1.0 2.0 2.5 3.0 3.5 4.0 4.5 5.5 5.0 VDD (V) (1) maximum (2) typical (3) minimum Fig 8. Pass gate voltage versus supply voltage Figure 8 shows the voltage characteristics of the pass gate transistors (note that the graph was generated using the data specified in Section 10 “Static characteristics” of this data sheet). In order for the PCA9543A to act as a voltage translator, the Vo(sw) voltage should be equal to, or lower than the lowest bus voltage. For example, if the main bus was running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vo(sw) should be equal to or below 2.7 V to effectively clamp the downstream bus voltages. Looking at PCA9543A_43B_43C_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 17 November 2008 7 of 23 PCA9543A/43B/43C NXP Semiconductors 2-channel I2C-bus switch with interrupt logic and reset Figure 8, we see that Vo(sw)(max) will be at 2.7 V when the PCA9543A supply voltage is 3.5 V or lower, so the PCA9543A supply voltage could be set to 3.3 V. Pull-up resistors can then be used to bring the bus voltages to their appropriate levels (see Figure 15). More Information can be found in Application Note AN262: PCA954X family of I2C/SMBus multiplexers and switches. 7. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 7.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 9). SDA SCL data line stable; data valid Fig 9. change of data allowed mba607 Bit transfer 7.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 10). SDA SDA SCL SCL S P START condition STOP condition mba608 Fig 10. Definition of START and STOP conditions PCA9543A_43B_43C_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 17 November 2008 8 of 23 PCA9543A/43B/43C NXP Semiconductors 2-channel I2C-bus switch with interrupt logic and reset 7.3 System configuration A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 11). SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C-BUS MULTIPLEXER SLAVE 002aaa966 Fig 11. System configuration 7.4 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also, a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; setup and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master 1 S START condition 2 8 9 clock pulse for acknowledgement 002aaa987 Fig 12. Acknowledgement on the I2C-bus PCA9543A_43B_43C_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 17 November 2008 9 of 23 PCA9543A/43B/43C NXP Semiconductors 2-channel I2C-bus switch with interrupt logic and reset 7.5 Bus transactions Data is transmitted to the PCA9543A control register using the Write mode as shown in Figure 13. slave address SDA S 1 1 1 0 0 control register A1 A0 START condition 0 R/W A X X X X X X acknowledge from slave B1 B0 A P acknowledge from slave STOP condition 002aab182 Fig 13. Write control register Data is read from PCA9543A using the Read mode as shown in Figure 14. slave address SDA S 1 1 1 0 0 START condition last byte control register A1 A0 1 R/W A X X acknowledge from slave INT1 INT0 X X B1 B0 NA P no acknowledge from master STOP condition 002aab183 Fig 14. Read control register PCA9543A_43B_43C_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 17 November 2008 10 of 23 PCA9543A/43B/43C NXP Semiconductors 2-channel I2C-bus switch with interrupt logic and reset 8. Application design-in information VDD = 2.7 V to 5.5 V VDD = 3.3 V V = 2.7 V to 5.5 V see note (1) SDA SDA SD0 SCL SCL SC0 INT INT0 channel 0 V = 2.7 V to 5.5 V RESET see note (1) PCA9543A I2C/SMBus master A1 SD1 A0 SC1 VSS INT1 channel 1 002aab184 (1) If the device generating the interrupt has an open-drain output structure or can be 3-stated, a pull-up resistor is required. If the device generating the interrupt has a totem pole output structure and cannot be 3-stated, a pull-up resistor is not required. The interrupt inputs should not be left floating. Fig 15. Typical application 9. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS (ground = 0 V).[1] Symbol Parameter VDD Min Max Unit supply voltage −0.5 +7.0 V VI input voltage −0.5 +7.0 V II input current - ±20 mA IO output current - ±25 mA IDD supply current - ±100 mA ISS ground supply current - ±100 mA Ptot total power dissipation - 400 mW Tstg storage temperature −60 +150 °C Tamb ambient temperature −40 +85 °C [1] Conditions operating The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 125 °C. PCA9543A_43B_43C_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 17 November 2008 11 of 23 PCA9543A/43B/43C NXP Semiconductors 2-channel I2C-bus switch with interrupt logic and reset 10. Static characteristics Table 7. Static characteristics VDD = 2.3 V to 3.6 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. See Table 8 on page 13 for VDD = 4.5 V to 5.5 V.[1] Symbol Parameter Conditions Min Typ Max Unit 2.3 - 3.6 V Supply VDD supply voltage IDD supply current operating mode; VDD = 3.6 V; no load; VI = VDD or VSS; fSCL = 100 kHz - 40 100 µA Istb standby current Standby mode; VDD = 3.6 V; no load; VI = VDD or VSS; fSCL = 0 kHz - 0.2 1 µA VPOR power-on reset voltage no load; VI = VDD or VSS - 1.6 2.1 V [2] Input SCL; input/output SDA VIL LOW-level input voltage −0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 6 V IOL LOW-level output current VOL = 0.4 V 3 - - mA VOL = 0.6 V 6 - - mA IL leakage current VI = VDD or VSS −1 - +1 µA Ci input capacitance VI = VSS - 9 10 pF −0.5 - +0.3VDD V Select inputs A0, A1, INT0, INT1, RESET VIL LOW-level input voltage VIH HIGH-level input voltage 0.7VDD - VDD + 0.5 V ILI input leakage current VI = VDD or VSS −1 - +1 µA Ci input capacitance VI = VSS - 1.6 3 pF ON-state resistance VDD = 3.0 to 3.6 V; VO = 0.4 V; IO = 15 mA 5 11 30 Ω VDD = 2.3 V to 2.7 V; VO = 0.4 V; IO = 10 mA 7 16 55 Ω Vi(sw) = VDD = 3.3 V; Io(sw) = −100 µA - 1.9 - V Vi(sw) = VDD = 3.0 V to 3.6 V; Io(sw) = −100 µA 1.6 - 2.8 V Vi(sw) = VDD = 2.5 V; Io(sw) = −100 µA - 1.5 - V Vi(sw) = VDD = 2.5 V to 2.7 V; Io(sw) = −100 µA 1.1 - 2.0 V Pass gate Ron Vo(sw) switch output voltage IL leakage current VI = VDD or VSS −1 - +1 µA Cio input/output capacitance VI = VSS - 3 5 pF IOL LOW-level output current VOL = 0.4 V 3 - - mA IOH HIGH-level output current - - +100 µA INT output [1] For operation between published voltage ranges, refer to the worst-case parameter in both ranges. [2] VDD must be lowered to 0.2 V in order to reset part. PCA9543A_43B_43C_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 17 November 2008 12 of 23 PCA9543A/43B/43C NXP Semiconductors 2-channel I2C-bus switch with interrupt logic and reset Table 8. Static characteristics VDD = 4.5 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. See Table 7 on page 12 for VDD = 2.3 V to 3.6 V.[1] Symbol Parameter Conditions Min Typ Max Unit 4.5 - 5.5 V Supply VDD supply voltage IDD supply current Operating mode; VDD = 5.5 V; no load; VI = VDD or VSS; fSCL = 100 kHz - 25 100 µA Istb standby current Standby mode; VDD = 5.5 V; no load; VI = VDD or VSS; fSCL = 0 kHz - 0.2 1 µA VPOR power-on reset voltage no load; VI = VDD or VSS - 1.7 2.1 V −0.5 - +0.3VDD V [2] Input SCL; input/output SDA VIL LOW-level input voltage VIH HIGH-level input voltage IOL LOW-level output current 0.7VDD - 6 V VOL = 0.4 V 3 - - mA VOL = 0.6 V 6 - - mA IL leakage current VI = VDD or VSS −1 - +1 µA Ci input capacitance VI = VSS - 9 10 pF Select inputs A0, A1, INT0 to INT3, RESET VIL LOW-level input voltage −0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - VDD + 0.5 V ILI input leakage current VI = VDD or VSS −1 - +50 µA Ci input capacitance VI = VSS - 2 5 pF Ron on-state resistance VDD = 4.5 V to 5.5 V; VO = 0.4 V; IO = 15 mA 4 9 24 Ω Vo(sw) switch output voltage Vi(sw) = VDD = 5.0 V; Io(sw) = −100 µA - 3.6 - V Vi(sw) = VDD = 4.5 V to 5.5 V; Io(sw) = −100 µA 2.6 - 4.5 V Pass gate IL leakage current VI = VDD or VSS −1 - +100 µA Cio input/output capacitance VI = VSS - 3 5 pF IOL LOW-level output current VOL = 0.4 V 3 - - mA IOH HIGH-level output current - - +100 µA INT output [1] For operation between published voltage ranges, refer to the worst-case parameter in both ranges. [2] VDD must be lowered to 0.2 V in order to reset part. PCA9543A_43B_43C_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 17 November 2008 13 of 23 PCA9543A/43B/43C NXP Semiconductors 2-channel I2C-bus switch with interrupt logic and reset 11. Dynamic characteristics Table 9. Dynamic characteristics Symbol Parameter Standard-mode Fast-mode I2C-bus Unit I2C-bus Conditions from SDA to SDn, or SCL to SCn Min Max Min - 0.3[1] Max - 0.3[1] ns 0 100 0 400 4.7 - 1.3 - µs 4.0 - 0.6 - µs tPD propagation delay fSCL SCL clock frequency tBUF bus free time between a STOP and START condition tHD;STA hold time (repeated) START condition tLOW LOW period of the SCL clock 4.7 - 1.3 - µs tHIGH HIGH period of the SCL clock 4.0 - 0.6 - µs tSU;STA set-up time for a repeated START condition 4.7 - 0.6 - µs tSU;STO set-up time for STOP condition 4.0 - 0.6 - µs tHD;DAT data hold time 0[3] 3.45 0[3] 0.9 µs [2] kHz tSU;DAT data set-up time 250 - 100 - ns tr rise time of both SDA and SCL signals - 1000 20 + 0.1Cb[4] 300 ns tf fall time of both SDA and SCL signals - 300 20 + 0.1Cb[4] 300 µs Cb capacitive load for each bus line - 400 - 400 µs tSP pulse width of spikes that must be suppressed by the input filter - 50 - 50 ns tVD;DAT data valid time HIGH-to-LOW [5] - 1 - 1 µs LOW-to-HIGH [5] - 0.6 - 0.6 µs data valid acknowledge time - 1 - 1 µs tv(INTnN-INTN) valid time from INTn to INT signal - 4 - 4 µs tVD;ACK INT td(INTnN-INTN) delay time from INTn to INT inactive - 2 - 2 µs tw(rej)L LOW-level rejection time INTn inputs 1 - 1 - µs tw(rej)H HIGH-level rejection time INTn inputs 0.5 - 0.5 - µs 4 - 4 - ns SDA clear 500 - 500 - ns 0 - 0 - ns RESET tw(rst)L LOW-level reset time trst reset time tREC;STA recovery time to START condition [1] Pass gate propagation delay is calculated from the 20 Ω typical Ron and the 15 pF load capacitance. [2] Hold time (repeated) START condition. After this period, the first clock pulse is generated. [3] A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. [4] Cb = total capacitance of one bus line in pF. [5] Measurements taken with 1 kΩ pull-up resistor and 50 pF load. PCA9543A_43B_43C_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 17 November 2008 14 of 23 PCA9543A/43B/43C NXP Semiconductors 2-channel I2C-bus switch with interrupt logic and reset SDA tr tBUF tf tHD;STA tSP tLOW SCL tHD;STA P tSU;STA tHD;DAT S tHIGH tSU;DAT tSU;STO Sr P 002aaa986 Fig 16. Definition of timing on the I2C-bus ACK or read cycle START SCL SDA 30 % trst RESET 50 % 50 % 50 % tREC;STA tw(rst)L 002aac549 Fig 17. Definition of RESET timing protocol START condition (S) tSU;STA bit 7 MSB (A7) tLOW bit 6 (A6) tHIGH bit 0 (R/W) acknowledge (A) STOP condition (P) 1/f SCL SCL tBUF tr tf SDA tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO 002aab175 Rise and fall times refer to VIL and VIH. Fig 18. I2C-bus timing diagram PCA9543A_43B_43C_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 17 November 2008 15 of 23 PCA9543A/43B/43C NXP Semiconductors 2-channel I2C-bus switch with interrupt logic and reset 12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 19. Package outline SOT108-1 (SO14) PCA9543A_43B_43C_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 17 November 2008 16 of 23 PCA9543A/43B/43C NXP Semiconductors 2-channel I2C-bus switch with interrupt logic and reset TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 20. Package outline SOT402-1 (TSSOP14) PCA9543A_43B_43C_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 17 November 2008 17 of 23 PCA9543A/43B/43C NXP Semiconductors 2-channel I2C-bus switch with interrupt logic and reset 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 13.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities PCA9543A_43B_43C_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 17 November 2008 18 of 23 PCA9543A/43B/43C NXP Semiconductors 2-channel I2C-bus switch with interrupt logic and reset 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 21) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 10 and 11 Table 10. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 11. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 21. PCA9543A_43B_43C_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 17 November 2008 19 of 23 PCA9543A/43B/43C NXP Semiconductors 2-channel I2C-bus switch with interrupt logic and reset maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 21. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 14. Abbreviations Table 12. Abbreviations Acronym Description CDM Charged-Device Model ESD ElectroStatic Discharge HBM Human Body Model IC Integrated Circuit I2C-bus Inter-Integrated Circuit bus LSB Least Significant Bit MM Machine Model MSB Most Significant Bit PCB Printed-Circuit Board SMBus System Management Bus PCA9543A_43B_43C_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 17 November 2008 20 of 23 PCA9543A/43B/43C NXP Semiconductors 2-channel I2C-bus switch with interrupt logic and reset 15. Revision history Table 13. Revision history Document ID Release date PCA9543A_43B_43C_5 20081117 Modifications: • • Data sheet status Change notice Supersedes Product data sheet - PCA9543A_43B_43C_4 Section 6.3 “RESET input”: changed symbol from “tWL” to “tw(rst)L” Table 9 “Dynamic characteristics”, sub-section “INT”: – symbol tw(rej)L: changed Unit from “ns” to “µs” – symbol tw(rej)H: Min value (for both Standard-mode I2C-bus and Fast-mode I2C-bus) changed from “500 ns” to “0.5 µs” PCA9543A_43B_43C_4 20061020 Product data sheet - PCA9543A_3 PCA9543A_3 (9397 750 14316) 20050321 Product data sheet - PCA9543A_2 PCA9543A_2 (9397 750 13988) 20040929 Objective data sheet - PCA9543A_1 PCA9543A_1 (9397 750 13299) 20040728 Objective data sheet - - PCA9543A_43B_43C_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 17 November 2008 21 of 23 PCA9543A/43B/43C NXP Semiconductors 2-channel I2C-bus switch with interrupt logic and reset 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PCA9543A_43B_43C_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 17 November 2008 22 of 23 PCA9543A/43B/43C NXP Semiconductors 2-channel I2C-bus switch with interrupt logic and reset 18. Contents 1 2 3 3.1 4 5 5.1 5.2 6 6.1 6.2 6.2.1 6.2.2 6.3 6.4 6.5 7 7.1 7.2 7.3 7.4 7.5 8 9 10 11 12 13 13.1 13.2 13.3 13.4 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 5 Control register . . . . . . . . . . . . . . . . . . . . . . . . . 5 Control register definition . . . . . . . . . . . . . . . . . 6 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . 6 RESET input . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 7 Voltage translation . . . . . . . . . . . . . . . . . . . . . . 7 Characteristics of the I2C-bus. . . . . . . . . . . . . . 8 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 START and STOP conditions . . . . . . . . . . . . . . 8 System configuration . . . . . . . . . . . . . . . . . . . . 9 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 10 Application design-in information . . . . . . . . . 11 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11 Static characteristics. . . . . . . . . . . . . . . . . . . . 12 Dynamic characteristics . . . . . . . . . . . . . . . . . 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Soldering of SMD packages . . . . . . . . . . . . . . 18 Introduction to soldering . . . . . . . . . . . . . . . . . 18 Wave and reflow soldering . . . . . . . . . . . . . . . 18 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 18 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 19 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 21 Legal information. . . . . . . . . . . . . . . . . . . . . . . 22 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Contact information. . . . . . . . . . . . . . . . . . . . . 22 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 17 November 2008 Document identifier: PCA9543A_43B_43C_5