PCA9519 4-channel level translating I2C-bus/SMBus repeater Rev. 02 — 13 August 2007 Product data sheet 1. General description The PCA9519 is a 4-channel level translating I2C-bus/SMBus repeater that enables the processor low voltage 2-wire serial bus to interface with standard I2C-bus or SMBus I/O. While retaining all the operating modes and features of the I2C-bus system during the level shifts, it also permits extension of the I2C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus enabling the I2C-bus or SMBus maximum capacitance of 400 pF on the higher voltage side. The SDA and SCL pins are over-voltage tolerant and are high-impedance when the PCA9519 is unpowered. The port B drivers are compliant with SMBus I/O levels, while port A uses a current sensing mechanism to detect the input or output LOW signal which prevents bus lock-up. The port A uses a 1 mA current source for pull-up and a 200 Ω pull-down driver. This results in a LOW on port A accommodating smaller voltage swings. The output pull-down on the port A internal buffer LOW is set for approximately 0.2 V, while the input threshold of the internal buffer is set about 50 mV lower than that of the output voltage LOW. When the port A I/O is driven LOW internally, the LOW is not recognized as a LOW by the input. This prevents a lock-up condition from occurring. The output pull-down on the port B drives a hard LOW and the input level is set at 0.3 of SMBus or I2C-bus voltage level which enables port B to connect to any other I2C-bus device or buffer. The PCA9519 drivers are not enabled unless VCC(A) is above 0.8 V and VCC(B) is above 2.5 V. The enable (EN) pin can also be used to turn the drivers on and off under system control. Caution should be observed to only change the state of the EN pin when the bus is idle. 2. Features n 4-channel (4 SCL/SDA pairs), bidirectional buffer isolates capacitance and allows 400 pF on port B of the device n Voltage level translation from port A (1 V to VCC(B) − 1.5 V) to port B (3.0 V to 5.5 V) n Requires no external pull-up resistors on lower voltage port A n Active HIGH repeater enable input n Open-drain inputs/outputs n Lock-up free operation n Supports arbitration and clock stretching across the repeater n Accommodates Standard-mode and Fast-mode I2C-bus devices and multiple masters n Powered-off high-impedance I2C-bus pins n Operating supply voltage range of 1.0 V to VCC(B) − 1.5 V on port A, 3.0 V to 5.5 V on port B n 5 V tolerant B-side SCL and SDA and enable pins n 50 ns glitch filter on B-side input PCA9519 NXP Semiconductors 4-channel level translating I2C-bus/SMBus repeater n 0 Hz to 400 kHz clock frequency Remark: The maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater. n ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 n Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA n Packages offered: TSSOP20, HVQFN24 3. Ordering information Table 1. Ordering information Type number Topside mark Package Name Description Version PCA9519PW PCA9519 TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 PCA9519BS 9519 HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 × 4 × 0.85 mm SOT616-1 4. Functional diagram VCC(A) PCA9519 VCC(B) VCC(A) 1 mA A1 B1 VCC(A) 1 mA A2 B2 VCC(A) 1 mA A8 B8 EN 002aab643 GND Fig 1. Functional diagram of PCA9519 PCA9519_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 2 of 18 PCA9519 NXP Semiconductors 4-channel level translating I2C-bus/SMBus repeater 5. Pinning information 19 B1 20 n.c. 21 n.c. 22 GND 24 A1 terminal 1 index area 23 VCC(A) 5.1 Pinning EN 1 20 VCC(B) B1 2 19 A1 A2 1 18 B2 B2 3 18 A2 A3 2 17 B3 B3 4 17 A3 A4 3 B4 5 16 A4 A5 4 B5 6 15 A5 A6 5 14 B6 B6 7 14 A6 A7 6 13 B7 B7 8 13 A7 B8 9 12 A8 15 B5 B8 12 9 n.c. EN 11 8 VCC(B) 10 7 11 VCC(A) A8 GND 10 n.c. PCA9519PW 16 B4 PCA9519BS 002aab641 Transparent top view 002aab640 Fig 2. Pin configuration for TSSOP20 Fig 3. Pin configuration for HVQFN24 5.2 Pin description Table 2. Symbol EN Pin description Pin Description TSSOP20 HVQFN24 1 11 ground (0 V) enable input (active HIGH) GND 10 22[1] VCC(A) 11 23 port A power supply A1 19 24 A1 port (low voltage side)[2] A2 18 1 A2 port (low voltage side)[2] A3 17 2 A3 port (low voltage side)[2] A4 16 3 A4 port (low voltage side)[2] A5 15 4 A5 port (low voltage side)[2] A6 14 5 A6 port (low voltage side)[2] A7 13 6 A7 port (low voltage side)[2] A8 12 7 A8 port (low voltage side)[2] VCC(B) 20 10 port B power supply B8 9 12 B8 port (SMBus/I2C-bus side)[2] B7 8 13 B7 port (SMBus/I2C-bus side)[2] B6 7 14 B6 port (SMBus/I2C-bus side)[2] B5 6 15 B5 port (SMBus/I2C-bus side)[2] B4 5 16 B4 port (SMBus/I2C-bus side)[2] B3 4 17 B3 port (SMBus/I2C-bus side)[2] B2 3 18 B2 port (SMBus/I2C-bus side)[2] PCA9519_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 3 of 18 PCA9519 NXP Semiconductors 4-channel level translating I2C-bus/SMBus repeater Table 2. Symbol Pin description …continued Pin Description TSSOP20 HVQFN24 B1 2 19 n.c. - 8, 9, 20, 21 B1 port (SMBus/I2C-bus side)[2] [1] HVQFN package die supply ground is connected to both the GND pin and the exposed center pad. The GND pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region. [2] Port A and port B can be used for either SCL or SDA. 6. Functional description Refer to Figure 1 “Functional diagram of PCA9519”. The PCA9519 enables I2C-bus or SMBus translation down to VCC(A) as low as 1.0 V without degradation of system performance. The PCA9519 contains 8 bidirectional open-drain buffers specifically designed to support up-translation/down-translation between the low voltage and 3.3 V SMBus or 5 V I2C-bus. Port B I/Os are over-voltage tolerant to 5.5 V even when the device is unpowered. The PCA9519 includes a power-up circuit that keeps the output drivers turned off until VCC(B) is above 2.5 V and the VCC(A) is above 0.8 V. VCC(B) and VCC(A) can be applied in any sequence at power-up. After power-up and with the EN pin HIGH, a LOW level on the port A (below approximately 0.15 V) turns the corresponding port B driver (either SDA or SCL) on and drives the port B down to about 0 V. When port A rises above approximately 0.15 V, the port B pull-down driver is turned off and the external pull-up resistor pulls the pin HIGH. When the port B falls first and goes below 0.3VCC(B), the port A driver is turned on and the port A pulls down to 0.2 V (typical). The port B pull-down is not enabled unless the port A voltage goes below VILc. If the port A low voltage goes below VILc, the port B pull-down driver is enabled until the port A rises above approximately 0.15 V (VILc), then the port B, if not externally driven LOW, will continue to rise being pulled up by the external pull-up resistor. Remark: Ground offset between the PCA9519 ground and the ground of devices on port A of the PCA9519 must be avoided. The reason for this cautionary remark is that a CMOS/NMOS open-drain capable of sinking 3 mA of current at 0.4 V will have an output resistance of 133 Ω or less (R = E / I). Such a driver will share enough current with the port A output pull-down of the PCA9519 to be seen as a LOW as long as the ground offset is zero. If the ground offset is greater than 0 V, then the driver resistance must be less. Since VILc can be as low as 90 mV at cold temperatures and the low end of the current distribution, the maximum ground offset should not exceed 50 mV. Bus repeaters that use an output offset are not interoperable with port A of the PCA9519 as their output LOW levels will not be recognized by the PCA9519 as a LOW. If the PCA9519 is placed in an application where the VIL of the port A of the PCA9519 does not go below its VILc it will pull the port B LOW initially when the port A input transitions LOW but port B will return HIGH, so it will not reproduce the port A input on port B. Such applications should be avoided. PCA9519_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 4 of 18 PCA9519 NXP Semiconductors 4-channel level translating I2C-bus/SMBus repeater Port B is interoperable with all I2C-bus slaves, masters, and repeaters and includes the 50 ns glitch filter. 6.1 Enable The EN pin is active HIGH and allows the user to select when the repeater is active. This can be used to isolate a badly behaved slave on power-up until after the system power-up reset. It should never change state during an I2C-bus operation because disabling during a bus operation will hang the bus and enabling part way through a bus cycle could confuse the I2C-bus parts being enabled. The enable pin should only change state when the bus and the repeater port are in an idle state to prevent system failures. 6.2 I2C-bus systems As with the standard I2C-bus system, pull-up resistors are required to provide the logic HIGH levels on the buffered bus (standard open-collector configuration of the I2C-bus). The size of these pull-up resistors depends on the system. Each of the port A I/Os has an internal pull-up current source and does not require the external pull-up resistor. The port B is designed to work with Standard mode and Fast mode I2C-bus devices in addition to SMBus devices. Standard mode I2C-bus devices only specify 3 mA output drive; this limits the termination current to 3 mA in a generic I2C-bus system where Standard mode devices and multiple masters are possible. Under certain conditions higher termination currents can be used. 7. Application design-in information A typical application is shown in Figure 4. In this example, the CPU is running on a 1.1 V I2C-bus while the master is connected to a 3.3 V bus. Both buses run at 400 kHz. Master devices can be placed on either bus. 1.1 V 3.3 V 10 kΩ 10 kΩ VCC(A) VCC(B) A1 SDA A2 SCL B1 SDA B2 SCL PCA9519 1.1 V CPU 10 kΩ A8 MASTER 400 kHz B8 EN bus A bus B 002aab642 Fig 4. Typical application When port B of the PCA9519 is pulled LOW by a driver on the I2C-bus, a CMOS hysteresis detects the falling edge when it goes below 0.3VCC(B) and causes the internal driver on port A to turn on, causing port A to pull down to about 0.2 V. When port A of the PCA9519 falls, first a comparator detects the falling edge and causes the internal driver PCA9519_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 5 of 18 PCA9519 NXP Semiconductors 4-channel level translating I2C-bus/SMBus repeater on port B to turn on and pull the port B pin down to ground. In order to illustrate what would be seen in a typical application, refer to Figure 5 and Figure 6. If the bus master in Figure 4 were to write to the slave through the PCA9519, waveforms shown in Figure 5 would be observed on the B bus. This looks like a normal I2C-bus transmission. On the port A bus of the PCA9519, the clock and data lines would have a positive offset from ground equal to the VOL of the PCA9519. After the 8th clock pulse, the data line will be pulled to the VOL of the master device, which is very close to ground in this example. At the end of the acknowledge, the level rises only to the LOW level set by the driver in the PCA9519 for a short delay while the port B bus rises above 0.5VCC(B), then it continues HIGH. It is important to note that any arbitration or clock stretching events require that the LOW level on the port A bus at the input of the PCA9519 (VIL) is below VILc to be recognized by the PCA9519 and then transmitted to the port B bus. 9th clock pulse acknowledge SCL SDA 002aab644 Fig 5. Bus B SMBus/I2C-bus waveform 9th clock pulse acknowledge SCL SDA VOL of PCA9519 002aab645 VOL of master Fig 6. Bus A lower voltage waveform PCA9519_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 6 of 18 PCA9519 NXP Semiconductors 4-channel level translating I2C-bus/SMBus repeater 8. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VCC(B) supply voltage port B VCC(A) supply voltage port A VI/O voltage on an input/output pin Conditions Min Max Unit −0.5 +6 V −0.5 +6 V port A −0.5 +6 V port B; enable pin (EN) −0.5 +6 V II/O input/output current - ±20 mA II input current - ±20 mA Ptot total power dissipation - 100 mW Tstg storage temperature −65 +150 °C Tamb ambient temperature operating in free air −40 +85 °C Tj junction temperature - 125 °C Tsp solder point temperature 10 s max. - 300 °C 9. Static characteristics Table 4. Static characteristics GND = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Supplies VCC(B) supply voltage port B 3.0 - 5.5 V VCC(A) supply voltage port A 1.0 - VCC(B) − 1.5 V ICC(A) supply current port A all port A static HIGH 1 2.1 3.6 mA all port A static LOW 5 11.6 20 mA all port B static HIGH 2 3.3 4.5 mA ICC(B) supply current port B Input and output of port A (A1 to A8) VIH VIL HIGH-level input voltage port A LOW-level input voltage port A VILc contention LOW-level input voltage VIK input clamping voltage IL = −18 mA ILI input leakage current VI = VCC(A) IIL 0.7VCC(A) - VCC(A) V [2] −0.5 - +0.3 V [2] −0.5 +0.15 - V −1.5 - −0.5 V - - ±1 µA LOW-level input current [3] −1.5 −1 −0.45 mA [4] - 0.2 0.35 V [5] - 50 - mV - - 10 µA - 6 7 pF VOL LOW-level output voltage VOL−VILc difference between LOW-level output and LOW-level input voltage contention port A ILOH HIGH-level output leakage current VO = 1.1 V Cio input/output capacitance PCA9519_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 7 of 18 PCA9519 NXP Semiconductors 4-channel level translating I2C-bus/SMBus repeater Table 4. Static characteristics …continued GND = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit 0.7VCC(B) - VCC(B) V Input and output of port B (B1 to B8) VIH HIGH-level input voltage VIL LOW-level input voltage −0.5 - +0.3VCC(B) V VIK input clamping voltage IL = −18 mA −1.5 - −0.5 V ILI input leakage current VI = 3.6 V −1.0 - +1.0 µA IIL LOW-level input current VI = 0.2 V - - 10 µA VOL LOW-level output voltage IOL = 6 mA - 0.1 0.2 V ILOH HIGH-level output leakage current VO = 3.6 V - - 10 µA Cio input/output capacitance - 6 7 pF Enable VIL LOW-level input voltage −0.5 - +0.1VCC(A) V VIH HIGH-level input voltage 0.9VCC(A) - VCC(B) V IIL(EN) LOW-level input current on pin EN −1 - +1 µA ILI input leakage current −1 - +1 µA Ci input capacitance - 2 3 pF VI = 0.2 V, EN; VCC = 3.6 V VI = 3.0 V or 0 V [1] Typical values with VCC(A) = 1.1 V, VCC(B) = 5.0 V. [2] VIL specification is for the falling edge seen by the port A input. VILc is for the static LOW levels seen by the port A input resulting in port B output staying LOW. [3] The port A current source has a typical value of about 1 mA, but varies with both VCC(A) and VCC(B). Below VCC(A) of about 0.7 V the port A current source current drops to 0 mA. The current source current dropping across the internal pull-down driver resistance of about 200 Ω defines the VOL. [4] As long as the chip ground is common with the input ground reference the driver resistance may be as large as 120 Ω. However, ground offset will rapidly decrease the maximum allowed driver resistance. [5] Guaranteed by design. PCA9519_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 8 of 18 PCA9519 NXP Semiconductors 4-channel level translating I2C-bus/SMBus repeater 10. Dynamic characteristics Table 5. Dynamic characteristics Symbol Parameter Conditions Min Typ Max Unit VCC(A) = 1.1 V; VCC(B) = 3.3 V LOW-to-HIGH propagation delay tPLH port B to port A [1] 69 109 216 ns tPHL HIGH-to-LOW propagation delay port B to port A [1] 63 86 140 ns tTLH LOW to HIGH output transition time port A [1] 14 22 96 ns port A [1] 5 8.1 16 ns port A to port B [1] −69 −91 −139 ns 91 153 226 ns 73 122 183 ns - 61 - ns 15 24 40 ns HIGH to LOW output transition time tTHL LOW-to-HIGH propagation delay tPLH tPLH2 LOW to HIGH propagation delay 2 port A to port B; measured from the 50 % of initial LOW on port A to 1.5 V rising on port B [1] tPHL HIGH-to-LOW propagation delay port A to port B [1] tTLH LOW to HIGH output transition time port B [1][2] tTHL HIGH to LOW output transition time port B [1] tsu set-up time EN HIGH before START condition 100 - - ns th hold time EN HIGH after STOP condition 100 - - ns VCC(A) = 1.9 V; VCC(B) = 5.0 V LOW-to-HIGH propagation delay tPLH HIGH-to-LOW propagation delay tPHL LOW to HIGH output transition time tTLH port B to port A [1] 69 105 216 ns port B to port A [1] 63 86 140 ns port A [1] 14 27 96 ns tTHL HIGH to LOW output transition time port A [1] 5 8 35 ns tPLH LOW-to-HIGH propagation delay port A to port B [1] −69 −89 −139 ns tPLH2 LOW to HIGH propagation delay 2 port A to port B; measured from the 50 % of initial LOW on port A to 1.5 V rising on port B [1] 91 131 226 ns tPHL HIGH-to-LOW propagation delay port A to port B [1] 73 99 183 ns - 65 - ns 15 31 40 ns LOW to HIGH output transition time tTLH port B [1][2] [1] tTHL HIGH to LOW output transition time port B tsu set-up time EN HIGH before START condition 100 - - ns th hold time EN HIGH after STOP condition 100 - - ns [1] Load capacitance = 50 pF; load resistance on port B = 1.35 kΩ. [2] Value is determined by RC time constant of bus line. PCA9519_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 9 of 18 PCA9519 NXP Semiconductors 4-channel level translating I2C-bus/SMBus repeater 10.1 AC waveforms VCC(B) input 0.5VCC(B) VCC(A) 0.5VCC(B) input 0.5VCC(A) 0.5VCC(A) 0.1 V tPHL output 70 % tPHL tPLH 0.5VCC(A) 0.5VCC(A) 30 % 30 % VCC(A) 70 % tTHL output 70 % VOL tTLH tPLH 0.5VCC(B) 0.5VCC(B) 30 % 30 % tTHL VCC(B) tTLH 002aab646 Fig 7. Propagation delay and transition times; port B to port A 70 % 002aab647 Fig 8. Propagation delay and transition times; port A to port B input port A 50 % of initial value 0.5VCC(B) output port B tPLH2 002aab648 Fig 9. Propagation delay from port A’s external driver switching off to the port B LOW-to-HIGH transition; port A to port B 11. Test information VCC(B) VCC(B) VCC(A) PULSE GENERATOR VI RL VO DUT CL RT 002aab649 RL = load resistor; 1.35 kΩ on port B CL = load capacitance includes jig and probe capacitance; 50 pF RT = termination resistance should be equal to Zo of pulse generators Fig 10. Test circuit for open-drain outputs PCA9519_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 10 of 18 PCA9519 NXP Semiconductors 4-channel level translating I2C-bus/SMBus repeater 12. Package outline TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 11. Package outline SOT360-1 (TSSOP20) PCA9519_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 11 of 18 PCA9519 NXP Semiconductors 4-channel level translating I2C-bus/SMBus repeater HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm A B D SOT616-1 terminal 1 index area A A1 E c detail X e1 C 1/2 e e 12 y y1 C v M C A B w M C b 7 L 13 6 e e2 Eh 1/2 e 1 18 terminal 1 index area 24 19 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 e2 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 4.1 3.9 2.25 1.95 4.1 3.9 2.25 1.95 0.5 2.5 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT616-1 --- MO-220 --- EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-22 Fig 12. Package outline SOT616-1 (HVQFN24) PCA9519_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 12 of 18 PCA9519 NXP Semiconductors 4-channel level translating I2C-bus/SMBus repeater 13. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering 13.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities PCA9519_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 13 of 18 PCA9519 NXP Semiconductors 4-channel level translating I2C-bus/SMBus repeater 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 13) than a PbSn process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 6 and 7 Table 6. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 7. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 13. PCA9519_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 14 of 18 PCA9519 NXP Semiconductors 4-channel level translating I2C-bus/SMBus repeater maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 13. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 14. Abbreviations Table 8. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor CPU Central Processing Unit DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model I/O Input/Output I2C-bus Inter-Integrated Circuit Bus MM Machine Model NMOS Negative-channel Metal Oxide Semiconductor PCB Printed-Circuit Board RC Resistor Capacitor network SMBus System Management Bus PCA9519_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 15 of 18 PCA9519 NXP Semiconductors 4-channel level translating I2C-bus/SMBus repeater 15. Revision history Table 9. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9519_2 20070813 Product data sheet - PCA9519_1 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Section 2 “Features”: – 2nd bullet item: changed “VCC(B) − 1 V” to “VCC(B) − 1.5 V” – 10th bullet item: changed “VCC(B) − 1 V” to “VCC(B) − 1.5 V” – added new 12th bullet item • PCA9519_1 Table 4 “Static characteristics”, sub-section “Supplies”: changed maximum VCC(A) from “VCC(B) − 1 V” to “VCC(B) − 1.5 V”. 20060622 Objective data sheet - PCA9519_2 Product data sheet - © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 16 of 18 PCA9519 NXP Semiconductors 4-channel level translating I2C-bus/SMBus repeater 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 17. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] PCA9519_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 17 of 18 PCA9519 NXP Semiconductors 4-channel level translating I2C-bus/SMBus repeater 18. Contents 1 2 3 4 5 5.1 5.2 6 6.1 6.2 7 8 9 10 10.1 11 12 13 13.1 13.2 13.3 13.4 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 I2C-bus systems . . . . . . . . . . . . . . . . . . . . . . . . 5 Application design-in information . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 10 Test information . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Introduction to soldering . . . . . . . . . . . . . . . . . 13 Wave and reflow soldering . . . . . . . . . . . . . . . 13 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 13 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 13 August 2007 Document identifier: PCA9519_2