INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT7597 8-bit shift register with input latches Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 8-bit shift register with input latches 74HC/HCT7597 The 74HC/HCT7597 both consist of an 8-bit storage latch feeding a parallel-in, serial-out 8-bit shift register. FEATURES • 8-bit parallel input latches When LE is LOW, data at the Dn inputs enter the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D-input changes. • Shift register has direct overriding load and clear • Output capability: standard • ICC category: MSI When LE is HIGH the latches store the information that was present at the D-inputs, a set-up time preceding the LOW-to-HIGH transition of LE. GENERAL DESCRIPTION The 74HC/HCT7597 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The shift register has a positive edge-triggered clock, direct load (from storage) and clear inputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH propagation delay HCT CL = 15 pF; VCC = 5 V SHCP to Q 15 17 ns LE to Q 22 27 ns PL to Q 20 23 ns D7 to Q 20 24 ns fmax maximum clock frequency SHCP 99 79 MHz CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per package 29 30 pF notes 1, 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF; VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. December 1990 2 Philips Semiconductors Product specification 8-bit shift register with input latches 74HC/HCT7597 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 8 GND ground (0 V) 9 Q serial data output 10 MR asynchronous reset input (active LOW) 11 SHCP shift clock input (LOW-to-HIGH, edge-triggered) 12 LE latch enable input (active LOW) 13 PL parallel load input (active LOW) 14 DS serial data input 15, 1, 2, 3, 4, 5, 6, 7 D0 to D7 parallel data inputs 16 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification 8-bit shift register with input latches 74HC/HCT7597 FUNCTION TABLE LE SHCP PL MR FUNCTION L X X X data enabled to input latches (transparent) H X X X data stored into latches (non-transparent) X X L H data transferred from input latches to shift register X X L L invalid logic, state of shift register indeterminate when signals removed X X H L shift register cleared X ↑ H H shift register clocked Qn = Qn-1, Q0 = DS Notes 1. H = HIGH voltage level L = LOW voltage level X = don’t care ↑ = LOW-to-HIGH CP transition Fig.4 Functional diagram. December 1990 4 Philips Semiconductors Product specification 8-bit shift register with input latches 74HC/HCT7597 Fig.5 Logic diagram. December 1990 5 Philips Semiconductors Product specification 8-bit shift register with input latches 74HC/HCT7597 Fig.6 Timing diagram. December 1990 6 Philips Semiconductors Product specification 8-bit shift register with input latches 74HC/HCT7597 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 −40 to +85 min. typ. max. min. max. −40 to +125 min. UNIT V CC WAVEFORMS (V) max. tPHL/ tPLH propagation delay SHCP to Q 50 18 14 175 35 30 220 44 37 265 53 45 ns 2.0 4.5 6.0 Fig.7 tPHL propagation delay MR to Q 52 19 15 175 35 30 220 44 37 265 53 45 ns 2.0 4.5 6.0 Fig.7 tPHL/ tPLH propagation delay LE to Q 72 26 21 250 50 43 315 63 54 375 75 64 ns 2.0 4.5 6.0 Fig.7 tPHL/ tPLH propagation delay PL to Q 63 23 18 190 38 32 240 48 41 285 57 48 ns 2.0 4.5 6.0 Fig.7 tPHL/ tPLH propagation delay D7 to Q 63 23 18 190 38 32 240 48 41 285 57 48 ns 2.0 4.5 6.0 Fig.7 tTHL/ tTLH output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 Fig.7 tW SHCP pulse width HIGH or LOW 80 16 14 11 4 3 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.7 tW LE pulse width LOW 80 16 14 11 4 3 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.7 tW MR pulse width LOW 80 16 14 17 6 5 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.7 tW PL pulse width LOW 80 16 14 17 6 5 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.7 trem removal time MR to SHCP 50 10 9 −3 −1 −1 65 13 11 75 15 13 ns 2.0 4.5 6.0 Fig.7 December 1990 7 Philips Semiconductors Product specification 8-bit shift register with input latches 74HC/HCT7597 Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 −40 to +85 −40 to +125 min. typ. max. min. max. min. UNIT V CC WAVEFORMS (V) max. trem removal time MR to PL 100 20 17 22 8 6 125 25 21 150 30 26 ns 2.0 4.5 6.0 Fig.7 tsu set-up time Dn to LE 80 16 14 6 2 2 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.7 tsu set-up time DS to SHCP 80 16 14 11 4 3 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.7 tsu set-up time PL to SHCP 80 16 14 8 3 2 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.7 th hold time Dn to LE 4 4 4 −3 −1 −1 4 4 4 4 4 4 ns 2.0 4.5 6.0 Fig.7 th hold time DS to SHCP 2 2 2 −8 −3 −2 2 2 2 2 2 2 ns 2.0 4.5 6.0 Fig.7 th hold time PL to SHCP 2 2 2 −8 −3 −2 2 2 2 2 2 2 ns 2.0 4.5 6.0 Fig.7 fmax maximum pulse frequency 6.0 SHCP 30 35 30 90 107 4.8 24 28 4.0 20 24 MHz 2.0 4.5 6.0 Fig.7 December 1990 8 Philips Semiconductors Product specification 8-bit shift register with input latches 74HC/HCT7597 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT DS Dn PL, MR LE, SHCP 0.25 0.40 1.50 1.50 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 −40 to +85 −40 to +125 min. typ. max. min. max. min. UNIT VCC WAVEFORMS (V) max. tPHL/ tPLH propagation delay SHCP to Q 20 35 44 53 ns 4.5 Fig.7 tPHL propagation delay MR to Q 25 42 53 63 ns 4.5 Fig.7 tPHL/ tPLH propagation delay LE to Q 31 53 66 80 ns 4.5 Fig.7 tPHL/ tPLH propagation delay PL to Q 27 46 58 69 ns 4.5 Fig.7 tPHL/ tPLH propagation delay D7 to Q 28 49 61 74 ns 4.5 Fig.7 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.7 tW SHCP pulse width HIGH or LOW 16 6 20 24 ns 4.5 Fig.7 tW LE pulse width LOW 16 7 20 24 ns 4.5 Fig.7 tW MR pulse width LOW 20 11 25 30 ns 4.5 Fig.7 tW PL pulse width LOW 18 9 23 27 ns 4.5 Fig.7 trem removal time MR to SHCP 10 −1 13 15 ns 4.5 Fig.7 trem removal time MR to PL 20 9 25 30 ns 4.5 Fig.7 December 1990 9 Philips Semiconductors Product specification 8-bit shift register with input latches 74HC/HCT7597 Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 −40 to +85 −40 to +125 min. typ. max. min. max. min. UNIT VCC WAVEFORMS (V) max. tsu set-up time Dn to LE 16 5 20 24 ns 4.5 Fig.7 tsu set-up time DS to SHCP 16 5 20 24 ns 4.5 Fig.7 tsu set-up time PL to SHCP 16 3 20 24 ns 4.5 Fig.7 th hold time Dn to LE 4 −2 4 4 ns 4.5 Fig.7 th hold time DS to SHCP 2 −4 2 2 ns 4.5 Fig.7 th hold time PL to SHCP 2 −3 2 2 ns 4.5 Fig.7 fmax maximum pulse frequency 30 SHCP 72 24 20 MHz 4.5 Fig.7 December 1990 10 Philips Semiconductors Product specification 8-bit shift register with input latches 74HC/HCT7597 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Fig.8 Waveforms showing the SHCP input to Q output propagation delays, the SHCP pulse width and maximum clock pulse frequency. Waveforms showing the MR input to Q output propagation delay and the MR pulse width. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.9 Fig.10 Waveforms showing the PL input to Q output propagation delays, PL pulse width and output transition times. Waveforms showing the LE input to Q output propagation delays and the LE pulse width. December 1990 11 Philips Semiconductors Product specification 8-bit shift register with input latches 74HC/HCT7597 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.11 Waveforms showing the D7 input to Q output propagation delays and output transition times. Fig.12 Waveforms showing the MR input to PL, SHCP removal times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.14 Waveforms showing set-up and hold times for PL input to SHCP input. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.13 Waveforms showing hold and set-up times for DS, Dn inputs to SHCP, LE inputs. December 1990 PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. 12