INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT354 8-input multiplexer/register with transparent latches; 3-state Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 8-input multiplexer/register with transparent latches; 3-state 74HC/HCT354 (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Transparent data latches The 74HC/HCT354 data selectors/multiplexers contain full on-chip binary decoding, to select one-of-eight data sources. The data select address is stored in transparent latches that are enabled by a LOW on the latch enable input (LE). • Transparent address latch • Easily expanding • Complementary outputs • Output capability: bus driver • ICC category: MSI The transparent 8-bit data latches are enabled when the active LOW data enable input (E) is LOW. When the output enable input OE1 = HIGH, OE2 = HIGH or OE3 = LOW, the outputs go to the high impedance OFF-state. Operation of these output enable inputs does not affect the state of the latches. GENERAL DESCRIPTION The 74HC/HCT354 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH propagation delay HCT CL = 15 pF; VCC = 5 V Dn, E to Y, Y 20 22 ns Sn, LE to Y, Y 24 27 ns CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per latch 68 71 pF notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. December 1990 2 Philips Semiconductors Product specification 8-input multiplexer/register with transparent latches; 3-state 74HC/HCT354 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 8, 7, 6, 5, 4, 3, 2, 1 D0 to D7 data inputs 9 E data enable input (active LOW) 10 GND ground (0 V) 11 LE address latch enable inputs (active LOW) 14, 13, 12 S0, S1, S2 select inputs 15, 16 OE1, OE2 output enable input (active LOW) 17 OE3 output enable input (active HIGH) 18 Y 3-state multiplexer output (active LOW) 19 Y 3-state multiplexer output (active HIGH) 20 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification 8-input multiplexer/register with transparent latches; 3-state 74HC/HCT354 FUNCTION TABLE INPUTS ADDRESS (1) S2 S1 OUTPUTS OUTPUT ENABLE S0 E OE1 OE2 OE3 DESCRIPTION Y Y X X X X X X X X X X X X H X X X H X X X L Z Z Z Z Z Z L L L L L L H H L H L H L L L L L L L L L L L L H H H H D0 D1 D2 D3 D0 D1 D2 D3 H H H H L L H H L H L H L L L L L L L L L L L L H H H H D4 D5 D6 D7 D4 D5 D6 D7 L L L L L L H H L H L H H H H H L L L L L L L L H H H H D0n D1n D2n D3n D0n D1n D2n D3n H H H H L L H H L H L H H H H H L L L L L L L L H H H H D4n D5n D6n D7n D4n D5n D6n D7n Notes 1. This column shows the input address set-up with LE = LOW (address latch is transparent). 2. D0 to D7 = data at inputs D0 to D7 D0n to D7n = data at inputs D0 to D7 before the most recent LOW-to-HIGH transition of E H = HIGH voltage level L = LOW voltage level X = don’t care Z = high impedance OFF-state December 1990 4 outputs in high impedance OFF-state data latch is transparent data is latched Philips Semiconductors Product specification 8-input multiplexer/register with transparent latches; 3-state 74HC/HCT354 Fig.4 Functional diagram. December 1990 5 Philips Semiconductors Product specification 8-input multiplexer/register with transparent latches; 3-state 74HC/HCT354 Fig.5 Logic diagram. December 1990 6 Philips Semiconductors Product specification 8-input multiplexer/register with transparent latches; 3-state 74HC/HCT354 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 min. −40 to +85 typ. max. min. max. −40 to +125 min. WAVEFORMS UNIT V CC (V) max. tPHL/ tPLH propagation delay Dn to Y, Y 61 22 18 210 42 36 265 53 45 315 63 54 ns 2.0 4.5 6.0 Fig.7 tPHL/ tPLH propagation delay E to Y, Y 63 23 18 250 50 43 315 63 54 375 75 64 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay Sn to Y, Y 77 28 22 260 52 44 325 65 55 390 78 66 ns 2.0 4.5 6.0 Fig.8 tPHL/ tPLH propagation delay LE to Y, Y 77 28 22 290 58 49 365 73 62 435 87 74 ns 2.0 4.5 6.0 Fig.9 tPZH/ tPZL 3-state output enable time OEn to Y, Y 39 14 11 125 25 21 155 31 26 190 38 32 ns 2.0 4.5 6.0 Fig.10 tPZH/ tPZL 3-state output enable time OE3 to Y, Y 44 16 13 135 27 23 170 34 29 205 41 35 ns 2.0 4.5 6.0 Fig.10 tPHZ/ tPLZ 3-state output disable time OEn to Y, Y 50 18 14 155 31 26 195 39 33 235 47 40 ns 2.0 4.5 6.0 Fig.10 tPHZ/ tPLZ 3-state output disable time OE3 to Y, Y 55 20 16 155 31 26 195 39 33 235 47 40 ns 2.0 4.5 6.0 Fig.10 tTHL/ tTLH output transition time 14 5 4 60 12 10 75 15 13 90 18 15 ns 2.0 4.5 6.0 Figs 7, 8 and 9 tW data enable pulse width E LOW 80 16 14 17 6 5 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.6 tW latch enable pulse width LE 80 LOW 16 14 17 6 5 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.9 December 1990 7 Philips Semiconductors Product specification 8-input multiplexer/register with transparent latches; 3-state 74HC/HCT354 Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 −40 to +85 −40 to +125 min. typ. max. min. max. min. UNIT V WAVEFORMS CC (V) max. tsu set-up time Dn to E 50 10 9 11 4 3 65 13 11 75 15 13 ns 2.0 4.5 6.0 Fig.10 tsu set-up time Sn to LE 50 10 9 14 5 4 65 13 11 75 15 13 ns 2.0 4.5 6.0 Fig.10 th hold time Dn to E 5 5 5 −6 −2 −2 5 5 5 5 5 5 ns 2.0 4.5 6.0 Fig.11 th hold time Sn to LE 5 5 5 −8 −3 −2 5 5 5 5 5 5 ns 2.0 4.5 6.0 Fig.10 December 1990 8 Philips Semiconductors Product specification 8-input multiplexer/register with transparent latches; 3-state 74HC/HCT354 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT Dn, Sn OE3 LE E, OEn 0.2 0.25 0.5 1.0 December 1990 9 Philips Semiconductors Product specification 8-input multiplexer/register with transparent latches; 3-state 74HC/HCT354 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min. −40 to +85 typ. max. min. max. −40 to +125 min. WAVEFORMS UNIT V CC (V) max. tPHL/ tPLH propagation delay Dn to Y, Y 25 47 59 71 ns 4.5 Fig.7 tPHL/ tPLH propagation delay E to Y, Y 26 54 68 81 ns 4.5 Fig.6 tPHL/ tPLH propagation delay Sn to Y, Y 30 59 74 89 ns 4.5 Fig.8 tPHL/ tPLH propagation delay LE to Y, Y 31 63 79 95 ns 4.5 Fig.9 tPZH/ tPZL 3-state output enable time OEn to Y, Y 18 34 43 51 ns 4.5 Fig.10 tPZH/ tPZL 3-state output enable time OE3 to Y, Y 18 34 43 51 ns 4.5 Fig.10 tPHZ/ tPLZ 3-state output disable time OEn to Y, Y 18 33 41 50 ns 4.5 Fig.10 tPHZ/ tPLZ 3-state output disable time OE3 to Y, Y 21 39 49 59 ns 4.5 Fig.10 tTHL/ tTLH output transition time 5 12 15 18 ns 4.5 Figs 7, 8 and 9 tW data enable pulse width E LOW 16 6 20 24 ns 4.5 Fig.6 tW latch enable pulse width LE LOW 16 6 20 24 ns 4.5 Fig.9 tsu set-up time Dn to E 10 4 13 15 ns 4.5 Fig.11 tsu set-up time Sn to LE 10 5 13 15 ns 4.5 Fig.10 th hold time Dn to E 9 0 11 14 ns 4.5 Fig.11 th hold time Sn to LE 9 −3 11 14 ns 4.5 Fig.10 December 1990 10 Philips Semiconductors Product specification 8-input multiplexer/register with transparent latches; 3-state 74HC/HCT354 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the data enable input (E) pulse width, the data enable to output (Y, Y) propagation delays, and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the data input (Dn) to output (Y, Y) propagation delays and the output transition times (E = LOW). December 1990 11 Philips Semiconductors Product specification 8-input multiplexer/register with transparent latches; 3-state 74HC/HCT354 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the select input (Sn) to output (Y, Y) propagation delays and the output transition times (LE = LOW). (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.9 Waveforms showing the address latch enable input (LE) pulse width, the address latch enable input to output (Y, Y) propagation delays and the output transition times. December 1990 12 Philips Semiconductors Product specification 8-input multiplexer/register with transparent latches; 3-state 74HC/HCT354 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.10 Waveforms showing the set-up and hold times for the select input (Sn) to the address latch enable input (LE). (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.11 Waveforms showing the set-up and hold times for the data input (Dn) to the data enable input (E). (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.12 Waveforms showing the 3-state enable and disable times. December 1990 13 Philips Semiconductors Product specification 8-input multiplexer/register with transparent latches; 3-state 74HC/HCT354 PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 14