INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT237 3-to-8 line decoder/demultiplexer with address latches Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer with address latches 74HC/HCT237 The 74HC/HCT237 are 3-to-8 line decoder/demultiplexers with latches at the three address inputs (An). The “237” essentially combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE = LOW), the “237” acts as a 3-to-8 active LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long as LE remains HIGH. FEATURES • Combines 3-to-8 decoder with 3-bit latch • Multiple input enable for easy expansion or independent controls • Active HIGH mutually exclusive outputs • Output capability: standard • ICC category: MSI The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH. GENERAL DESCRIPTION The 74HC/HCT237 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The “237” is ideally suited for implementing non-overlapping decoders in 3-state systems and strobed (stored address) applications in bus oriented systems. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL / tPLH PARAMETER CONDITIONS HCT An to Yn 16 19 ns LE to Yn 19 21 ns E1 to Yn 14 17 ns E2 to Yn 14 17 ns 3.5 3.5 pF 60 63 pF propagation delay CI input capacitance CPD power dissipation capacitance per package CL = 15 pF; VCC = 5 V notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. December 1990 UNIT HC 2 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer with address latches 74HC/HCT237 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 2, 3 A0 to A2 data inputs 4 LE latch enable input (active LOW) 5 E1 data enable input (active LOW) 6 E2 data enable input (active HIGH) 8 GND ground (0 V) 15, 14, 13, 12, 11, 10, 9, 7 Y0 to Y7 multiplexer outputs 16 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer with address latches 74HC/HCT237 Fig.4 Functional diagram. FUNCTION TABLE INPUTS OUTPUTS LE E1 E2 A0 A1 A2 Y0 Y1 H L H X X X X H X X X X L L L X X L X X X L L L L H L L L H L L H H L L L L H L H L L H H H L L H L L L H H L L H L L H Y4 Y5 Y6 Y7 Y3 L L L L L L L L L L L L L L L L L L L H L L L L L L L L L H L L L L L L L L L H L L L L L H L L L L H L L L L H L L L L L H L L L H H L L L L L L H L H H H L L L L L L L H stable Notes 1. H = HIGH voltage level L = LOW voltage level X = don’t care December 1990 Y2 4 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer with address latches Fig.5 Logic diagram. December 1990 5 74HC/HCT237 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer with address latches 74HC/HCT237 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 min. typ. −40 to +85 max. min. max. −40 to +125 min. UNIT V WAVEFORMS CC (V) max. tPHL/ tPLH propagation delay An to Yn 52 19 15 160 32 27 200 40 34 240 48 41 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay LE to Yn 61 22 18 190 38 32 240 48 41 285 57 48 ns 2.0 4.5 6.0 Fig.7 tPHL/ tPLH propagation delay E1 to Yn 47 17 14 145 29 25 180 36 31 220 44 38 ns 2.0 4.5 6.0 Fig.7 tPHL/ tPLH propagation delay E2 to Yn 47 17 14 145 29 25 180 36 31 220 44 38 ns 2.0 4.5 6.0 Fig.6 tTHL/ tTLH output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 Fig.6 tW LE pulse width LOW 50 10 9 11 4 3 65 13 11 75 15 13 ns 2.0 4.5 6.0 Fig.8 tsu set-up time An to LE 50 10 9 6 2 2 65 13 11 75 15 13 ns 2.0 4.5 6.0 Fig.8 th hold time An to LE 30 6 5 3 1 1 40 8 7 45 9 8 ns 2.0 4.5 6.0 Fig.8 December 1990 6 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer with address latches 74HC/HCT237 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT An 1.50 E1 1.50 E2 1.50 LE 1.50 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min. typ. −40 to +85 max. min. max. −40 to +125 min. UNIT V WAVEFORMS CC (V) max. tPHL/ tPLH propagation delay An to Yn 22 38 48 57 ns 4.5 Fig.6 tPHL/ tPLH propagation delay LE to Yn 25 42 53 63 ns 4.5 Fig.7 tPHL/ tPLH propagation delay E1 to Yn 20 35 44 53 ns 4.5 Fig.7 tPHL/ tPLH propagation delay E2 to Yn 20 33 41 50 ns 4.5 Fig.6 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.6 tW LE pulse width HIGH 10 5 13 15 ns 4.5 Fig.8 tsu set-up time An to LE 10 2 13 15 ns 4.5 Fig.8 th hold time An to LE 5 0 5 5 ns 4.5 Fig.8 December 1990 7 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer with address latches 74HC/HCT237 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC . HCT: VM = 1.3 V; VI = GND to 3 V. (1) HC : VM = 50%; VI = GND to VCC . HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Fig.7 Waveforms showing the address input (An) and enable inputs (E2, LE) to output (Yn) propagation delays and the output transition times. Waveforms showing the enable input (E1) to output (Yn) propagation delays and the output transition times. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC . HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the data set-up, hold times for An input to LE input and the latch enable pulse width. December 1990 8 Philips Semiconductors Product specification 3-to-8 line decoder/demultiplexer with address latches APPLICATION INFORMATION Fig.9 6-to-64 line decoder with input address storage. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 9 74HC/HCT237