Philips Semiconductors Product specification PowerMOS transistor Logic level FET GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope suitable for surface mount applications. The device is intended for use in Switched Mode Power Supplies (SMPS), motor control, welding, DC/DC and AC/DC converters, and in automotive and general purpose switching applications. PINNING - SOT404 PIN BUK566-60A QUICK REFERENCE DATA SYMBOL PARAMETER VDS ID Ptot RDS(ON) Drain-source voltage Drain current (DC) Total power dissipation Drain-source on-state resistance VGS = 5 V PIN CONFIGURATION MAX. UNIT 60 50 150 26 V A W mΩ SYMBOL DESCRIPTION d mb 1 gate 2 drain 3 source mb drain g 2 1 3 s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS VDGR ±VGS ±VGSM ID ID IDM Ptot Tstg Tj Drain-source voltage Drain-gate voltage Gate-source voltage Non-repetitive gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage temperature Junction temperature RGS = 20 kΩ tp ≤ 50 µs Tmb = 25 ˚C Tmb = 100 ˚C Tmb = 25 ˚C Tmb = 25 ˚C - - 55 - 60 60 15 20 50 38 200 150 175 175 V V V V A A A W ˚C ˚C THERMAL RESISTANCES SYMBOL PARAMETER Rth j-mb Thermal resistance junction to mounting base Thermal resistance junction to ambient Rth j-a February 1996 CONDITIONS minimum footprint, FR4 boards (see. Fig 18). 1 MIN. TYP. MAX. UNIT - - 1.0 K/W - 50 - K/W Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level FET BUK566-60A STATIC CHARACTERISTICS Tmb = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(BR)DSS Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current Zero gate voltage drain current Gate source leakage current Drain-source on-state resistance VGS(TO) IDSS IDSS IGSS RDS(ON) MIN. TYP. MAX. UNIT VGS = 0 V; ID = 0.25 mA 60 - - V VDS = VGS; ID = 1 mA VDS = 60 V; VGS = 0 V; Tj = 25 ˚C VDS = 60 V; VGS = 0 V; Tj =125 ˚C VGS = ±15 V; VDS = 0 V VGS = 5 V; ID = 25 A 1.0 - 1.5 1 0.1 10 20 2.0 10 1.0 100 26 V µA mA nA mΩ MIN. TYP. MAX. UNIT DYNAMIC CHARACTERISTICS Tmb = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS gfs Forward transconductance VDS = 25 V; ID = 25 A 17 30 - S Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 2200 700 280 2800 1000 400 pF pF pF td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 30 V; ID = 3 A; VGS = 5 V; RGS = 50 Ω; Rgen = 50 Ω - 40 150 350 190 50 250 450 250 ns ns ns ns Ld Internal drain inductance - 2.5 - nH Ls Internal source inductance Measured from upper edge of drain tab to centre of die Measured from source lead soldering point to source bond pad - 7.5 - nH MIN. TYP. MAX. UNIT REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tmb = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS IDR - - - 50 A IDRM VSD Continuous reverse drain current Pulsed reverse drain current Diode forward voltage IF = 50 A ; VGS = 0 V - 1.1 200 2.0 A V trr Qrr Reverse recovery time Reverse recovery charge IF = 50 A; -dIF/dt = 100 A/µs; VGS = 0 V; VR = 30 V - 80 0.4 - ns µC MIN. TYP. MAX. UNIT - - 150 mJ AVALANCHE LIMITING VALUE Tmb = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS WDSS Drain-source non-repetitive unclamped inductive turn-off energy ID = 25 A ; VDD ≤ 25 V ; VGS = 5 V ; RGS = 50 Ω February 1996 2 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level FET Normalised Power Derating PD% 120 BUK566-60A 10 Zth j-mb / (K/W) BUKx56-lv 110 100 90 D= 1 80 0.5 70 0.2 0.1 0.05 60 0.1 50 0.02 40 30 0.01 tp PD D= 0 20 10 0 0 20 40 60 80 100 Tmb / C 120 140 160 1E-05 Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Tmb) 120 ID / IDmax % t T 0.001 180 tp T 1E-03 t/s 1E-01 1E+01 Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T Normalised Current Derating 150 ID / A 10 8 BUK5y6-60A 7 6 VGS / V = 100 80 100 5 4.5 60 4 40 50 3.5 20 3 2.5 0 0 20 40 60 80 100 Tmb / C 120 140 160 0 180 0 BUK556-60A ID / A 0.1 N) = 8 10 12 RDS(ON) / Ohm 3 BUK5y6-60A 3.5 4 4.5 5 6 tp = 10 us VD (O S RD 10 6 VDS / V 0.08 ID S/ 100 4 Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 10 V 1000 2 0.06 100 us 1 ms 0.04 10 ms 100 ms 0.02 DC 7 VGS / V = 10 1 0 1 10 100 0 VDS / V Fig.3. Safe operating area. Tmb = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp February 1996 20 40 60 80 ID / A 100 120 140 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VGS 3 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level FET BUK566-60A ID / A 150 VGS(TO) / V BUK5y6-60A max. 2 Tj / C = 25 150 100 typ. min. 1 50 0 0 0 2 4 6 8 10 -60 -20 20 60 Tj / C VGS / V gfs / S 140 180 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj 40 100 BUK5y6-60A SUB-THRESHOLD CONDUCTION ID / A 1E-01 35 1E-02 30 25 2% 1E-03 98 % typ 20 1E-04 15 10 1E-05 5 1E-06 0 0 20 40 60 80 100 0 0.4 0.8 1.2 VGS / V ID / A Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID); conditions: VDS = 15 V 2.0 a 1.6 2 2.4 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS Normalised RDS(ON) = f(Tj) 10000 C / pF BUK5y6-60A Ciss 1.5 1000 Coss 1.0 Crss 100 0.5 10 0 -60 -20 20 60 Tj / C 100 140 0 180 40 VDS / V Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 25 A; VGS = 5 V February 1996 20 Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 4 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level FET 10 BUK566-60A VGS / V BUK5y6-60A 120 WDSS% 110 9 VDS / V =12 8 100 48 90 7 80 6 70 5 60 4 50 40 3 30 2 20 1 10 0 0 0 20 40 QG / nC 60 20 80 Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 50 A; parameter VDS 200 IF / A 40 80 100 120 Tmb / C 140 160 180 Fig.15. Normalised avalanche energy rating. WDSS% = f(Tmb); conditions: ID = 25 A BUK5y6-60A VDD + 150 L Tj / C = 25 150 60 VDS - VGS 100 -ID/100 T.U.T. 0 50 RGS R 01 shunt 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VSDS / V 2 Fig.16. Avalanche energy test circuit. WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD ) Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj February 1996 5 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level FET BUK566-60A MECHANICAL DATA Dimensions in mm 4.5 max 1.4 max 10.3 max Net Mass: 1.4 g 11 max 15.4 2.5 0.85 max (x2) 0.5 2.54 (x2) Fig.17. SOT404 : centre pin connected to mounting base. MOUNTING INSTRUCTIONS Dimensions in mm 11.5 9.0 17.5 2.0 3.8 5.08 Fig.18. SOT404 : soldering pattern for surface mounting. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8". February 1996 6 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level FET BUK566-60A DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. February 1996 7 Rev 1.000