Philips Semiconductors Product specification PowerMOS transistor Logic level FET GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic full-pack envelope. The device is intended for use in Switched Mode Power Supplies (SMPS), motor control, welding, DC/DC and AC/DC converters, and in automotive and general purpose switching applications. PINNING - SOT186 PIN BUK542-60A/B QUICK REFERENCE DATA SYMBOL PARAMETER MAX. MAX. UNIT VDS ID Ptot RDS(ON) BUK542 Drain-source voltage Drain current (DC) Total power dissipation Drain-source on-state resistance; VGS = 5 V -60A 60 9.2 22 0.15 -60B 60 8.4 22 0.18 V A W Ω PIN CONFIGURATION SYMBOL DESCRIPTION d case 1 gate 2 drain 3 source g case isolated s 1 2 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDS VDGR ±VGS ±VGSM Drain-source voltage Drain-gate voltage Gate-source voltage Non-repetitive gate-source voltage RGS = 20 kΩ tp ≤ 50 µs - 60 60 15 20 V V V V ID ID IDM Drain current (DC) Drain current (DC) Drain current (pulse peak value) Ths = 25 ˚C Ths = 100 ˚C Ths = 25 ˚C - Ptot Tstg Tj Total power dissipation Storage temperature Junction Temperature Ths = 25 ˚C - - 55 - -60A 9.2 5.8 37 -60B 8.4 5.3 33 A A A 22 150 150 W ˚C ˚C THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS Rth j-hs Thermal resistance junction to heatsink Thermal resistance junction to ambient with heatsink compound Rth j-a August 1994 1 MIN. TYP. MAX. UNIT - - 5.68 K/W - 55 - K/W Rev 1.100 Philips Semiconductors Product specification PowerMOS transistor Logic level FET BUK542-60A/B STATIC CHARACTERISTICS Ths = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS V(BR)DSS Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current Zero gate voltage drain current Gate source leakage current Drain-source on-state resistance VGS(TO) IDSS IDSS IGSS RDS(ON) MIN. TYP. MAX. UNIT VGS = 0 V; ID = 0.25 mA 60 - - V VDS = VGS; ID = 1 mA VDS = 60 V; VGS = 0 V; Tj = 25 ˚C VDS = 60 V; VGS = 0 V; Tj =125 ˚C VGS = ±15 V; VDS = 0 V VGS = 5 V; BUK542-60A BUK542-60B ID = 8.5 A 1.0 - 1.5 1 0.1 10 0.12 0.15 2.0 10 1.0 100 0.15 0.18 V µA mA nA Ω Ω MIN. TYP. MAX. UNIT DYNAMIC CHARACTERISTICS Ths = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS gfs Forward transconductance VDS = 25 V; ID = 8.5 A 5 6.7 - S Ciss Coss Crss Input capacitance Output capacitance Feedback capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 400 150 65 600 200 100 pF pF pF td on tr td off tf Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time VDD = 30 V; ID = 3 A; VGS = 5 V; RGS = 50 Ω; Rgen = 50 Ω - 12 60 50 45 18 80 70 70 ns ns ns ns Ld Internal drain inductance - 4.5 - nH Ls Internal source inductance Measured from drain lead 6 mm from package to centre of die Measured from source lead 6 mm from package to source bond pad - 7.5 - nH MIN. TYP. MAX. UNIT 1500 V ISOLATION LIMITING VALUE & CHARACTERISTIC Ths = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS Visol Repetitive peak voltage from all three terminals to external heatsink R.H. ≤ 65% ; clean and dustfree Cisol Capacitance from T2 to external f = 1 MHz heatsink - - 12 - pF MIN. TYP. MAX. UNIT REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Ths = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS IDR - - - 9.2 A IDRM VSD Continuous reverse drain current Pulsed reverse drain current Diode forward voltage IF = 9.2 A ; VGS = 0 V - 1.3 37 1.7 A V trr Qrr Reverse recovery time Reverse recovery charge IF = 9.2 A; -dIF/dt = 100 A/µs; VGS = 0 V; VR = 30 V - 60 0.15 - ns µC August 1994 2 Rev 1.100 Philips Semiconductors Product specification PowerMOS transistor Logic level FET BUK542-60A/B AVALANCHE LIMITING VALUE Ths = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS WDSS Drain-source non-repetitive unclamped inductive turn-off energy ID = 14 A ; VDD ≤ 25 V ; VGS = 5 V ; RGS = 50 Ω Normalised Power Derating PD% 120 100 with heatsink compound 110 MIN. TYP. MAX. UNIT - - 30 mJ ID / A BUK542-60 ID S/ 100 90 N) = VD A B tp = 10 us (O 80 70 S RD 10 100 us 60 1 ms 50 40 10 ms DC 1 100 ms 30 20 10 0 0 20 40 60 80 Ths / C 100 120 0.1 140 Fig.3. Safe operating area. Ths = 25 ˚C ID & IDM = f(VDS); IDM single pulse; parameter tp Normalised Current Derating ID% 1E+01 with heatsink compound 110 100 VDS / V Fig.1. Normalised power dissipation. PD% = 100⋅PD/PD 25 ˚C = f(Ths) 120 10 1 100 90 Zth j-hs / (K/W) ZTHX42 0.5 80 70 1E+00 60 50 1E-01 40 0.2 0.1 0.05 0.02 PD 30 tp D= tp T 0 20 10 1E-02 1E-07 0 0 20 40 60 80 Ths / C 100 120 140 Fig.2. Normalised continuous drain current. ID% = 100⋅ID/ID 25 ˚C = f(Ths); conditions: VGS ≥ 5 V August 1994 T 1E-05 1E-03 t/s 1E-01 t 1E+01 Fig.4. Transient thermal impedance. Zth j-hs = f(t); parameter D = tp/T 3 Rev 1.100 Philips Semiconductors Product specification PowerMOS transistor Logic level FET 28 BUK542-60A/B ID / A BUK552-60A 6 7 10 24 BUK 552-60A gfs / S 7 6 5 20 5 4 16 VGS / V = 12 4 3 8 2 3 4 1 0 0 0 2 4 6 8 0 10 4 8 12 16 ID / A VDS / V Fig.5. Typical output characteristics, Tj = 25 ˚C. ID = f(VDS); parameter VGS 0.5 RDS(ON) / Ohm 3 3.5 4.5 5 0.4 24 28 Fig.8. Typical transconductance, Tj = 25 ˚C. gfs = f(ID); conditions: VDS = 25 V a BUK552-60A 4 20 VGS / V = 5.5 Normalised RDS(ON) = f(Tj) 1.5 6 7 0.3 1.0 0.2 10 0.5 0.1 0 0 10 20 ID / A 30 0 40 Fig.6. Typical on-state resistance, Tj = 25 ˚C. RDS(ON) = f(ID); parameter VGS 28 ID / A -60 -40 -20 0 20 40 60 Tj / C 80 100 120 140 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 8.5 A; VGS = 5 V VGS(TO) / V BUK552-60A max. 24 Tj / C = 2 25 20 typ. 150 16 min. 12 1 8 4 0 0 0 2 4 VGS / V 6 -60 8 -20 0 20 40 60 Tj / C 80 100 120 140 Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj August 1994 -40 4 Rev 1.100 Philips Semiconductors Product specification PowerMOS transistor Logic level FET SUB-THRESHOLD CONDUCTION ID / A 1E-01 BUK542-60A/B IF / A 30 BUK552-60A 1E-02 2% 1E-03 20 98 % typ 1E-04 10 Tj / C = 150 1E-05 1E-06 0 0 0.4 0.8 1.2 VGS / V 1.6 2 0 2.4 Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS 10000 25 C / pF 1 VSDS / V 2 Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj BUK5y2-50 120 110 WDSS% 100 90 80 1000 70 Ciss 60 50 100 Coss 40 Crss 30 20 10 0 10 0 20 20 40 40 VDS / V Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz 12 60 80 100 Ths / C 120 140 Fig.15. Normalised avalanche energy rating. WDSS% = f(Ths); conditions: ID = 14 A BUK552-60 VGS / V VDD + VDS / V = 12 10 L 8 VDS 48 - VGS 6 -ID/100 T.U.T. 0 4 2 RGS R 01 shunt 0 0 2 4 6 8 10 QG / nC 12 14 16 Fig.16. Avalanche energy test circuit. WDSS = 0.5 ⋅ LID2 ⋅ BVDSS /(BVDSS − VDD ) Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 14 A; parameter VDS August 1994 5 Rev 1.100 Philips Semiconductors Product specification PowerMOS transistor Logic level FET BUK542-60A/B MECHANICAL DATA Dimensions in mm 10.2 max 5.7 max 3.2 3.0 Net Mass: 2 g 4.4 max 0.9 0.5 2.9 max 4.4 4.0 7.9 7.5 17 max seating plane 3.5 max not tinned 4.4 13.5 min 1 0.4 2 3 0.9 0.7 M 0.55 max 2.54 1.3 5.08 top view Fig.17. SOT186; The seating plane is electrically isolated from all terminals. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Refer to mounting instructions for F-pack envelopes. 3. Epoxy meets UL94 V0 at 1/8". August 1994 6 Rev 1.100 Philips Semiconductors Product specification PowerMOS transistor Logic level FET BUK542-60A/B DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. August 1994 7 Rev 1.100 Error Log 542-60.A&B 1) Level: Format Error Message: Page break required with Keep enabled Location: Document Body Page E1 96-11-11 04:05 pm