74HC73 Dual JK flip-flop with reset; negative-edge trigger Rev. 04 — 19 March 2008 Product data sheet 1. General description The 74HC73 is a high-speed Si-gate CMOS device that complies with JEDEC standard no. 7A. It is pin compatible with Low-power Schottky TTL (LSTTL). The 74HC73 is a dual negative-edge triggered JK flip-flop featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. The reset (nR) is an asynchronous active LOW input. When LOW, it overrides the clock and data inputs, forcing the nQ output LOW and the nQ output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. 2. Features n Low-power dissipation n Complies with JEDEC standard no. 7A n ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V n Multiple package options n Specified from −40 °C to +80 °C and from −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC73N −40 °C to +125 °C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 74HC73D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74HC73DB −40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 74HC73PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74HC73 NXP Semiconductors Dual JK flip-flop with reset; negative-edge trigger 4. Functional diagram 14 1J 1 1CP 3 1K J Q 1Q 12 FF1 CP Q K 1Q 13 R 2 1R 7 2J 5 2CP 10 2K J Q 2Q 9 FF2 CP Q K 2Q 8 R 6 2R 001aab981 Fig 1. Functional diagram 14 1 14 7 1J 2J 1 1CP 5 2CP J Q 3 1Q 12 2Q 9 2 FF 1K 2K Q K 1Q 13 2Q 8 5 10 R 1R 2R 2 6 Fig 2. Logic symbol 6 1K 13 R 1J 9 C1 1K 8 R 001aab980 001aab979 Fig 3. IEC logic symbol 74HC73_4 Product data sheet 12 C1 CP 7 3 10 1J © NXP B.V. 2008. All rights reserved. Rev. 04 — 19 March 2008 2 of 16 74HC73 NXP Semiconductors Dual JK flip-flop with reset; negative-edge trigger C C C C K Q J C C C C R Q C CP 001aab982 C Fig 4. Logic diagram (one flip-flop) 5. Pinning information 5.1 Pinning 74HC73 1CP 1 14 1J 1R 2 13 1Q 1K 3 12 1Q VCC 4 11 GND 2CP 5 10 2K 2R 6 9 2Q 2J 7 8 2Q 001aab978 Fig 5. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Pin Description 1CP, 2CP 1, 5 clock input (HIGH-to-LOW edge-triggered); also referred to as nCP 1R, 2R 2, 6 asynchronous reset input (active LOW); also referred to as nR 1K, 2K 3, 10 synchronous K input; also referred to as nK VCC 4 positive supply voltage GND 11 ground (0 V) 1Q, 2Q 12, 9 true output; also referred to as nQ 1Q, 2Q 13, 8 complement output; also referred to as nQ 1J, 2J 14, 7 synchronous J input; also referred to as nJ 74HC73_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 19 March 2008 3 of 16 74HC73 NXP Semiconductors Dual JK flip-flop with reset; negative-edge trigger 6. Functional description Table 3. Function table[1] Input Output Operating mode nR nCP nJ nK nQ nQ L X X X L H asynchronous reset H ↓ h h q q toggle H ↓ l h L H load 0 (reset) H ↓ h l H L load 1 (set) H ↓ l l q q hold (no change) [1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition; q = state of referenced output one set-up time prior to the HIGH-to-LOW clock transition; X = don’t care; ↓ = HIGH-to-LOW clock transition. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions IIK input clamping current VI < −0.5 V or VI > VCC + 0.5 V IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V VO = −0.5 V to VCC + 0.5 V Min Max Unit −0.5 +7.0 V [1] - ±20 mA [1] - ±20 mA IO output current - ±25 mA ICC supply current - 50 mA IGND ground current −50 - mA Tstg storage temperature −65 +150 °C Ptot total power dissipation Tamb = −40 °C to +125 °C DIP14 package [2] - 750 mW SO14 package [3] - 500 mW (T)SSOP14 package [4] - 500 mW [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Ptot derates linearly with 12 mW/K above 70 °C. [3] Ptot derates linearly with 8 mW/K above 70 °C. [4] Ptot derates linearly with 5.5 mW/K above 60 °C. 74HC73_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 19 March 2008 4 of 16 74HC73 NXP Semiconductors Dual JK flip-flop with reset; negative-edge trigger 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC Conditions Min Typ Max Unit supply voltage 2.0 5.0 6.0 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature −40 - +125 °C ∆t/∆V input transition rise and fall rate VCC = 2.0 V - - 625 ns VCC = 4.5 V - 1.67 139 ns VCC = 6.0 V - - 83 ns 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH VOL 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V LOW-level input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V HIGH-level output voltage VI = VIH or VIL IO = −20 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = −20 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = −20 µA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = −4 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = −5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V HIGH-level input voltage LOW-level output voltage VI = VIH or VIL IO = 20 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 µA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V - - ±0.1 - ±1.0 - ±1.0 µA supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 4.0 - 40.0 - 80.0 µA input capacitance - 3.5 - - - - - pF II input leakage current ICC CI VI = VCC or GND; VCC = 6.0 V 74HC73_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 19 March 2008 5 of 16 74HC73 NXP Semiconductors Dual JK flip-flop with reset; negative-edge trigger 10. Dynamic characteristics Table 7. Dynamic characteristics GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 8 Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max tpd propagation delay nCP to nQ; see Figure 6 Min Max Min Max [1] VCC = 2.0 V - 52 160 - 200 - 240 ns VCC = 4.5 V - 19 32 - 40 - 48 ns VCC = 6.0 V - 15 27 - 34 - 41 ns VCC = 5.0 V; CL = 15 pF - 16 - - - - - ns VCC = 2.0 V - 52 160 - 200 - 240 ns VCC = 4.5 V - 19 32 - 40 - 48 ns 34 - 41 nCP to nQ; see Figure 6 VCC = 6.0 V - 15 27 VCC = 5.0 V; CL = 15 pF - 16 - - VCC = 2.0 V - 50 145 - VCC = 4.5 V - 18 29 - VCC = 6.0 V - 14 25 - 15 - VCC = 2.0 V - 19 VCC = 4.5 V - 7 VCC = 6.0 V - 6 13 VCC = 2.0 V 80 22 - 100 VCC = 4.5 V 16 8 - 20 VCC = 6.0 V 14 6 - 17 VCC = 2.0 V 80 22 - 100 VCC = 4.5 V 16 8 - 20 VCC = 6.0 V 14 6 - 17 VCC = 2.0 V 80 22 - 100 VCC = 4.5 V 16 8 - 20 VCC = 6.0 V 14 6 - 17 VCC = 2.0 V 80 22 - 100 VCC = 4.5 V 16 8 - 20 VCC = 6.0 V 14 6 - 17 ns ns nR to nQ, nQ; see Figure 7 VCC = 5.0 V; CL = 15 pF tt tW - 220 ns 36 - 44 ns 31 - 38 ns - - - - ns 75 - 95 - 110 ns 15 - 19 - 22 ns 16 - 19 ns 120 - ns - 24 - ns - 20 [2] transition time nQ, nQ; see Figure 6 pulse width 180 nCP input, HIGH or LOW; see Figure 6 ns nR input, HIGH or LOW; see Figure 7 trec tsu recovery time set-up time - ns - 24 - ns - 20 ns nR to nCP; see Figure 7 120 - ns - 24 - ns - 20 ns nJ, nK to nCP; see Figure 6 74HC73_4 Product data sheet 120 120 - ns - 24 - ns - 20 ns © NXP B.V. 2008. All rights reserved. Rev. 04 — 19 March 2008 6 of 16 74HC73 NXP Semiconductors Dual JK flip-flop with reset; negative-edge trigger Table 7. Dynamic characteristics …continued GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 8 Symbol Parameter th hold time maximum frequency fmax 25 °C Conditions power dissipation capacitance [1] Min Typ Max Min Max Min Max nJ, nK to nCP; see Figure 6 VCC = 2.0 V 3 −8 - 3 3 - ns VCC = 4.5 V 3 −3 - 3 - 3 - ns VCC = 6.0 V 3 −2 - 3 - 3 VCC = 2.0 V 6.0 23 - 4.8 4.0 - MHz VCC = 4.5 V 30 70 - 24 - 20 - MHz VCC = 6.0 V 35 83 - 28 - 24 - MHz - 77 - - MHz - 30 - - pF ns nCP input; see Figure 6 VCC = 5.0 V; CL = 15 pF CPD −40 °C to +85 °C −40 °C to +125 °C Unit per flip-flop; VI = GND to VCC [3] - - - tpd is the same as tPHL, tPLH. [2] tt is the same as tTHL, tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 74HC73_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 19 March 2008 7 of 16 74HC73 NXP Semiconductors Dual JK flip-flop with reset; negative-edge trigger 11. Waveforms VI nJ, nK input GND VM th tsu th tsu 1/f max VI VM nCP input GND tW tPLH tPHL VOH 90 % nQ output 90 % VM 10 % VOL 10 % tTHL VOH tTLH 90 % 90 % nQ output VM 10 % VOL 10 % tTLH tTHL tPLH tPHL 001aab983 The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the J and K to nCP set-up and hold times, the output transition times and the maximum clock frequency VI VM nCP input GND trec tW VI VM nR input GND tPHL VOH nQ output VOL tPLH VOH nQ output 001aab984 VOL Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Waveforms showing the reset (nR) input to output (nQ, nQ) propagation delays and the reset pulse width and the nR to nCP removal time 74HC73_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 19 March 2008 8 of 16 74HC73 NXP Semiconductors Dual JK flip-flop with reset; negative-edge trigger Table 8. Measurement points Type Input 74HC73 Output VI VM VM VCC 0.5VCC 0.5VCC VI negative pulse tW 90 % VM VM 10 % GND tr tf tr tf VI 90 % positive pulse GND VM VM 10 % tW VCC G VI VO DUT RT CL 001aah768 Test data is given in Table 9. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. Fig 8. Table 9. Test circuit for measuring switching times Test data Type 74HC73 Input Load VI tr, tf CL VCC 6 ns 15 pF, 50 pF 74HC73_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 19 March 2008 9 of 16 74HC73 NXP Semiconductors Dual JK flip-flop with reset; negative-edge trigger 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.2 inches 0.17 0.02 0.13 0.068 0.044 0.021 0.015 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. Fig 9. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT27-1 050G04 MO-001 SC-501-14 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Package outline SOT27-1 (DIP14) 74HC73_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 19 March 2008 10 of 16 74HC73 NXP Semiconductors Dual JK flip-flop with reset; negative-edge trigger SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT108-1 (SO14) 74HC73_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 19 March 2008 11 of 16 74HC73 NXP Semiconductors Dual JK flip-flop with reset; negative-edge trigger SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.4 0.9 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 11. Package outline SOT337-1 (SSOP14) 74HC73_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 19 March 2008 12 of 16 74HC73 NXP Semiconductors Dual JK flip-flop with reset; negative-edge trigger TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 12. Package outline SOT402-1 (TSSOP14) 74HC73_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 19 March 2008 13 of 16 74HC73 NXP Semiconductors Dual JK flip-flop with reset; negative-edge trigger 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC73_4 20080319 Product data sheet - 74HC73_3 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • Legal texts have been adapted to the new company name where appropriate. Quick reference data incorporated into Section 9 and 10. Section 8 “Recommended operating conditions” tr, tf converted to ∆t/∆V. 74HC73_3 20041112 Product data sheet - 74HC_HCT73_CNV_2 74HC_HCT73_CNV_2 December 1990 Product specification - - 74HC73_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 19 March 2008 14 of 16 74HC73 NXP Semiconductors Dual JK flip-flop with reset; negative-edge trigger 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74HC73_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 19 March 2008 15 of 16 74HC73 NXP Semiconductors Dual JK flip-flop with reset; negative-edge trigger 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 19 March 2008 Document identifier: 74HC73_4