74AHC74; 74AHCT74 Dual D-type flip-flop with set and reset; positive-edge trigger Rev. 05 — 9 June 2008 Product data sheet 1. General description The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has complementary outputs (Q and Q). The set and reset are asynchronous active LOW inputs that operate independent of the clock input. Information on the data input is transferred to the Q output on the LOW to HIGH transition of the clock pulse. The data inputs must be stable one set-up time prior to the LOW to HIGH clock transition for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. 2. Features n n n n Balanced propagation delays All inputs have Schmitt-trigger actions Inputs accept voltages higher than VCC Input levels: u For 74AHC74: CMOS level u For 74AHCT74: TTL level n ESD protection: u HBM EIA/JESD22-A114E exceeds 2000 V u MM EIA/JESD22-A115-A exceeds 200 V u CDM EIA/JESD22-C101C exceeds 1000 V n Multiple package options n Specified from −40 °C to +85 °C and from −40 °C to +125 °C 74AHC74; 74AHCT74 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC74D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74AHC74PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74AHC74BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm SOT762-1 74AHCT74D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74AHCT74PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74AHCT74BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm 74AHC74 74AHCT74 SOT762-1 4. Functional diagram 4 10 1SD 2SD 2 12 3 11 SD 1Q 1D Q D 2D 2Q 1CP CP 2CP FF 1Q Q 2Q RD 5 9 6 8 1RD 2RD 1 13 Fig 1. mna418 Functional diagram 74AHC_AHCT74_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 9 June 2008 2 of 18 74AHC74; 74AHCT74 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 4 2 3 1SD 1D 1CP SD Q D 1Q 5 CP FF Q 1Q 6 RD 1 10 12 11 4 1RD 3 2SD 2 1 2D 2CP SD Q D 2Q 9 10 CP 11 FF Q 2Q 12 8 13 RD 13 Fig 2. 2RD S 5 C1 1D 6 R S 9 C1 1D 8 R mna420 mna419 Logic symbol Fig 3. IEC logic symbol Q C C C C C C D Q C C RD SD CP mna421 C C Fig 4. Logic diagram (one flip-flop) 74AHC_AHCT74_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 9 June 2008 3 of 18 74AHC74; 74AHCT74 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 5. Pinning information 1 terminal 1 index area 1CP 3 12 2D 1SD 4 74 2 13 2RD 3 12 2D 1SD 4 74 11 2CP 1Q 5 GND(1) 10 2SD 1Q 6 11 2CP 1Q 5 10 2SD 1Q 6 9 2Q GND 7 8 2Q 9 8 2 1D 1CP 2Q 1D 14 VCC 13 2RD 7 1 GND 1RD 14 VDD 1RD 5.1 Pinning 2Q 001aac450 Transparent top view 001aac449 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as supply pin or input. Fig 5. Pin configuration SO14 and TSSOP14 Fig 6. Pin configuration DHVQFN14 5.2 Pin description Table 2. Pin description Symbol Pin Description 1RD 1 asynchronous reset direct input (active LOW) 1D 2 data input 1CP 3 clock input (LOW to HIGH, edge-triggered) 1SD 4 asynchronous set direct input (active LOW) 1Q 5 true flip-flop output 1Q 6 complement flip-flop output GND 7 ground (0 V) 2Q 8 complement flip-flop output 2Q 9 true flip-flop output 2SD 10 asynchronous set direct input (active LOW) 2CP 11 clock input (LOW to HIGH, edge-triggered) 2D 12 data input 2RD 13 asynchronous reset direct input (active LOW) VCC 14 supply voltage 74AHC_AHCT74_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 9 June 2008 4 of 18 74AHC74; 74AHCT74 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 6. Functional description Table 3. Function table[1] Control Input Output nSD nRD nCP nD nQ nQ nQn+1 nQn+1 L H X X H L L H H L X X L H H L L L X X H H - - H H ↑ L - - L H H H ↑ H - - H L [1] H = HIGH voltage level; L = LOW voltage level; ↑ = LOW to HIGH transition; Qn+1 = state after the next LOW to HIGH CP transition; X = don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI input voltage Conditions input clamping current VI < −0.5 V [1] IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V [1] IO output current VO = −0.5V to (VCC + 0.5 V) ICC IIK Min Max Unit −0.5 +7.0 V −0.5 +7.0 V −20 - mA −20 +20 mA −25 +25 mA supply current - +75 mA IGND ground current −75 - mA Tstg storage temperature −65 +150 °C Ptot total power dissipation - 500 mW Tamb = −40 °C to +125 °C [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO14 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K. For TSSOP14 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K. For DHVQFN14 packages: above 60 °C the value of Ptot derates linearly at 4.5 mW/K. 74AHC_AHCT74_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 9 June 2008 5 of 18 74AHC74; 74AHCT74 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 8. Recommended operating conditions Table 5. Operating conditions Symbol Parameter Conditions Min Typ Max Unit 2.0 5.0 5.5 V 74AHC74 VCC supply voltage VI input voltage 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature −40 +25 +125 °C ∆t/∆V input transition rise and fall rate VCC = 3.0 V to 3.6 V - - 100 ns/V VCC = 4.5 V to 5.5 V - - 20 ns/V 74AHCT74 VCC supply voltage 4.5 5.0 5.5 V VI input voltage 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature −40 +25 +125 °C ∆t/∆V input transition rise and fall rate - - 20 ns/V VCC = 4.5 V to 5.5 V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max 74AHC74 VIH VIL VOH VOL HIGH-level input voltage VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V LOW-level input voltage VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V HIGH-level VI = VIH or VIL output voltage IO = −50 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = −50 µA; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V IO = −50 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = −4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V IO = −8.0 mA; VCC = 4.5 V 3.94 - - 3.80 - 3.70 - V LOW-level VI = VIH or VIL output voltage IO = 50 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 µA; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V IO = 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V 74AHC_AHCT74_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 9 June 2008 6 of 18 74AHC74; 74AHCT74 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions VI = 5.5 V or GND; VCC = 0 V to 5.5 V −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max - - 0.1 - 1.0 - 2.0 µA II input leakage current ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 2.0 - 20 - 40 µA CI input capacitance - 3 10 - 10 - 10 pF VI = VCC or GND 74AHCT74 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V VOH HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = −50 µA 4.4 4.5 - 4.4 - 4.4 - V 3.94 - - 3.80 - 3.70 - V - 0 0.1 - 0.1 - 0.1 V - - 0.36 - 0.44 - 0.55 V - - 0.1 - 1.0 - 2.0 µA IO = −8.0 mA VOL LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 µA IO = 8.0 mA II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 2.0 - 20 - 40 µA ∆ICC additional per input pin; supply current VI = VCC − 2.1 V; other pins at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V - - 1.35 - 1.5 - 1.5 mA CI input capacitance - 3 10 - 10 - 10 pF VI = VCC or GND 74AHC_AHCT74_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 9 June 2008 7 of 18 74AHC74; 74AHCT74 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9. Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max Min Max CL = 15 pF - 5.2 11.9 1.0 14.0 1.0 15.0 ns CL = 50 pF - 7.4 15.4 1.0 17.5 1.0 19.5 ns CL = 15 pF - 3.7 7.3 1.0 8.5 1.0 9.5 ns CL = 50 pF - 5.2 9.3 1.0 10.5 1.0 12.0 ns CL = 15 pF - 5.4 12.3 1.0 14.5 1.0 15.5 ns CL = 50 pF - 7.7 15.8 1.0 18.0 1.0 20.0 ns CL = 15 pF - 3.7 7.7 1.0 9.0 1.0 10.0 ns CL = 50 pF - 5.3 9.7 1.0 11.0 1.0 12.5 ns CL = 15 pF 80 125 - 45 - 45 - MHz CL = 50 pF 50 75 - 70 - 70 - MHz CL = 15 pF 130 170 - 110 - 110 - MHz CL = 50 pF 90 115 - 75 - 75 - MHz VCC = 3.0 V to 3.6 V 6.0 - - 7.0 - 7.0 - ns VCC = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns VCC = 3.0 V to 3.6 V 6.0 - - 7.0 - 7.0 - ns VCC = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns VCC = 3.0 V to 3.6 V 0.5 - - 0.5 - 0.5 - ns VCC = 4.5 V to 5.5 V 0.5 - - 0.5 - 0.5 - ns VCC = 3.0 V to 3.6 V 5.0 - - 5.0 - 5.0 - ns VCC = 4.5 V to 5.5 V 3.0 - - 3.0 - 3.0 - ns 74AHC74 tpd propagation nCP to nQ, nQ; see Figure 7 delay VCC = 3.0 V to 3.6 V [2] VCC = 4.5 V to 5.5 V nSD, nRD to nQ, nQ; see Figure 8 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V fmax maximum frequency see Figure 7 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tW tsu th trec pulse width set-up time hold time recovery time CP HIGH or LOW; nSD, nRD LOW; see Figure 7 and 8 nD to nCP; see Figure 7 nD to nCP; see Figure 7 nRD to nCP; see Figure 8 74AHC_AHCT74_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 9 June 2008 8 of 18 74AHC74; 74AHCT74 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9. Symbol Parameter CPD 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max Min Max - 12 - - - - - - 3.3 7.8 1.0 9.0 1.0 10.0 ns - 4.8 8.8 1.0 10.0 1.0 11.0 ns CL = 15 pF - 3.7 10.4 1.0 12.0 1.0 13.0 ns CL = 50 pF - 5.3 11.4 1.0 13.0 1.0 14.5 ns 100 160 - 80 - 80 - fi = 1 MHz; VI = GND to VCC power dissipation capacitance [3] pF 74AHCT74; VCC = 4.5 V to 5.5 V tpd propagation nCP to nQ, nQ; see Figure 7 delay CL = 15 pF [2] CL = 50 pF nSD, nRD to nQ, nQ; see Figure 7 maximum frequency see Figure 7 80 140 - 65 - 65 - MHz tW pulse width CP HIGH or LOW; nSD, nRD LOW; see Figure 7 and 8 5.0 - - 5.0 - 5.0 - ns fmax CL = 15 pF CL = 50 pF MHz tsu set-up time nD to nCP; see Figure 7 5.0 - - 5.0 - 5.0 - ns th hold time nD to nCP; see Figure 7 0 - - 0 - 0 - ns trec recovery time nRD to nCP; see Figure 8 3.5 - - 3.5 - 3.5 - ns CPD power fi = 1 MHz; VI = GND to VCC dissipation capacitance - 16 - - - - - pF [3] [1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. 74AHC_AHCT74_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 9 June 2008 9 of 18 74AHC74; 74AHCT74 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 11. Waveforms VI VM nD input GND th th t su t su 1/fmax VI VM nCP input GND tW t PHL t PLH VOH VM nQ output VOL VOH nQ output VM VOL t PLH t PHL mna422 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical voltage output drop that occur with the output load. Fig 7. Clock pulse width, maximum frequency, set-up times, hold times and input to output propagation delays 74AHC_AHCT74_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 9 June 2008 10 of 18 74AHC74; 74AHCT74 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger VI VM nCP input GND t rec VI VM nSD input GND tW tW VI VM nRD input GND t PLH t PHL VOH nQ output VM VOL VOH VM nQ output VOL t PHL t PLH mna423 Measurement points are given in Table 8. VOL and VOH are typical voltage output drop that occur with the output load. Fig 8. Set and reset pulse widths, recovery time and input to output propagation delays Table 8. Measurement points Type Input Output VM VM 74AHC74 0.5 × VCC 0.5 × VCC 74AHCT74 1.5 V 0.5 × VCC 74AHC_AHCT74_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 9 June 2008 11 of 18 74AHC74; 74AHCT74 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger VI negative pulse tW 90 % VM VM 10 % GND tr tf tr VI positive pulse GND tf 90 % VM VM 10 % tW VCC G VI VO DUT RT CL 001aah768 For test data see Table 9. Definitions for test circuit: CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 9. Load circuitry for switching times Table 9. Test data Type Input Load Test VI tr, tf CL 74AHC74 VCC ≤ 3.0 ns 50 pF, 15 pF tPLH, tPHL 74AHCT74 3.0 V ≤ 3.0 ns 50 pF, 15 pF tPLH, tPHL 74AHC_AHCT74_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 9 June 2008 12 of 18 74AHC74; 74AHCT74 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT108-1 (SO14) 74AHC_AHCT74_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 9 June 2008 13 of 18 74AHC74; 74AHCT74 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 11. Package outline SOT402-1 (TSSOP14) 74AHC_AHCT74_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 9 June 2008 14 of 18 74AHC74; 74AHCT74 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.1 2.9 1.65 1.35 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT762-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 12. Package outline SOT762-1 (DHVQFN14) 74AHC_AHCT74_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 9 June 2008 15 of 18 74AHC74; 74AHCT74 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AHC_AHCT74_5 20080609 Product data sheet - 74AHC_AHCT74_4 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Table 6: the conditions for input leakage current have been changed. 74AHC_AHCT74_4 20050207 Product data sheet - 74AHC_AHCT74_3 74AHC_AHCT74_3 20040429 Product specification - 74AHC_AHCT74_2 74AHC_AHCT74_2 19990923 Product specification - 74AHC_AHCT74_1 74AHC_AHCT74_1 19990805 Product specification - - 74AHC_AHCT74_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 9 June 2008 16 of 18 74AHC74; 74AHCT74 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74AHC_AHCT74_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 9 June 2008 17 of 18 74AHC74; 74AHCT74 NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 9 June 2008 Document identifier: 74AHC_AHCT74_5