74AHC273; 74AHCT273 Octal D-type flip-flop with reset; positive-edge trigger Rev. 03 — 13 May 2008 Product data sheet 1. General description The 74AHC273; 74AHCT273 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC273; 74AHCT273 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs, load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. All outputs will be forced LOW, independent of clock or data inputs, by a LOW on the MR input. The device is useful for applications where only the true output is required and the clock and master reset are common to all storage elements. 2. Features n n n n n n n n n n Balanced propagation delays All inputs have Schmitt-trigger actions Inputs accept voltages higher than VCC Ideal buffer for MOS microcontroller or memory Common clock and master reset Related product versions: u 74AHC377; 74AHCT377 for clock enable version u 74AHC373; 74AHCT373 for transparent latch version u 74AHC374; 74AHCT374 for 3-state version Input levels: u For 74AHC273: CMOS level u For 74AHCT273: TTL level ESD protection: u HBM EIA/JESD22-A114E exceeds 2000 V u MM EIA/JESD22-A115-A exceeds 200 V u CDM EIA/JESD22-C101C exceeds 1000 V Multiple package options Specified from −40 °C to +85 °C and from −40 °C to +125 °C 74AHC273; 74AHCT273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC273D −40 °C to +125 °C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 74AHC273PW −40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 74AHC273BQ −40 °C to +125 °C DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1 thin quad flat package; no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm 74AHCT273D −40 °C to +125 °C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 74AHCT273PW −40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 74AHCT273BQ −40 °C to +125 °C DHVQFN20 plastic dual in-line compatible thermal enhanced very SOT764-1 thin quad flat package; no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm 74AHC273 74AHCT273 4. Functional diagram CP MR 11 1 C1 R 11 3 4 7 8 13 14 17 18 D0 CP D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 2 D1 5 6 D2 9 D3 12 D4 15 D5 16 D6 19 MR 1 Fig 1. Logic symbol D7 2 1D 4 5 7 6 8 9 13 12 14 15 17 16 18 19 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 mna764 mna763 Fig 2. IEC logic symbol 74AHC_AHCT273_3 Product data sheet 3 © NXP B.V. 2008. All rights reserved. Rev. 03 — 13 May 2008 2 of 18 74AHC273; 74AHCT273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger D0 D1 D Q D2 D Q D3 D Q D Q CP FF1 CP FF2 CP FF3 CP FF4 RD RD RD RD CP MR Q0 D4 Q1 D5 D Q Q2 D6 D Q Q3 D7 D Q D Q CP FF5 CP FF6 CP FF7 CP FF8 RD RD RD RD Q4 Q5 Q6 Q7 001aae056 Fig 3. Logic diagram 3 4 7 8 13 14 17 18 1 11 D0 D1 D2 D3 D4 D5 D6 D7 FF1 TO FF8 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19 MR CP 001aae055 Fig 4. Functional diagram 74AHC_AHCT273_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 13 May 2008 3 of 18 74AHC273; 74AHCT273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger 5. Pinning information 5.1 Pinning terminal 1 index area MR 1 1 74AHC273 74AHCT273 20 VCC 20 VCC MR 74AHC273 74AHCT273 Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q0 2 19 Q7 D0 3 18 D7 Q1 5 16 Q6 15 Q5 4 17 D6 Q2 6 5 16 Q6 D2 7 Q2 6 15 Q5 D2 7 14 D5 8 13 D4 Q3 9 12 Q4 GND 10 11 CP 8 Q3 9 13 D4 12 Q4 GND 10 D3 D3 14 D5 GND(1) CP 11 D1 Q1 001aai067 Transparent top view 001aai066 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 5. Pin configuration SO20 and TSSOP20 Fig 6. Pin configuration DHVQFN20 5.2 Pin description Table 2. Pin description Symbol Pin Description MR 1 master reset input (active LOW) Q0 2 flip-flop output D0 3 data input D1 4 data input Q1 5 flip-flop output Q2 6 flip-flop output D2 7 data input D3 8 data input Q3 9 flip-flop output GND 10 ground (0 V) CP 11 clock input (LOW-to-HIGH edge-triggered) Q4 12 flip-flop output D4 13 data input D5 14 data input Q5 15 flip-flop output Q6 16 flip-flop output 74AHC_AHCT273_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 13 May 2008 4 of 18 74AHC273; 74AHCT273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger Table 2. Pin description …continued Symbol Pin Description D6 17 data input D7 18 data input Q7 19 flip-flop output VCC 20 supply voltage 6. Functional description Table 3. Function table[1] Operating mode Input Output MR CP Dn Qn Reset (clear) L X X L Load ‘1’ H ↑ h H Load ‘0’ H ↑ l L [1] Control H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; ↑ = LOW-to-HIGH; X = don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI input voltage Conditions Min Max Unit −0.5 +7.0 V −0.5 +7.0 V −20 - mA −20 +20 mA −25 +25 mA IIK input clamping current VI < −0.5 V [1] IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V [1] IO output current VO = −0.5 V to (VCC + 0.5 V) ICC supply current - +75 mA IGND ground current −75 - mA Tstg storage temperature −65 +150 °C - 500 mW total power dissipation Ptot Tamb = −40 °C to +125 °C [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO20 packages: above 70 °C the value of Ptot derates linearly at 8 mW/K. For TSSOP20 packages: above 60 °C the value of Ptot derates linearly at 5.5 mW/K. For DHVQFN20 packages: above 60 °C the value of Ptot derates linearly at 4.5 mW/K. 74AHC_AHCT273_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 13 May 2008 5 of 18 74AHC273; 74AHCT273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger 8. Recommended operating conditions Table 5. Operating conditions Symbol Parameter Conditions Min Typ Max Unit 74AHC273 VCC supply voltage 2.0 5.0 5.5 V VI input voltage 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature −40 +25 +125 °C ∆t/∆V input transition rise and fall rate VCC = 3.0 V to 3.6 V - - 100 ns/V VCC = 4.5 V to 5.5 V - - 20 ns/V 74AHCT273 VCC supply voltage 4.5 5.0 5.5 V VI input voltage 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature −40 +25 +125 °C ∆t/∆V input transition rise and fall rate - - 20 ns/V VCC = 4.5 V to 5.5 V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max 74AHC273 VIH VIL VOH VOL HIGH-level input voltage VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V LOW-level input voltage VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V VCC = 3.0 V - - 0.9 - 0.9 - 0.9 V VCC = 5.5 V - - 1.65 - 1.65 - 1.65 V HIGH-level VI = VIH or VIL output voltage IO = −50 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = −50 µA; VCC = 3.0 V 2.9 3.0 - 2.9 - 2.9 - V IO = −50 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = −4.0 mA; VCC = 3.0 V 2.58 - - 2.48 - 2.40 - V IO = −8.0 mA; VCC = 4.5 V 3.94 - - 3.80 - 3.70 - V LOW-level VI = VIH or VIL output voltage IO = 50 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 µA; VCC = 3.0 V - 0 0.1 - 0.1 - 0.1 V IO = 50 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 3.0 V - - 0.36 - 0.44 - 0.55 V IO = 8.0 mA; VCC = 4.5 V - - 0.36 - 0.44 - 0.55 V 74AHC_AHCT273_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 13 May 2008 6 of 18 74AHC273; 74AHCT273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions VI = 5.5 V or GND; VCC = 0 V to 5.5 V −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max - - 0.1 - 1.0 - 2.0 µA II input leakage current ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 4.0 - 40 - 80 µA CI input capacitance - 3 10 - 10 - 10 pF CO output capacitance - 4 - - - - - pF 74AHCT273 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V VOH HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = −50 µA 4.4 - - 4.4 - 4.4 - V 3.94 - - 3.80 - 3.70 - V - 0 0.1 - 0.1 - 0.1 V - - 0.36 - 0.44 - 0.55 V - - 0.1 - 1.0 - 2.0 µA IO = −8.0 mA VOL LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 50 µA IO = 8.0 mA II input leakage current VI = 5.5 V or GND; VCC = 0 V to 5.5 V ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 4.0 - 40 - 80 µA ∆ICC additional per input pin; supply current VI = VCC − 2.1 V; other pins at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.5 V - - 1.35 - 1.5 - 1.5 mA CI input capacitance - 3 10 - 10 - 10 pF CO output capacitance - 4 - - - - - pF 74AHC_AHCT273_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 13 May 2008 7 of 18 74AHC273; 74AHCT273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10. Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max Min Max CL = 15 pF - 6.0 13.6 1.0 16.0 1.0 17.0 ns CL = 50 pF - 8.6 17.1 1.0 19.5 1.0 21.5 ns - 4.2 9 1.0 10.5 1.0 11.5 ns - 6.0 11.0 1.0 12.5 1.0 14.0 ns CL = 15 pF - 5.1 13.6 1.0 16.0 1.0 17.0 ns CL = 50 pF - 7.3 17.1 1.0 19.5 1.0 21.5 ns CL = 15 pF - 3.7 8.5 1.0 10.0 1.0 11.0 ns CL = 50 pF - 5.3 10.5 1.0 12.0 1.0 13.5 ns CL = 15 pF 75 120 - 65 - 65 - MHz CL = 50 pF 50 75 - 45 - 45 - MHz CL = 15 pF 120 165 - 100 - 100 - MHz CL = 50 pF 80 110 - 70 - 70 - MHz VCC = 3.0 V to 3.6 V 5.0 - - 6.5 - 6.5 - ns VCC = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns VCC = 3.0 V to 3.6 V 5.0 - - 6.0 - 6.0 - ns VCC = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns VCC = 3.0 V to 3.6 V 3.0 - - 3.0 - 3.0 - ns VCC = 4.5 V to 5.5 V 3.0 - - 3.0 - 3.0 - ns VCC = 3.0 V to 3.6 V 1.0 - - 1.0 - 1.0 - ns VCC = 4.5 V to 5.5 V 1.0 - - 1.0 - 1.0 - ns 74AHC273 tpd propagation CP to Qn; see Figure 7 delay VCC = 3.0 V to 3.6 V [2] VCC = 4.5 V to 5.5 V CL = 15 pF CL = 50 pF MR to Qn; see Figure 8 [3] VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V fmax maximum frequency see Figure 7 VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V tW pulse width CP HIGH or LOW; see Figure 7 MR LOW; see Figure 8 tsu th set-up time hold time Dn to CP; see Figure 9 Dn to CP; see Figure 9 74AHC_AHCT273_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 13 May 2008 8 of 18 74AHC273; 74AHCT273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10. Symbol Parameter trec CPD recovery time 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max Min Max VCC = 3.0 V to 3.6 V 2.5 - - 2.5 - 2.5 - ns VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - ns - 14 - - - - - pF - 4.0 7.5 1.0 8.8 1.0 9.5 ns - 5.8 9.2 1.0 10.5 1.0 11.5 ns CL = 15 pF - 3.9 10.0 1.0 11.6 1.0 12.5 ns CL = 50 pF - 5.6 11.0 1.0 12.6 1.0 14.0 ns CL = 15 pF 75 120 - 65 - 65 - MHz CL = 50 pF 50 75 - 45 - 45 - MHz CP HIGH or LOW; see Figure 7 5.0 - - 6.5 - 6.5 - ns MR LOW; see Figure 8 5.0 - - 6.0 - 6.0 - ns MR to CP; see Figure 8 fi = 1 MHz; VI = GND to VCC power dissipation capacitance [4] 74AHCT273; VCC = 4.5 V to 5.5 V tpd [2] propagation CP to Qn; see Figure 7 delay CL = 15 pF CL = 50 pF [3] MR to Qn; see Figure 8 fmax tW maximum frequency pulse width see Figure 7 tsu set-up time Dn to CP; see Figure 9 3.0 - - 3.0 - 3.0 - ns th hold time Dn to CP; see Figure 9 1.0 - - 1.0 - 1.0 - ns trec recovery time MR to CP; see Figure 8 2.5 - - 2.5 - 2.5 - ns CPD power fi = 1 MHz; VI = GND to VCC dissipation capacitance - 18 - - - - - pF [4] [1] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). [2] tpd is the same as tPLH and tPHL. [3] tpd is the same as tPHL only. [4] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. 74AHC_AHCT273_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 13 May 2008 9 of 18 74AHC273; 74AHCT273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger 11. Waveforms 1/fmax VI CP input VM GND tW t PHL t PLH VOH VM Qn output 001aac426 VOL Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Clock pulse width, maximum frequency and input to output propagation delays VI VM MR input GND tW trec VI CP input VM GND tPHL VOH VM Qn output VOL mna464 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Master reset pulse width, recovery time and propagation delay 74AHC_AHCT273_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 13 May 2008 10 of 18 74AHC273; 74AHCT273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger VI VM CP input GND tsu tsu th th VI VM Dn input GND VOH VM Qn output VOL mna202 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical voltage output levels that occur with the output load. Fig 9. Data set-up and hold times Table 8. Measurement points Type Input Output VM VM 74AHC273 0.5 × VCC 0.5 × VCC 74AHCT273 1.5 V 0.5 × VCC 74AHC_AHCT273_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 13 May 2008 11 of 18 74AHC273; 74AHCT273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger VI negative pulse tW 90 % VM VM 10 % GND tr tf tr VI positive pulse GND tf 90 % VM VM 10 % tW VCC G VI VO DUT RT CL 001aah768 Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. Fig 10. Load circuitry for measuring switching times Table 9. Test data Type Input Load Test VI tr, tf CL 74AHC273 VCC ≤ 3.0 ns 15 pF, 50 pF tPLH, tPHL 74AHCT273 3.0 V ≤ 3.0 ns 15 pF, 50 pF tPLH, tPHL 74AHC_AHCT273_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 13 May 2008 12 of 18 74AHC273; 74AHCT273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 10 1 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT163-1 (SO20) 74AHC_AHCT273_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 13 May 2008 13 of 18 74AHC273; 74AHCT273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 12. Package outline SOT360-1 (TSSOP20) 74AHC_AHCT273_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 13 May 2008 14 of 18 74AHC273; 74AHCT273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 9 y y1 C v M C A B w M C b L 1 10 Eh e 20 11 19 12 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b 1 0.05 0.00 0.30 0.18 mm c D (1) Dh E (1) Eh 0.2 4.6 4.4 3.15 2.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 3.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT764-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 13. Package outline SOT764-1 (DHVQFN20) 74AHC_AHCT273_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 13 May 2008 15 of 18 74AHC273; 74AHCT273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model MOS Metal-Oxide Semiconductor 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AHC_AHCT273_3 20080513 Product data sheet - 74AHC_AHCT273_2 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Table 6: the conditions for input leakage current have been changed. 74AHC_AHCT273_2 20030721 Product specification - 74AHC_AHCT273_1 74AHC_AHCT273_1 19990901 Product specification - - 74AHC_AHCT273_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 13 May 2008 16 of 18 74AHC273; 74AHCT273 NXP Semiconductors Octal D-type flip-flop with reset; positive-edge trigger 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74AHC_AHCT273_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 13 May 2008 17 of 18 NXP Semiconductors 74AHC273; 74AHCT273 Octal D-type flip-flop with reset; positive-edge trigger 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 13 May 2008 Document identifier: 74AHC_AHCT273_3