PHILIPS 74LVC2G125

74LVC2G125
Dual bus buffer/line driver; 3-state
Rev. 10 — 11 June 2008
Product data sheet
1. General description
The 74LVC2G125 provides a dual non-inverting buffer/line driver with 3-state output.
The 3-state output is controlled by the output enable input (pin nOE). A HIGH-level at pin
nOE causes the output to assume a high-impedance OFF-state. Schmitt trigger action at
all inputs makes the circuit highly tolerant of slower input rise and fall times.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing a damaging backflow current through the device
when it is powered down.
2. Features
n
n
n
n
n
n
n
n
n
n
n
n
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
u JESD8-7 (1.65 V to 1.95 V)
u JESD8-5 (2.3 V to 2.7 V)
u JESD8-B/JESD36 (2.7 V to 3.6 V)
ESD protection:
u HBM JESD22-A114E exceeds 2000 V
u MM JESD22-A115-A exceeds 200 V
±24 mA output drive (VCC = 3.0 V)
CMOS low-power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from −40 °C to +85 °C and −40 °C to +125 °C
74LVC2G125
NXP Semiconductors
Dual bus buffer/line driver; 3-state
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC2G125DP
−40 °C to +125 °C
TSSOP8
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
74LVC2G125DC
−40 °C to +125 °C
VSSOP8
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
74LVC2G125GT
−40 °C to +125 °C
XSON8
plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1 × 1.95 × 0.5 mm
74LVC2G125GD
−40 °C to +125 °C
XSON8U
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; UTLP based; body 3 × 2 × 0.5 mm
74LVC2G125GM
−40 °C to +125 °C
XQFN8U
plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm
SOT902-1
4. Marking
Table 2.
Marking codes
Type number
Marking code
74LVC2G125DP
V25
74LVC2G125DC
V25
74LVC2G125GT
V25
74LVC2G125GD
V25
74LVC2G125GM
V25
5. Functional diagram
74LVC2G125
1A
74LVC2G125
1Y
1
EN1
1OE
2A
2Y
2
2OE
EN2
001aae009
mna941
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74LVC2G125_10
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 10 — 11 June 2008
2 of 17
74LVC2G125
NXP Semiconductors
Dual bus buffer/line driver; 3-state
6. Pinning information
6.1 Pinning
74LVC2G125
1OE
1
8
VCC
1A
2
7
2OE
2Y
3
6
1Y
GND
4
5
2A
74LVC2G125
1OE
1
8
VCC
1A
2
7
2OE
2Y
3
6
1Y
GND
4
5
2A
001aab739
Transparent top view
001aab738
Fig 3.
Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8)
Fig 4.
Pin configuration SOT833-1 (XSON8)
74LVC2G125
74LVC2G125
1
8
VCC
1A
2
7
2OE
2Y
3
6
1Y
GND
4
5
2A
1
1Y
2A
8
2OE
7
1OE
2
6
1A
3
5
2Y
GND
4
1OE
VCC
terminal 1
index area
001aai243
Transparent top view
Transparent top view
Fig 5.
001aae010
Pin configuration XSON8
Fig 6.
Pin configuration XQFN8U
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
SOT505-2, SOT765-1,
SOT833-1 and SOT996-2
SOT902-1
1OE, 2OE
1, 7
7, 1
output enable input (active LOW)
1A, 2A
2, 5
6, 3
data input
GND
4
4
ground (0 V)
1Y, 2Y
6, 3
2, 5
data output
VCC
8
8
supply voltage
74LVC2G125_10
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 10 — 11 June 2008
3 of 17
74LVC2G125
NXP Semiconductors
Dual bus buffer/line driver; 3-state
7. Functional description
Table 4.
Function table[1]
Control
Input
Output
nOE
nA
nY
L
L
L
L
H
H
H
X
Z
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground 0 V).
Symbol
Parameter
VCC
supply voltage
Conditions
IIK
input clamping current
VI
input voltage
IOK
output clamping current
[1]
output voltage
VO
VI < 0 V
Min
Max
Unit
−0.5
+6.5
V
−50
-
mA
−0.5
+6.5
V
-
±50
mA
Enable mode
[1]
−0.5
VCC + 0.5
V
Disable mode
[1]
−0.5
+6.5
V
[1][2]
−0.5
+6.5
V
-
±50
mA
100
mA
VO > VCC or VO < 0 V
Power-down mode
IO
output current
VO = 0 V to VCC
ICC
supply current
-
IGND
ground current
−100
-
mA
Tstg
storage temperature
−65
+150
°C
Ptot
total power dissipation
-
300
mW
Tamb = −40 °C to +125 °C
[3]
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3]
For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K.
For XSON8, XSON8U and XQFN8U packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 6.
Operating conditions
Symbol
Parameter
VCC
supply voltage
VI
input voltage
VO
output voltage
Conditions
Max
Unit
1.65
5.5
V
0
5.5
V
VCC = 1.65 V to 5.5 V; Enable mode
0
VCC
V
VCC = 1.65 V to 5.5 V; Disable mode
0
5.5
V
VCC = 0 V; Power-down mode
0
5.5
V
74LVC2G125_10
Product data sheet
Min
© NXP B.V. 2008. All rights reserved.
Rev. 10 — 11 June 2008
4 of 17
74LVC2G125
NXP Semiconductors
Dual bus buffer/line driver; 3-state
Table 6.
Operating conditions …continued
Symbol
Parameter
Min
Max
Unit
Tamb
ambient temperature
Conditions
−40
+125
°C
∆t/∆V
input transition rise and VCC = 1.65 V to 2.7 V
fall rate
VCC = 2.7 V to 5.5 V
-
20
ns/V
-
10
ns/V
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VCC = 1.65 V to 1.95 V
0.65VCC
-
-
V
VCC = 2.3 V to 2.7 V
1.7
-
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
V
VCC = 4.5 V to 5.5 V
0.7VCC
-
-
V
VCC = 1.65 V to 1.95 V
-
-
0.35VCC
V
VCC = 2.3 V to 2.7 V
-
-
0.7
V
VCC = 2.7 V to 3.6 V
-
-
0.8
V
VCC = 4.5 V to 5.5 V
-
-
0.3VCC
V
IO = 100 µA; VCC = 1.65 V to 5.5 V
-
-
0.1
V
Tamb = −40 °C to +85 °C[1]
VIH
VIL
VOL
VOH
HIGH-level input voltage
LOW-level input voltage
LOW-level output voltage
VI = VIH or VIL
IO = 4 mA; VCC = 1.65 V
-
-
0.45
V
IO = 8 mA; VCC = 2.3 V
-
-
0.3
V
IO = 12 mA; VCC = 2.7 V
-
-
0.4
V
IO = 24 mA; VCC = 3.0 V
-
-
0.55
V
IO = 32 mA; VCC = 4.5 V
-
-
0.55
V
IO = −100 µA; VCC = 1.65 V to 5.5 V
VCC − 0.1
-
-
V
IO = −4 mA; VCC = 1.65 V
1.2
-
-
V
HIGH-level output voltage VI = VIH or VIL
IO = −8 mA; VCC = 2.3 V
1.9
-
-
V
IO = −12 mA; VCC = 2.7 V
2.2
-
-
V
IO = −24 mA; VCC = 3.0 V
2.3
-
-
V
IO = −32 mA; VCC = 4.5 V
3.8
-
-
V
II
input leakage current
VI = 5.5 V or GND; VCC = 0 V to 5.5 V
-
±0.1
±5
µA
IOZ
OFF-state output current
VI = VIH or VIL; VO = 5.5 V or GND;
VCC = 3.6 V
-
±0.1
±10
µA
IOFF
power-off leakage current
VI or VO = 5.5 V; VCC = 0 V
-
±0.1
±10
µA
ICC
supply current
VI = 5.5 V or GND;
VCC = 1.65 V to 5.5 V; IO = 0 A
-
0.1
10
µA
∆ICC
additional supply current
per pin; VI = VCC − 0.6 V; IO = 0 A;
VCC = 2.3 V to 5.5 V
-
5
500
µA
Ci
input capacitance
-
2
-
pF
74LVC2G125_10
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 10 — 11 June 2008
5 of 17
74LVC2G125
NXP Semiconductors
Dual bus buffer/line driver; 3-state
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VCC = 1.65 V to 1.95 V
0.65VCC
-
-
V
VCC = 2.3 V to 2.7 V
1.7
-
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
V
VCC = 4.5 V to 5.5 V
0.7VCC
-
-
V
VCC = 1.65 V to 1.95 V
-
-
0.35VCC
V
Tamb = −40 °C to +125 °C
HIGH-level input voltage
VIH
LOW-level input voltage
VIL
LOW-level output voltage
VOL
VOH
VCC = 2.3 V to 2.7 V
-
-
0.7
V
VCC = 2.7 V to 3.6 V
-
-
0.8
V
VCC = 4.5 V to 5.5 V
-
-
0.3VCC
V
VI = VIH or VIL
IO = 100 µA; VCC = 1.65 V to 5.5 V
-
-
0.1
V
IO = 4 mA; VCC = 1.65 V
-
-
0.70
V
IO = 8 mA; VCC = 2.3 V
-
-
0.45
V
IO = 12 mA; VCC = 2.7 V
-
-
0.60
V
IO = 24 mA; VCC = 3.0 V
-
-
0.80
V
IO = 32 mA; VCC = 4.5 V
-
-
0.80
V
IO = −100 µA; VCC = 1.65 V to 5.5 V
VCC − 0.1
-
-
V
HIGH-level output voltage VI = VIH or VIL
IO = −4 mA; VCC = 1.65 V
0.95
-
-
V
IO = −8 mA; VCC = 2.3 V
1.7
-
-
V
IO = −12 mA; VCC = 2.7 V
1.9
-
-
V
IO = −24 mA; VCC = 3.0 V
2.0
-
-
V
IO = −32 mA; VCC = 4.5 V
3.4
-
-
V
II
input leakage current
VI = 5.5 V or GND; VCC = 0 V to 5.5 V
-
-
±20
µA
IOZ
OFF-state output current
VI = VIH or VIL; VO = 5.5 V or GND;
VCC = 3.6 V
-
-
±20
µA
IOFF
power-off leakage current
VI or VO = 5.5 V; VCC = 0 V
-
-
±20
µA
ICC
supply current
VI = 5.5 V or GND;
VCC = 1.65 V to 5.5 V; IO = 0 A
-
-
40
µA
∆ICC
additional supply current
per pin; VI = VCC − 0.6 V; IO = 0 A;
VCC = 2.3 V to 5.5 V
-
-
5
mA
[1]
Typical values are measured at VCC = 3.3 V and Tamb = 25 °C.
74LVC2G125_10
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 10 — 11 June 2008
6 of 17
74LVC2G125
NXP Semiconductors
Dual bus buffer/line driver; 3-state
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground 0 V); for test circuit see Figure 9.
Symbol Parameter
−40 °C to +85 °C
Conditions
enable time
ten
Max
Min
Max
VCC = 1.65 V to 1.95 V
1.0
3.7
9.1
1.0
11.4
ns
VCC = 2.3 V to 2.7 V
0.5
2.5
4.8
0.5
6.0
ns
VCC = 2.7 V
1.0
2.7
4.8
1.0
6.0
ns
VCC = 3.0 V to 3.6 V
0.5
2.3
4.3
0.5
5.5
ns
VCC = 4.5 V to 5.5 V
0.5
1.9
3.7
0.5
4.6
ns
VCC = 1.65 V to 1.95 V
1.5
4.3
9.9
1.5
12.4
ns
VCC = 2.3 V to 2.7 V
1.0
2.8
5.6
1.0
7.0
ns
VCC = 2.7 V
1.5
3.3
5.7
1.5
7.1
ns
VCC = 3.0 V to 3.6 V
0.5
2.4
4.7
0.5
5.9
ns
0.5
2.0
3.8
0.5
4.8
ns
VCC = 1.65 V to 1.95 V
1.0
3.5
11.6
1.0
14.1
ns
VCC = 2.3 V to 2.7 V
0.5
1.8
5.8
0.5
7.6
ns
VCC = 2.7 V
1.0
2.7
4.8
1.0
6.2
ns
VCC = 3.0 V to 3.6 V
1.0
2.7
4.6
1.0
5.9
ns
VCC = 4.5 V to 5.5 V
0.5
1.8
3.4
0.5
4.6
ns
output enabled
-
18
-
-
-
pF
output disabled
-
5
-
-
-
pF
nOE to nY; see Figure 8
[2]
[3]
VCC = 4.5 V to 5.5 V
disable time
tdis
power dissipation
capacitance
CPD
nOE to nY; see Figure 8
per buffer; VI = GND to VCC
[4]
[5]
[1]
Typical values are measured at nominal VCC and at Tamb = 25 °C.
[2]
tpd is the same as tPLH and tPHL.
[3]
ten is the same as tPZH and tPZL.
[4]
tdis is the same as tPLZ and tPHZ.
[5]
CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of outputs.
74LVC2G125_10
Product data sheet
Unit
Min
propagation delay nA to nY; see Figure 7
tpd
−40 °C to +125 °C
Typ[1]
© NXP B.V. 2008. All rights reserved.
Rev. 10 — 11 June 2008
7 of 17
74LVC2G125
NXP Semiconductors
Dual bus buffer/line driver; 3-state
12. Waveforms
VI
VM
nA input
GND
tPHL
tPLH
VOH
VM
nY output
VOL
mna230
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7.
Propagation delay input (nA) to output (nY)
VI
nOE input
VM
GND
tPLZ
tPZL
VCC
output
LOW-to-OFF
OFF-to-LOW
VM
VX
VOL
tPHZ
VOH
tPZH
VY
output
HIGH-to-OFF
OFF-to-HIGH
GND
VM
outputs
enabled
outputs
disabled
outputs
enabled
mna362
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8.
Table 9.
3-state output enable and disable times
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
VX
VY
1.65 V to 1.95 V
0.5VCC
0.5VCC
VOL + 0.15 V
VOH − 0.15 V
2.3 V to 2.7 V
0.5VCC
0.5VCC
VOL + 0.15 V
VOH − 0.15 V
2.7 V
1.5 V
1.5 V
VOL + 0.3 V
VOH − 0.3 V
3.0 V to 3.6 V
1.5 V
1.5 V
VOL + 0.3 V
VOH − 0.3 V
4.5 V to 5.5 V
0.5VCC
0.5VCC
VOL + 0.3 V
VOH − 0.3 V
74LVC2G125_10
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 10 — 11 June 2008
8 of 17
74LVC2G125
NXP Semiconductors
Dual bus buffer/line driver; 3-state
VEXT
VCC
VI
RL
VO
G
DUT
RT
CL
RL
mna616
Test data is given in Table 10.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
VEXT = Test voltage for switching times.
Fig 9.
Table 10.
Load circuitry for switching times
Test data
Supply voltage
Input
Load
VEXT
VCC
VI
tr, tf
CL
RL
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
1.65 V to 1.95 V
VCC
≤ 2.0 ns
30 pF
1 kΩ
open
GND
2VCC
2.3 V to 2.7 V
VCC
≤ 2.0 ns
30 pF
500 Ω
open
GND
2VCC
2.7 V
2.7 V
≤ 2.5 ns
50 pF
500 Ω
open
GND
6V
3.0 V to 3.6 V
2.7 V
≤ 2.5 ns
50 pF
500 Ω
open
GND
6V
4.5 V to 5.5 V
VCC
≤ 2.5 ns
50 pF
500 Ω
open
GND
2VCC
74LVC2G125_10
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 10 — 11 June 2008
9 of 17
74LVC2G125
NXP Semiconductors
Dual bus buffer/line driver; 3-state
13. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
D
E
A
SOT505-2
X
c
HE
y
v M A
Z
5
8
A
A2
(A3)
A1
pin 1 index
θ
Lp
L
1
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(1)
e
HE
L
Lp
v
w
y
Z(1)
θ
mm
1.1
0.15
0.00
0.95
0.75
0.25
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
0.65
4.1
3.9
0.5
0.47
0.33
0.2
0.13
0.1
0.70
0.35
8°
0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT505-2
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-01-16
---
Fig 10. Package outline SOT502-2 (TSSOP8)
74LVC2G125_10
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 10 — 11 June 2008
10 of 17
74LVC2G125
NXP Semiconductors
Dual bus buffer/line driver; 3-state
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
D
E
SOT765-1
A
X
c
y
HE
v M A
Z
5
8
Q
A
A2
A1
pin 1 index
(A3)
θ
Lp
1
4
e
L
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(2)
e
HE
L
Lp
Q
v
w
y
Z(1)
θ
mm
1
0.15
0.00
0.85
0.60
0.12
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
0.5
3.2
3.0
0.4
0.40
0.15
0.21
0.19
0.2
0.13
0.1
0.4
0.1
8°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT765-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-06-07
MO-187
Fig 11. Package outline SOT765-1 (VSSOP8)
74LVC2G125_10
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 10 — 11 June 2008
11 of 17
74LVC2G125
NXP Semiconductors
Dual bus buffer/line driver; 3-state
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
1
2
SOT833-1
b
4
3
4×
(2)
L
L1
e
8
7
6
e1
5
e1
e1
8×
A
(2)
A1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max
A1
max
b
D
E
e
e1
L
L1
mm
0.5
0.04
0.25
0.17
2.0
1.9
1.05
0.95
0.6
0.5
0.35
0.27
0.40
0.32
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT833-1
---
MO-252
---
EUROPEAN
PROJECTION
ISSUE DATE
07-11-14
07-12-07
Fig 12. Package outline SOT833-1 (XSON8)
74LVC2G125_10
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 10 — 11 June 2008
12 of 17
74LVC2G125
NXP Semiconductors
Dual bus buffer/line driver; 3-state
XSON8U: plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 x 2 x 0.5 mm
B
D
SOT996-2
A
A
E
A1
detail X
terminal 1
index area
e1
v
w
b
e
L1
1
4
8
5
C
C A B
C
M
M
y
y1 C
L2
L
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
b
D
E
e
e1
L
L1
L2
v
w
y
y1
mm
0.5
0.05
0.00
0.35
0.15
2.1
1.9
3.1
2.9
0.5
1.5
0.5
0.3
0.15
0.05
0.6
0.4
0.1
0.05
0.05
0.1
REFERENCES
OUTLINE
VERSION
IEC
SOT996-2
---
JEDEC
JEITA
---
EUROPEAN
PROJECTION
ISSUE DATE
07-12-18
07-12-21
Fig 13. Package outline SOT996-2 (XSON8U)
74LVC2G125_10
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 10 — 11 June 2008
13 of 17
74LVC2G125
NXP Semiconductors
Dual bus buffer/line driver; 3-state
XQFN8U: plastic extremely thin quad flat package; no leads;
8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm
B
D
SOT902-1
A
terminal 1
index area
E
A
A1
detail X
L1
e
e
C
∅v M C A B
∅w M C
L
4
y1 C
y
5
3
metal area
not for soldering
e1
b
2
6
e1
7
1
terminal 1
index area
8
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
b
D
E
e
e1
L
L1
v
w
y
y1
mm
0.5
0.05
0.00
0.25
0.15
1.65
1.55
1.65
1.55
0.55
0.5
0.35
0.25
0.15
0.05
0.1
0.05
0.05
0.05
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT902-1
---
MO-255
---
EUROPEAN
PROJECTION
ISSUE DATE
05-11-25
07-11-14
Fig 14. Package outline SOT902-1 (XQFN8U)
74LVC2G125_10
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 10 — 11 June 2008
14 of 17
74LVC2G125
NXP Semiconductors
Dual bus buffer/line driver; 3-state
14. Abbreviations
Table 11.
Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LVC2G125_10
20080611
Product data sheet
-
74LVC2G125_9
Modifications:
•
Section 8: derating factor for TSSOP8, VSSOP8, XSON8, XSON8U and XQFN8U package
added
•
Added type number 74LVC2G125GD (XSON8U package)
74LVC2G125_9
20080226
Product data sheet
-
74LVC2G125_8
74LVC2G125_8
20070907
Product data sheet
-
74LVC2G125_7
74LVC2G125_7
20060523
Product data sheet
-
74LVC2G125_6
74LVC2G125_6
20051223
Product data sheet
-
74LVC2G125_5
74LVC2G125_5
20050201
Product specification
-
74LVC2G125_4
74LVC2G125_4
20040922
Product specification
-
74LVC2G125_3
74LVC2G125_3
20040109
Product specification
-
74LVC2G125_2
74LVC2G125_2
20030901
Product specification
-
74LVC2G125_1
74LVC2G125_1
20030310
Product specification
-
-
74LVC2G125_10
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 10 — 11 June 2008
15 of 17
74LVC2G125
NXP Semiconductors
Dual bus buffer/line driver; 3-state
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74LVC2G125_10
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 10 — 11 June 2008
16 of 17
74LVC2G125
NXP Semiconductors
Dual bus buffer/line driver; 3-state
18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 11 June 2008
Document identifier: 74LVC2G125_10