INTEGRATED CIRCUITS SSTVF16857 DDR PC1600-PC3200 14-bit SSTL_2 registered driver with differential clock inputs Product data Philips Semiconductors 2003 Sep 19 Philips Semiconductors Product data DDR PC1600-PC3200 14-bit SSTL_2 registered driver with differential clock inputs FEATURES SSTVF16857 PIN CONFIGURATION • Stub-series terminated logic for 2.5 V VDDQ (SSTL_2) • Optimized for PC 2700 DDR (Double Data Rate) SDRAM applications • Suitable for PC1600/PC2100 DDR SDRAM applications • Suitable for PC3200 applications when used at VDD = 2.6 V • Inputs compatible with JESD8-9 SSTL_2 specifications. • Flow-through architecture optimizes PCB layout • ESD classification testing is done to JEDEC Standard JESD22. Protection exceeds 2000 V to HBM per method A114. • Latch-up testing is done to JEDEC Standard JESD78, which exceeds 100 mA. • Full DDR300/333/400 solution @ 2.5V when used with PCKV857 • Available in TSSOP-48, TVSOP-48 and 56 ball VFBGA packages • Superior VREF noise rejection DESCRIPTION The SSTVF16857 is a 14-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V. VDDQ must not exceed VCC. Inputs are SSTL_2 type with VREF normally at 0.5*VDDQ. The outputs support class I which can be used for standard stub-series applications or capacitive loads. Master reset (RESET) asynchronously resets all registers to zero. The SSTVF16857 is intended to be incorporated into standard DIMM (Dual In-Line Memory Module) designs defined by JEDEC, such as DDR (Double Data Rate) SDRAM or SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR DRAM rated at 166 MHz will have a burst rate of 333 MT/s (mega-transfers per second). The modules require between 23 and 27 registered control and address lines, so two 14-bit wide devices will be used on each module. The SSTVF16857 is intended to be used for SSTL_2 input and output signals. Q1 1 48 D1 Q2 2 47 D2 GND 3 46 GND VDDQ 4 45 VCC Q3 5 44 D3 Q4 6 43 D4 Q5 7 42 D5 GND 8 41 D6 VDDQ 9 40 D7 Q6 10 39 CLK- Q7 11 38 CLK+ VDDQ 12 37 VCC GND 13 36 GND Q8 14 35 VREF Q9 15 34 RESET VDDQ 16 33 D8 GND 17 32 D9 Q10 18 31 D10 Q11 19 30 D11 Q12 20 29 D12 VDDQ 21 28 VCC GND 22 27 GND Q13 23 26 D13 Q14 24 25 D14 SW00685 The device data inputs consist of differential receivers. One differential input is tied to the input pin while the other is tied to a reference input pad, which is shared by all inputs. The clock input is fully differential to be compatible with DRAM devices that are installed on the DIMM. However, since the control inputs to the SDRAM change at only half the data rate, the device must only change state on the positive transition of the CLK signal. In order to be able to provide defined outputs from the device even before a stable clock has been supplied, the device must support an asynchronous input pin (reset), which when held to the LOW state will assume that all registers are reset to the LOW state and all outputs drive a LOW signal as well. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr =tf v2.5 ns SYMBOL tPHL/tPLH CI 2003 Sep 19 TYPICAL UNIT Propagation delay; CLK to Qn PARAMETER CL = 30 pF; VDDQ = 2.5 V CONDITIONS 1.9 ns Input capacitance VCC = 2.5 V 2.9 pF 2 Philips Semiconductors Product data DDR PC1600-PC3200 14-bit SSTL_2 registered driver with differential clock inputs SSTVF16857 ORDERING INFORMATION TEMPERATURE RANGE ORDER CODE DWG NUMBER 48-Pin Plastic TSSOP Type I PACKAGES 0 to +70 °C SSTVF16857DGG SOT362-1 48-Pin Plastic TSSOP (TVSOP) 0 to +70 °C SSTVF16857DGV SOT480-1 56-Ball Plastic VFBGA 0 to +70 °C SSTVF16857EV SOT702-1 PIN DESCRIPTION PIN NUMBER SYMBOL 34 RESET LOGIC DIAGRAM NAME AND FUNCTION LVCMOS asynchronous master reset (Active LOW) RESET VREF D1 REGISTER Q1 D2 REGISTER Q2 SSTL_2 data outputs D3 REGISTER Q3 VREF SSTL_2 input reference level D4 REGISTER Q4 3, 8, 13, 17, 22, 27, 36, 46 GND Ground (0 V) D5 REGISTER Q5 28, 37, 45 VCC Positive supply voltage 4, 9, 12, 16, 21 VDDQ Output supply voltage D6 REGISTER Q6 38 39 CLK+ CLK- Differential clock inputs D7 REGISTER Q7 D8 REGISTER Q8 D9 REGISTER Q9 D10 REGISTER Q10 D11 REGISTER Q11 D12 REGISTER Q12 D13 REGISTER Q13 D14 REGISTER Q14 48, 47, 44, 43, 42, 41, 40, 33, 32, 31, 30, 29, 26, 25 D1 - D14 1, 2, 5, 6, 7, 10, 11, 14, 15, 18, 19, 20, 23, 24 Q1 - Q14 35 SSTL_2 data inputs FUNCTION TABLE OUTPUT INPUTS D Q RESET CLK CLK L X X X L H ↓ ↑ H H H ↓ ↑ L L H L or H L or H X Q0 H = High voltage level L = High voltage level ↓ = High-to-Low transition ↑ = Low-to-High transition X = Don’t care CLK+ CLK- 2003 Sep 19 3 SW00763 Philips Semiconductors Product data DDR PC1600-PC3200 14-bit SSTL_2 registered driver with differential clock inputs SSTVF16857 BALL CONFIGURATION 1 2 3 4 5 6 A Q1 NC NC NC NC D1 B GND Q2 VCC VCC D2 GND C Q4 Q3 Q5 D5 D3 D4 D VCC GND Q6 CLK- D6 D7 E VCC Q7 CLK+ VCC F GND Q8 VREF GND G VCC GND Q9 RESET D9 D8 H Q11 Q12 Q10 D10 D12 D11 J GND Q13 VCC VCC D13 GND K Q14 NC NC NC NC D14 SW00952 ABSOLUTE MAXIMUM RATINGS1 SYMBOL PARAMETER VCC DC supply voltage IIK DC input diode current VI DC input voltage3 IOK DC output diode current VOUT DC output voltage3 IOUT CONDITION VI < 0 VO < 0 LIMITS UNIT MIN MAX -0.5 +4.6 V — -50 mA -0.5 VDDQ + 0.5 V — -50 mA V -0.5 VDDQ + 0.5 DC output current VO = 0 to VDDQ — ±50 Continuous current4 VCC, VDDQ, or GND — ±100 mA Tstg Storage temperature range2 -65 +150 °C NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 4. The continuous current at VCC, VDDQ, or GND should not exceed ±100 mA. 2003 Sep 19 4 Philips Semiconductors Product data DDR PC1600-PC3200 14-bit SSTL_2 registered driver with differential clock inputs SSTVF16857 RECOMMENDED OPERATING CONDITIONS1 SYMBOL PARAMETER VCC Supply voltage TEST CONDITIONS VDDQ Output supply voltage PC1600-PC2700 MIN TYP MAX UNIT 2.3 2.5 2.7 V 2.3 2.5 2.7 V 1.15 1.25 1.35 V VREF Reference voltage (VREF = 0.5 x VDDQ) 1.25 1.30 1.35 V VTT Termination voltage VREF - 40 mV VREF VREF + 40 mV V VI Input voltage 0 — VCC V VIH AC HIGH-level input voltage All inputs VREF + 310 mV — — V VIL AC LOW-level input voltage All inputs — — VREF - 310 mV V VIH DC HIGH-level input voltage All inputs VREF + 150 mV — VDDQ + 0.5 V V All inputs PC3200 VIL DC LOW-level input voltage VSS - 0.5 V — VREF - 150 mV V IOH HIGH-level output current — — -20 mA IOL LOW-level output current — — 20 mA 0 — 70 °C Tamb Operating free-air temperature range NOTE: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. DC ELECTRICAL CHARACTERISTICS—PC1600-PC2700 Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER VIK I/O supply voltage VOH HIGH-level output voltage VOL LOW-level output voltage TEST CONDITIONS Temp = 0 to +70 °C UNIT MIN TYP2 MAX — — -1.2 VCC - 0.2 — — 1.95 — — VCC = 2.3 V to 2.7 V; IOL = 100 µA — — 0.2 VCC = 2.3 V; IOL = 16 mA — — 0.35 VCC = 2.3 V; II = -18 mA VCC = 2.3 V to 2.7 V; IOH = -100 µA VCC = 2.3 V; IOH = -16 mA V V VCMR CLK, CLK Common mode range for reliable performance 0.97 — 1.53 V VPPmim CLK, CLK Minimum peak-to-peak input to ensure logic state — — 360 mV VCC = 2.7 V; VI = 1.7 V or 0.8 V — 0.01 ±5 — 0.01 ±5 — 0.05 ±5 — 0.05 ±5 Data inputs, RESET II ICC CI CLK, CLK VCC = 2.7 V; VI = 2.7 V or 0 V VCC = 2.7 V; VI = 1.7 V or 0.8 V VCC = 2.7 V; VI = 2.7 V or 0 V VREF = 1.15 V or 1.35 V VREF = 1.15 V or 1.35 V µ µA VREF VCC = 2.7 V VREF = 1.15 V or 1.35 V — 0.05 ±5 Quiescent supply current CLK and CLK in opposite state1 VCC = 2.7 V; VI = 1.7 V or 0.8 V RESET = GND — 0.5 10 µ µA VCC = 2.7 V; VI = 2.7 V or 0 V RESET = VCC — 10 25 mA Data inputs VI = VREF ± 310 mV, VCC = 2.5 V VREF = 1.15 V or 1.35 V 2.5 2.9 3.4 CLK, CLK VICR = 1.25 V, VI(PP) = 360 mV, VCC = 2.5 V VREF = 1.15 V or 1.35 V 2.5 2.9 3.4 RESET VI = VCC or GND, VCC = 2.5 V VREF = 1.15 V or 1.35 V 2.5 2.9 3.4 NOTES: 1. When CLK and CLK are HIGH, typical ICC = 25 mA. 2. All typical values are at VCC = 2.5 V and Tamb = 25 °C (unless otherwise specified). 2003 Sep 19 µ µA 5 µA pF Philips Semiconductors Product data DDR PC1600-PC3200 14-bit SSTL_2 registered driver with differential clock inputs SSTVF16857 DC ELECTRICAL CHARACTERISTICS—PC3200 Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL VIK PARAMETER I/O supply voltage VOH HIGH-level output voltage VOL LOW-level output voltage Temp = 0 to +70 °C TEST CONDITIONS VCC = 2.5 V; II = -18 mA UNIT MIN TYP2 MAX — — -1.2 VCC - 0.2 — — 1.95 — — VCC = 2.5 V to 2.7 V; IOL = 100 µA — — 0.2 VCC = 2.5 V; IOL = 16 mA — — 0.35 0.97 — 1.53 V mV VCC = 2.5 V to 2.7 V; IOH = -100 µA VCC = 2.5 V; IOH = -16 mA VCMR CLK, CLK Common mode range for reliable performance VPPmim CLK, CLK Minimum peak-to-peak input to ensure logic state — — 360 VCC = 2.7 V; VI = 1.7 V or 0.8 V — 0.01 ±5 — 0.01 ±5 — 0.05 ±5 — 0.05 ±5 Data inputs, RESET II ICC CI VCC = 2.7 V; VI = 2.7 V or 0 V VCC = 2.7 V; VI = 1.7 V or 0.8 V CLK, CLK VCC = 2.7 V; VI = 2.7 V or 0 V VREF = 1.25 V or 1.35 V VREF = 1.25 V or 1.35 V V V µ µA µ µA VREF VCC = 2.7 V VREF = 1.25 V or 1.35 V — 0.05 ±5 µA Quiescent supply current CLK and CLK in opposite state1 VCC = 2.7 V; VI = 1.7 V or 0.8 V RESET = GND — 0.5 10 µ µA VCC = 2.7 V; VI = 2.7 V or 0 V RESET = VCC — 10 25 mA Data inputs VI = VREF ± 310 mV, VCC = 2.6 V VREF = 1.25 V or 1.35 V 2.5 2.9 3.4 CLK, CLK VICR = 1.25 V, VI(PP) = 360 mV, VCC = 2.6 V VREF = 1.25 V or 1.35 V 2.5 2.9 3.4 RESET VI = VCC or GND, VCC = 2.6 V VREF = 1.25 V or 1.35 V 2.5 2.9 3.4 pF NOTES: 1. When CLK and CLK are HIGH, typical ICC = 25 mA. 2. All typical values are at VCC = 2.6 V and Tamb = 25 °C (unless otherwise specified). TIMING REQUIREMENTS—PC1600-PC2700 Over recommended operating conditions; Tamb = 0 to +70 °C (unless otherwise noted) (see Figure 1) LIMITS SYMBOL fclock PARAMETER TEST CONDITIONS VCC = 2.5 V ±0.2 V MIN MAX UNIT Clock frequency — 200 MHz tw Pulse duration, CLK, CLK HIGH or LOW 1.0 — ns Data before CLK↑, CLK↓ 0.2 — tsu Setup time RESET HIGH before CLK↑, CLK↓ 0.8 — th Hold time 0.75 — ns ns TIMING REQUIREMENTS—PC3200 Over recommended operating conditions; Tamb = 0 to +70 °C (unless otherwise noted) (see Figure 1) LIMITS SYMBOL fclock tw PARAMETER Clock frequency Pulse duration, CLK, CLK HIGH or LOW tsu Setup time th Hold time 2003 Sep 19 TEST CONDITIONS VCC = 2.5 V ±0.2 V MIN MAX — 210 MHz ns 1.0 — Data before CLK↑, CLK↓ 0.2 — RESET HIGH before CLK↑, CLK↓ 0.8 — 0.75 — 6 UNIT ns ns Philips Semiconductors Product data DDR PC1600-PC3200 14-bit SSTL_2 registered driver with differential clock inputs SSTVF16857 SWITCHING CHARACTERISTICS—PC1600-PC2700 Over recommended operating conditions; Tamb = 0 to +70 °C; VDDQ = 2.3 - 2.7 V and VDDQ does not exceed VCC. Class I, VREF = VTT = VDDQ × 0.5 and CL = 10 pF (unless otherwise noted) (see Figure 1) LIMITS FROM (INPUT) SYMBOL TO (OUTPUT) VCC = 2.5 V ±0.2 V MIN fmax tPLH/tPHL tPHL Maximum clock frequency UNIT MAX 200 — MHz CLK and CLK Q 1.0 2.6 ns RESET Q 2.0 4.0 ns SWITCHING CHARACTERISTICS—PC3200 Over recommended operating conditions; Tamb = 0 to +70 °C; VDDQ = 2.3 - 2.7 V and VDDQ does not exceed VCC. Class I, VREF = VTT = VDDQ × 0.5 and CL = 10 pF (unless otherwise noted) (see Figure 1) LIMITS FROM (INPUT) SYMBOL TO (OUTPUT) VCC = 2.5 V ±0.2 V MIN fmax tPLH/tPHL tPHL 2003 Sep 19 Maximum clock frequency UNIT MAX 210 — MHz CLK and CLK Q 1.0 2.6 ns RESET Q 2.0 4.0 ns 7 Philips Semiconductors Product data DDR PC1600-PC3200 14-bit SSTL_2 registered driver with differential clock inputs SSTVF16857 PARAMETER MEASUREMENT INFORMATION AC WAVEFORMS VIH CLK VREF tW VIH VREF INPUT VIL tPLH VREF VREF tPHL VIL VOH VREF OUTPUT SW00339 VREF Waveform 3. Pulse duration VOL SW00836 Waveform 1. Propagation delay times VIH TIMING INPUT VREF VIH VIL RESET VREF tsu th VIL VIH tPHL DATA INPUT VOH OUTPUT VREF VREF VREF VIL VOL SW00837 SW00340 Waveform 2. Propagation delay RESET to output. Waveform 4. Setup and hold times TEST CIRCUIT VTT 50 Ω TEST POINT CL = 30 pF NOTES: CL includes probe and jig capacitance All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 1.25 ns/V, tf 1.25 ns/V. The outputs are measured one at a time with one transition per measurement. VTT = VREF = VDDQ x 0.5 SW00838 Figure 1. Load circuitry 2003 Sep 19 8 Philips Semiconductors Product data DDR PC1600-PC3200 14-bit SSTL_2 registered driver with differential clock inputs TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm 2003 Sep 19 9 SSTVF16857 SOT362-1 Philips Semiconductors Product data DDR PC1600-PC3200 14-bit SSTL_2 registered driver with differential clock inputs TSSOP48: plastic thin shrink small outline package; 48 leads; body width 4.4 mm; lead pitch 0.4 mm 2003 Sep 19 10 SSTVF16857 SOT480-1 Philips Semiconductors Product data DDR PC1600-PC3200 14-bit SSTL_2 registered driver with differential clock inputs VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm 2003 Sep 19 11 SSTVF16857 SOT702-1 Philips Semiconductors Product data DDR PC1600-PC3200 14-bit SSTL_2 registered driver with differential clock inputs REVISION HISTORY Rev Date _1 2003 Sep 19 20030919 Description Product data (9397 750 12077); ECN 853-2405 30362 dated 18 September 2003. 12 SSTVF16857 Philips Semiconductors Product data DDR PC1600-PC3200 14-bit SSTL_2 registered driver with differential clock inputs SSTVF16857 Data sheet status Level Data sheet status[1] Product status[2] [3] Definitions I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Koninklijke Philips Electronics N.V. 2003 All rights reserved. Printed in U.S.A. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Date of release: 09-03 For sales offices addresses send e-mail to: [email protected]. Document order number: Philips Semiconductors 2003 Sep 19 13 9397 750 12077