INTEGRATED CIRCUITS SSTV16859 2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM Product specification ICL03 — PC Motherboard ICs; Logic Products Group 2000 Dec 01 Philips Semiconductors Product specification 2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM SSTV16859 DDR (Double Data Rate) SDRAM and SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR DRAM rated at 133 MHz will have a burst rate of 266 MHz. FEATURES • Stub-series terminated logic for 2.5 V VDD (SSTL_2) • Optimized for stacked DDR (Double Data Rate) SDRAM applications • Supports SSTL_2 signal inputs as per JESD 8–9 • Flow-through architecture optimizes PCB layout • ESD classification testing is done to JEDEC Standard JESD22. The device data inputs consist of different receivers. One differential input is tied to the input pin while the other is tied to a reference input pad, which is shared by all inputs. The clock input is fully differential (CK and CK) to be compatible with DRAM devices that are installed on the DIMM. Data are registered at the crossing of CK going high, and CK going low. However, since the control inputs to the SDRAM change at only half the data rate, the device must only change state on the positive transition of the CK signal. In order to be able to provide defined outputs from the device even before a stable clock has been supplied, the device has an asynchronous input pin (RESET), which when held to the LOW state, resets all registers and all outputs to the LOW state. Protection exceeds 2000 V to HBM per method A114. • Latch-up testing is done to JEDEC Standard JESD78, which exceeds 100 mA. • Supports efficient low power standby operation • Full DDR 200/266 solution for stacked DIMMs at 2.5 V when used with PCKV857 • See SSTV16857 for JEDEC compliant register support in The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low, all registers are reset, and all outputs are forced low. The LVCMOS RESET input must always be held at a valid logic high or low level. unstacked DIMM applications • See SSTV16856 for driver/buffer version with mode select. DESCRIPTION To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power-up. The SSTV16859 is a 13-bit to 26-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V. All inputs are compatible with the JEDEC standard for SSTL_2 with VREF normally at 0.5*VDD, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible which can be used for standard stub-series applications or capacitive loads. Master reset (RESET) asynchronously resets all registers to zero. In the DDR DIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering RESET, the register will be cleared and the outputs will be driven low. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the outputs will remain low. The SSTV16859 is intended to be incorporated into standard DIMM (Dual In-Line Memory Module) designs defined by JEDEC, such as Available in 64-pin plastic thin shrink small outline package. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf v2.5 ns TYPICAL UNIT Propagation delay; CLK to Qn PARAMETER CL = 30 pF; VDD = 2.5 V 2.4 ns Input capacitance VCC = 2.5 V 2.7 pF SYMBOL tPHL/tPLH CI CONDITIONS NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi + Σ (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; Σ (CL × VCC2 × fo) = sum of the outputs. ORDERING INFORMATION PACKAGES 64-Pin Plastic TSSOP Type I 2000 Dec 01 TEMPERATURE RANGE ORDER CODE DWG NUMBER 0 to +70 °C SSTV16859DGG SOT646AA1 2 853–2233 25137 Philips Semiconductors Product specification 2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM PIN CONFIGURATION SSTV16859 PIN DESCRIPTION Q13A 1 64 VDD Q12A 2 63 GND Q11A 3 62 D13 Q10A 4 61 D12 Q9A 5 60 VDD VDD 6 59 VDD GND 7 58 GND Q8A 8 57 D11 Q7A 9 56 D10 Q6A 10 55 D9 Q5A 11 54 GND Q4A 12 53 D8 Q3A 13 52 D7 Q2A 14 51 RESET GND 15 50 GND Q1A 16 49 CK Q13B 17 48 CK VDD 18 47 VDD Q12B 19 46 VDD Q11B 20 45 VREF Q10B 21 44 D6 Q9B 22 43 GND Q8B 23 42 D5 Q7B 24 41 D4 PIN NUMBER SYMBOL NAME AND FUNCTION 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 16 Q13A–Q1A Data output 17, 19, 20, 21, 22, 23, 24, 25, 28, 29, 30, 31, 32 Q13B–Q1B Data output 6, 18, 27, 33, 37, 38, 46, 47, 59, 60, 64 VDD Power supply voltage 7, 15, 26, 34, 39, 43, 50, 54, 58, 63 GND Ground 35, 36, 40, 41, 42, 44, 52, 53, 55, 56, 57, 61, 62 D1–D13 45 VREF 48, 49 CK, CK Positive and negative master clock input 51 RESET Asynchronous reset input: resets registers and disables data and clock differential input receivers Data input: clocked in on the crossing of the rising edge of CK and the falling edge of CK Input reference voltage LOGIC DIAGRAM RESET 51 16 1D CK Q6B 25 40 D3 GND 26 39 GND VDD 27 38 VDD D1 Q5B 28 37 VDD VREF Q4B 29 36 D2 Q3B 30 35 D1 Q2B 31 34 GND Q1B 32 33 VDD CK Q1A 48 C1 49 32 R 35 Q1B 45 to 12 other channels SW00750 FUNCTION TABLE (each flip flop) OUTPUT INPUTS SW00749 RESET CLK CLK D Q H ↑ # L L H ↑ # H H H L or H L or H X Q0 L X or floating X or floating X or floating L H = High voltage level L = Low voltage level ↓ = High-to-Low transition ↑ = Low-to-High transition X = Don’t care 2000 Dec 01 3 Philips Semiconductors Product specification 2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM SSTV16859 ABSOLUTE MAXIMUM RATINGS1 SYMBOL PARAMETER VDD Supply voltage range VI Input voltage range VO IIK LIMITS CONDITION MIN MAX UNIT –0.5 +3.6 V Notes 2 and 3 –0.5 VDD + 0.5 V Output voltage range Notes 2 and 3 –0.5 VDD + 0.5 V Input clamp current VI < 0 or VI > VDD ±50 mA IOK Output clamp current VO < 0 or VO > VDD ±50 mA IO Continuous output current VO = 0 to VDD ±50 mA ±100 mA +150 °C Continuous current through each VDD or GND Tstg Storage temperature range –65 NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 3. This value is limited to 3.6 V maximum. 4. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures that are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. RECOMMENDED OPERATING CONDITIONS1 SYMBOL PARAMETER VDD Supply voltage CONDITIONS VDD MIN TYP MAX UNIT 2.7 VREF Reference voltage (VREF = VDD/2) 1.15 1.25 1.35 V VTT Termination voltage VREF – 40 mV VREF VREF + 40 mV V VI Input voltage 0 VDD V VIH AC HIGH-level input voltage Data inputs VIL AC LOW-level input voltage Data inputs VIH DC HIGH-level input voltage Data inputs VIL DC LOW-level input voltage Data inputs VIH HIGH-level input voltage RESET 1.7 VREF + 310 mV V V VREF – 310 mV VREF + 150 mV V V VREF – 150 mV V VDD V VIL LOW-level input voltage 0.0 0.7 V VICR Common-mode input range CK, CK 0.97 1.53 V CK, CK 360 VID Differential input voltage IOH HIGH-level output current –20 mA IOL LOW-level output current 20 mA Tamb Operating free-air temperature range +70 °C 0 mV NOTE: 1. The RESET input of the device must be held at VDD or GND to ensure proper device operation. The differential inputs must not be floating, unless RESET is low. 2000 Dec 01 4 Philips Semiconductors Product specification 2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM SSTV16859 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = 0 to +70 °C MIN VIK II = –18 mA, VDD = 2.3 V VDD – 0.2 IOH = –16 mA, VDD = 2.3 V VOL O UNIT MAX –1.2 IOH = –100 µA, VDD = 2.3 to 2.7 V VOH O II TYP V V 1.95 IOL = 100 µA, VDD = 2.3 to 2.7 V 0.2 IOL = 16 mA, VDD = 2.3 V 0.35 ±5 V µA All inputs VI = VDD or GND, VDD = 2.7 V Static standby RESET = GND Static operating RESET = VDD, VI = VIH(AC) or VIL(AC) Dynamic operating – clock only RESET = VDD, VI = VIH(AC) or VIL(AC), CK and CK switching 50% duty cycle. Dynamic operating – per each data input RESET = VDD, VI = VIH(AC) or VIL(AC), CK and CK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle. rOH Output high IOH = –20 mA, VDD = 2.3 to 2.7 V 7 20 Ω rOL Output low IOL = 20 mA, VDD = 2.3 to 2.7 V 7 20 Ω rO(∆) |rOH – rOL| each separate bit IO = 20 mA, Tamb = 25°C, VDD = 2.5 V 4 Ω Data inputs VI = VREF ± 310 mV, VDD = 2.5 V 2.5 2.74 3.5 CK and CK VICR = 1.25 V, VI(PP) = 360 mV, VDD = 2.5 V 2.5 3.15 3.5 RESET VI = VDD or GND, VDD = 2.5 V IDD IDDD Ci 2000 Dec 01 0.01 IO = 0, VDD = 2.7 V 45 mA 20 µA/ clock MHz 90 µA/ clock MHz/ data input IO = 0, VDD = 2.7 V 2.27 5 pF Philips Semiconductors Product specification 2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM SSTV16859 TIMING REQUIREMENTS Over recommended operating conditions; Tamb = 0 to +70 °C (unless otherwise noted) (see Figure 1) LIMITS SYMBOL PARAMETER TEST CONDITIONS VDD = 2.5 V ±0.2 V MIN fclock UNIT MAX Clock frequency 200 Pulse duration, CK, CK HIGH or LOW tact Differential inputs active time Notes 1, 2 22 ns Differential inputs inactive time Notes 1, 3 22 ns tinact tsu th tSL Setup time, fast slew rate (see Notes 4 and 6) Setup time, slow slew rate (see Notes 5 and 6) Hold time, fast slew rate (see Notes 4 and 6) Hold time, slow slew rate (see Notes 5 and 6) 2.5 MHz tw ns 0.75 Data before CK↑, CK↑ CK↓ ns 0.9 0.75 CK↑ CK↓ Data after CK↑, ns 0.9 Output slew 1 6 V/ns NOTES: 1. This parameter is not necessarily production tested. 2. Data inputs must be below a minimum time of tact max, after RESET is taken high. 3. Data and clock inputs must be held at valid levels (not floating) a minimum time of tinact max, after RESET is taken low. 4. For data signal input slew rate ≥ 1 V/ns. 5. For data signal input slew rate ≥ 0.5 V/ns and < 1 V/ns. 6. CK, CK signals input slew rates are ≥ 1 V/ns. SWITCHING CHARACTERISTICS Over recommended operating conditions; Tamb = 0 to +70 °C; VDD = 2.3 – 2.7 V. Class I, VREF = VTT = VDD × 0.5 and CL = 10 pF (unless otherwise noted) (see Figure 1) LIMITS FROM O (INPUT) SYMBOL TO O (OUTPUT) VDD = 2.5 V ±0.2 V MIN fmax tpd tPHL 2000 Dec 01 UNIT MAX 200 MHz CK and CK Q 1.1 2.8 ns RESET Q 1.1 5 ns 6 Philips Semiconductors Product specification 2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM SSTV16859 OUTPUT BUFFER CHARACTERISTICS The following table describes output-buffer Voltage vs. Current (V/I) characteristics that are sufficient to meet the requirements of registered DDR DIMM performance and timings. These characteristics are not necessarily production tested but can be guaranteed by design or characterization. Compliance with these curves is not mandatory if it can be adequately demonstrated that alternate characteristics meet the requirements of the registered DDR DIMM application. PULL-DOWN VOLTAGE (V) I (mA) MIN PULL-UP I (mA) MAX I (mA) MIN I (mA) MAX 0.0 0 0 0 0 0.1 7 11 7 10 0.2 14 23 14 20 0.3 21 34 21 30 0.4 28 44 27 40 0.5 33 54 33 49 0.6 39 64 38 59 0.7 44 74 44 68 0.8 48 83 49 76 0.9 52 91 53 84 1.0 56 99 57 93 1.1 59 107 61 100 1.2 61 114 64 108 1.3 63 121 67 115 1.4 64 127 69 121 1.5 66 133 70 128 1.6 66 138 72 134 1.7 67 142 73 139 1.8 67 146 74 144 1.9 67 149 74 148 2.0 67 151 75 152 2.1 68 153 75 156 2.2 68 154 75 159 2.3 68 155 76 161 2.4 156 163 2.5 157 165 2.6 157 167 2.7 157 168 PARAMETER MEASUREMENT INFORMATION TEST CIRCUIT From Output RL = 50 Ω Test Point Under Test CL = 30 pF see Note 1 SW00751 Figure 1. Load circuitry NOTE: 1. CL includes probe and jig capacitance. 2000 Dec 01 7 Philips Semiconductors Product specification 2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM SSTV16859 AC WAVEFORMS LVCMOS RESET LVCMOS RESET VDD VDD/2 VDD/2 tinact VIH Input VDD/2 tact VIL 90% IDD 10% tPHL SW00752 VOH Output Waveform 1. Inputs active and inactive times (see Note 1) VTT VOL tW SW00755 VIH INPUT VREF Waveform 4. Propagation delay times VREF VIL Timing input SW00753 VI(PP) VICR Waveform 2. Pulse duration tsu TIMING INPUT VICR VICR th VI(PP) VIH Input VREF VREF VIL tPHL tPLH SW00756 VOH OUTPUT Waveform 5. Setup and hold times VTT VOL SW00754 Waveform 3. Propagation delay times NOTES: 1. IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA. 2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, input slew rate = 1 V/ns ± 20% (unless otherwise specified). 3. The outputs are measured one at a time with one transition per measurement. 4. VTT = VREF = VDD/2 5. VIH = VREF + 310 mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 6. VIL = VREF – 310 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input. 7. tPLH and tPHL are the same as tpd. 2000 Dec 01 8 Philips Semiconductors Product specification 2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM TSSOP64: plastic thin shrink small outline package; 64 leads; body width 6.1 mm 2000 Dec 01 9 SSTV16859 SOT646-1 Philips Semiconductors Product specification 2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM SSTV16859 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 12-00 Document order number: 2000 Dec 01 10 9397 750 07849