SSTVF16859 13-bit 1 : 2 SSTL_2 registered buffer for DDR Rev. 02 — 19 July 2005 Product data sheet 1. General description The SSTVF16859 is a 13-bit to 26-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V for PC1600-PC2700 applications or between 2.5 V and 2.7 V for PC3200 applications. All inputs are compatible with the JEDEC standard for SSTL_2 with Vref normally at 0.5 × VDD, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible, which can be used for standard stub-series applications or capacitive loads. Master reset (RESET) asynchronously resets all registers to zero. The SSTVF16859 is intended to be incorporated into standard DIMM (Dual In-Line Memory Module) designs defined by JEDEC, such as DDR (Double Data Rate) SDRAM and SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR DRAM rated at 133 MHz will have a burst rate of 266 MHz. The device data inputs consist of different receivers. One differential input is tied to the input pin while the other is tied to a reference input pad, which is shared by all inputs. The clock input is fully differential (CK and CK) to be compatible with DRAM devices that are installed on the DIMM. Data are registered at the crossing of CK going HIGH, and CK going LOW. However, since the control inputs to the SDRAM change at only half the data rate, the device must only change state on the positive transition of the CK signal. In order to be able to provide defined outputs from the device even before a stable clock has been supplied, the device has an asynchronous input pin (RESET), which when held to the LOW state, resets all registers and all outputs to the LOW state. The device supports low-power standby operation. When RESET is LOW, the differential input receivers are disabled, and un-driven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW, all registers are reset, and all outputs are forced LOW. The LVCMOS RESET input must always be held at a valid logic HIGH or LOW level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the LOW state during power-up. In the DDR DIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering RESET, the register will be cleared and the outputs will be driven LOW. As long as the data inputs are LOW, and the clock is stable during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the outputs will remain LOW. SSTVF16859 Philips Semiconductors 13-bit 1 : 2 SSTL_2 registered buffer for DDR 2. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Stub-series terminated logic for 2.5 V VDD (SSTL_2) Designed for PC1600-PC2700 (at 2.5 V) and PC3200 (at 2.6 V) applications Pin and function compatible with JEDEC standard SSTV16859 Supports SSTL_2 signal inputs as per JESD 8-9 Flow-through architecture optimizes printed-circuit board layout ESD classification testing is done to JEDEC Standard JESD22. Protection exceeds 2000 V to HBM per method A114. Latch-up testing is done to JEDEC Standard JESD78, which exceeds 100 mA Supports efficient low power standby operation Full DDR solution when used with PCKVF857 Available in TSSOP64, LFBGA96 and HVQFN56 packages 3. Quick reference data Table 1: Quick reference data GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns Symbol Parameter Conditions Min Typ Max Unit tPHL/tPLH propagation delay, CK/CK to Qn CL = 30 pF; VDD = 2.5 V - 1.7 - ns Ci input capacitance VDD = 2.5 V - 2.8 - pF [1] [1] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VDD2 × fi + Σ (CL × VDD2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VDD = supply voltage in V; Σ (CL × VDD2 × fo) = sum of the outputs. 4. Ordering information Table 2: Ordering information Tamb = 0 °C to +70 °C Type number Package Name SSTVF16859BS Description HVQFN56 plastic thermal enhanced very thin quad flat package; SOT684-1 no leads; 56 terminals; body 8 × 8 × 0.85 mm SSTVF16859DGG TSSOP64 plastic thin shrink small outline package; 64 leads; body width 6.1 mm SOT646-1 SSTVF16859EC SOT536-1 LFBGA96 plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 × 5.5 × 1.05 mm 9397 750 15157 Product data sheet Version © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 19 July 2005 2 of 23 SSTVF16859 Philips Semiconductors 13-bit 1 : 2 SSTL_2 registered buffer for DDR 5. Functional diagram SSTVF16859 RESET CK CK 1D C1 Q1A R Q1B D1 VREF 002aab621 to 12 other channels Fig 1. Logic diagram of SSTVF16859 6. Pinning information 43 D11 44 VDDQ 45 VDD 46 D12 47 D13 48 GND 49 VDDQ 50 Q13A 51 Q12A 52 Q11A 53 Q10A 54 Q9A terminal 1 index area 55 VDDQ 56 Q8A 6.1 Pinning Q7A 1 42 D10 Q6A 2 41 D9 Q5A 3 40 D8 Q4A 4 39 D7 Q3A 5 38 RESET Q2A 6 37 GND Q1A 7 Q13B 8 VDDQ 9 36 CK SSTVF16859BS 35 CK 34 VDDQ D3 28 VDDQ 27 VDD 26 D2 25 D1 24 VDDQ 23 Q1B 22 Q2B 21 Q3B 20 29 D4 Q4B 19 30 D5 Q8B 14 Q5B 18 31 D6 Q9B 13 VDDQ 17 32 VREF Q10B 12 Q6B 16 33 VDD Q11B 11 Q7B 15 Q12B 10 002aab618 Transparent top view Fig 2. Pin configuration for HVQFN56 9397 750 15157 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 19 July 2005 3 of 23 SSTVF16859 Philips Semiconductors 13-bit 1 : 2 SSTL_2 registered buffer for DDR Q13A 1 64 VDD Q12A 2 63 GND Q11A 3 62 D14 Q10A 4 61 D12 Q9A 5 60 VDD VDD 6 59 VDD GND 7 58 GND Q8A 8 57 D11 Q7A 9 56 D10 Q6A 10 55 D9 Q5A 11 54 GND Q4A 12 53 D8 Q3A 13 52 D7 Q2A 14 51 RESET GND 15 50 GND Q1A 16 Q13B 17 49 CK SSTVF16859DGG 48 CK VDD 18 47 VDD Q12B 19 46 VDD Q11B 20 45 VREF Q10B 21 44 D6 Q9B 22 43 GND Q8B 23 42 D5 Q7B 24 41 D4 Q6B 25 40 D3 GND 26 39 GND VDD 27 38 VDD Q5B 28 37 VDD Q4B 29 36 D2 Q3B 30 35 D1 Q2B 31 34 GND Q1B 32 33 VDD 002aab617 Fig 3. Pin configuration for TSSOP64 9397 750 15157 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 19 July 2005 4 of 23 SSTVF16859 Philips Semiconductors 13-bit 1 : 2 SSTL_2 registered buffer for DDR ball A1 SSTVF16859EC index area 1 2 3 4 5 6 A B C D E F G H J K L M N P R T 002aab619 Transparent top view Fig 4. Pin configuration for LFBGA96 1 2 3 4 5 6 A n.c. n.c. n.c. n.c. n.c. n.c. B Q12A Q13A GND GND n.c. n.c. C Q10A Q11A GND GND n.c. n.c. D Q8A Q9A VDDQ VDDQ D13 D12 E Q6A Q7A VDDQ VDDQ D11 D10 F Q4A Q5A VDDQ VDDQ D9 D8 G Q2A Q3A GND GND D7 RESET H Q1A Q13B GND GND n.c. CK J Q12B Q11B GND VREF n.c. CK K Q10B Q9B VDDQ VDDQ n.c. n.c. L Q8B Q7B VDDQ VDDQ D5 D6 M Q6B Q5B VDDQ VDDQ D3 D4 N Q4B Q3B GND GND D1 D2 P Q2B Q1B GND GND n.c. n.c. R n.c. n.c. n.c. n.c. n.c. n.c. T n.c. n.c. n.c. n.c. n.c. n.c. 002aab620 All VDD and VDDQ are tied internally. Fig 5. Ball mapping for LFBGA96 9397 750 15157 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 19 July 2005 5 of 23 SSTVF16859 Philips Semiconductors 13-bit 1 : 2 SSTL_2 registered buffer for DDR 6.2 Pin description Table 3: Symbol Pin description Pin Description TSSOP64 HVQFN56 LFBGA96 Q1A 16 7 H1 Q2A 14 6 G1 Q3A 13 5 G2 Q4A 12 4 F1 Q5A 11 3 F2 Q6A 10 2 E1 Q7A 9 1 E2 Q8A 8 56 D1 Q9A 5 54 D2 Q10A 4 53 C1 Q11A 3 52 C2 Q12A 2 51 B1 Q13A 1 50 B2 Q1B 32 22 P2 Q2B 31 21 P1 Q3B 30 20 N2 Q4B 29 19 N1 Q5B 28 18 M2 Q6B 25 16 M1 Q7B 24 15 L2 Q8B 23 14 L1 Q9B 22 13 K2 Q10B 21 12 K1 Q11B 20 11 J2 Q12B 19 10 J1 data output data output Q13B 17 8 H2 VDD 37, 46, 60 26, 33, 45 - power supply voltage VDDQ 6, 18, 27, 33, 38, 47, 59, 64 9, 17, 23, 27, 34, 44, 49, 55 D3, D4, E3, E4, F3, F4, K3, K4, L3, L4, M3, M4, output supply voltage GND 7, 15, 26, 34, 39, 37, 48 43, 50, 54, 58, 63 B3, B4, C3, C4, G3, G4, H3, H4, J3, N3, N4, P3, P4 ground 9397 750 15157 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 19 July 2005 6 of 23 SSTVF16859 Philips Semiconductors 13-bit 1 : 2 SSTL_2 registered buffer for DDR Table 3: Symbol Pin description …continued Pin Description TSSOP64 HVQFN56 LFBGA96 D1 35 24 N5 D2 36 25 N6 D3 40 28 M5 D4 41 29 M6 D5 42 30 L5 D6 44 31 L6 D7 52 39 G5 D8 53 40 F6 D9 55 41 F5 D10 56 42 E6 D11 57 43 E5 D12 61 46 D6 D13 62 47 D5 VREF 45 32 J4 input reference voltage CK 48 35 J6 positive master clock input CK 49 36 H6 negative master clock input RESET 51 38 G6 Asynchronous reset input. Resets registers and disables data and clock differential input receivers. n.c. - - A1, A2, A3, A4, A5, A6, B5, B6, C5, C6, H5, J5, K5, K6, P5, P6, R1, R2, R3, R4, R5, R6, T1, T2, T3, T4, T5, T6 not connected Data input. Clocked in on the crossing of the rising edge of CK and the falling edge of CK. 7. Functional description Refer to Figure 1 “Logic diagram of SSTVF16859”. 7.1 Function table Table 4: Function selection (each flip-flop) H = HIGH voltage level; L = LOW voltage level; ↓ = HIGH-to-LOW transition; ↑ = LOW-to-HIGH transition; X = Don’t care Inputs Output RESET CK CK Dn Qn H ↑ L L H ↑ ↓ ↓ H H H L or H L or H X Q0 [1] L X or floating X or floating X or floating L [1] Q0 is the previous state of output Qn. 9397 750 15157 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 19 July 2005 7 of 23 SSTVF16859 Philips Semiconductors 13-bit 1 : 2 SSTL_2 registered buffer for DDR 8. Limiting values Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD Conditions Min Max Unit supply voltage −0.5 +3.6 VDD + 0.5 [2] V V VI input voltage −0.5 [1] VO output voltage −0.5 [1] VDD + 0.5 [2] V IIK input clamp current VI < 0 V or VI > VDD - ±50 mA IOK output clamp current VO < 0 V or VO > VDD - ±50 mA IO continuous output current VO = 0 V to VDD - ±50 mA ICCC continuous current through each VDD or GND - ±100 mA Tstg storage temperature −65 +150 °C [3] [1] The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. [2] This value is limited to 3.6 V maximum. [3] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures that are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C. 9. Recommended operating conditions Table 6: Recommended operating conditions [1] Symbol Parameter VDD supply voltage Vref reference voltage (Vref = VDD/2) VTT termination voltage VI input voltage VIH(AC) AC HIGH-level input voltage VIL(AC) VIH(DC) Conditions Min Typ Max Unit VDD - 2.7 V 1.15 1.25 1.35 V 1.25 1.3 1.35 V Vref − 0.040 Vref Vref + 0.040 V 0 - VDD V data inputs Vref + 0.310 - - V AC LOW-level input voltage data inputs - - Vref − 0.310 V DC HIGH-level input voltage data inputs Vref + 0.150 - - V VIL(DC) DC LOW-level input voltage data inputs - - Vref − 0.150 V VIH HIGH-level input voltage RESET 1.7 - VDD V PC1600-PC2700 PC3200 VIL LOW-level input voltage 0 - 0.7 V VICR common-mode input voltage range CK, CK 0.97 - 1.53 V VID differential input voltage CK, CK 360 - - mV IOH HIGH-level output current - - −16 mA IOL LOW-level output current - - 16 mA Tamb ambient temperature 0 - +70 °C [1] operating in free air The RESET input of the device must be held at VDD or GND to ensure proper device operation. The differential inputs must not be floating, unless RESET is LOW. 9397 750 15157 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 19 July 2005 8 of 23 SSTVF16859 Philips Semiconductors 13-bit 1 : 2 SSTL_2 registered buffer for DDR 10. Static characteristics Table 7: Static characteristics (PC1600-PC2700) Tamb = 0 °C to +70 °C; over recommended operating conditions; voltages are referenced to GND (ground = 0 V); unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VIK input clamping voltage II = −18 mA; VDD = 2.3 V - - −1.2 V VOH HIGH-level output voltage IOH = −100 µA; VDD = 2.3 V to 2.7 V VDD − 0.2 - - V IOH = −16 mA; VDD = 2.3 V 1.95 - - V IOL = 100 µA; VDD = 2.3 V to 2.7 V - - 0.2 V VOL LOW-level output voltage IOL = 16 mA; VDD = 2.3 V - - 0.35 V II input current (all inputs) VI = VDD or GND; VDD = 2.7 V - - ±5 µA IDD supply current IO = 0 mA; VDD = 2.7 V static standby; RESET = GND - - 0.01 mA static operating; RESET = VDD; VI = VIH(AC) or VIL(AC) - - 45 mA dynamic operating current IO = 0 mA; VDD = 2.7 V; RESET = VDD; per MHz, clock only VI = VIH(AC) or VIL(AC); CK and CK switching 50 % duty cycle - 15 - µA dynamic operating current IO = 0 mA; VDD = 2.7 V; RESET = VDD; VI = VIH(AC) or VIL(AC); CK and CK per MHz, per each data input switching 50 % duty cycle; one data input switching at half clock frequency, 50 % duty cycle - 9 - µA data inputs; VI = Vref ± 310 mV; VDD = 2.5 V 2.5 2.8 3.5 pF CK and CK; VICR = 1.25 V; VI(p-p) = 360 mV; VDD = 2.5 V 2.5 3.2 3.5 pF RESET; VI = VDD or GND; VDD = 2.5 V - 2.4 3.5 pF IDDD Ci input capacitance 9397 750 15157 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 19 July 2005 9 of 23 SSTVF16859 Philips Semiconductors 13-bit 1 : 2 SSTL_2 registered buffer for DDR Table 8: Static characteristics (PC3200) At recommended operating conditions; Tamb = 0 °C to +70 °C; voltages are referenced to GND (ground = 0 V); unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VIK input clamping voltage II = −18 mA; VDD = 2.5 V - - −1.2 V VOH HIGH-level output voltage IOH = −100 µA; VDD = 2.5 V to 2.7 V VDD − 0.2 - - V IOH = −16 mA; VDD = 2.5 V 1.95 - - V IOL = 100 µA; VDD = 2.5 V to 2.7 V - - 0.2 V IOL = 16 mA; VDD = 2.5 V - - 0.35 V - - ±5 µA static standby; RESET = GND - - 0.01 mA static operating; RESET = VDD; VI = VIH(AC) or VIL(AC) - - 45 mA dynamic operating current IO = 0 mA; VDD = 2.7 V; RESET = VDD; per MHz, clock only VI = VIH(AC) or VIL(AC); CK and CK switching 50 % duty cycle - 15 - µA dynamic operating current IO = 0 mA; VDD = 2.7 V; RESET = VDD; VI = VIH(AC) or VIL(AC); CK and CK per MHz, per each data input switching 50 % duty cycle; one data input switching at half clock frequency, 50 % duty cycle - 9 - µA VOL LOW-level output voltage II input current (all inputs) VI = VDD or GND; VDD = 2.7 V IDD supply current IO = 0 mA; VDD = 2.7 V IDDD Ci input capacitance, data inputs VI = Vref ± 310 mV; VDD = 2.6 V 2.5 2.8 3.5 pF input capacitance, CK and CK VICR = 1.25 V; VI(p-p) = 360 mV; VDD = 2.6 V 2.5 3.2 3.5 pF input capacitance, RESET VI = VDD or GND; VDD = 2.6 V - 2.4 3.5 pF 9397 750 15157 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 19 July 2005 10 of 23 SSTVF16859 Philips Semiconductors 13-bit 1 : 2 SSTL_2 registered buffer for DDR 11. Dynamic characteristics Table 9: Timing requirements (PC1600-PC2700) At recommended operating conditions; VDD = 2.5 V ± 0.2 V; Tamb = 0 °C to +70 °C; unless otherwise specified. See Figure 11. Symbol Parameter Conditions Min Typ Max Unit fclock clock frequency - - 200 MHz tW pulse duration, CK, CK, HIGH or LOW 2.5 - - ns tACT differential inputs active time [1] [2] - - 22 ns tINACT differential inputs inactive time [1] [3] - - 22 ns tsu setup time, fast slew rate data before CK↑, CK↓ [4] [6] 0.65 - - ns data before CK↑, CK↓ [5] [6] 0.75 - - ns data after CK↑, CK↓ [4] [6] 0.75 - - ns data after CK↑, CK↓ [5] [6] 0.9 - - ns setup time, slow slew rate hold time, fast slew rate th hold time, slow slew rate [1] This parameter is not necessarily production tested. [2] Data inputs must be below a minimum time to tACT(max), after RESET is taken HIGH. [3] Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT(max), after RESET is taken LOW. [4] For data signal input slew rate ≥ 1 V/ns. [5] For data signal input slew rate ≥ 0.5 V/ns and < 1 V/ns. [6] CK, CK signals input slew rates are ≥ 1 V/ns. Table 10: Timing requirements (PC3200) At recommended operating conditions; VDD = 2.6 V ± 0.1 V; Tamb = 0 °C to +70 °C; unless otherwise specified. See Figure 11. Symbol Parameter Min Typ Max Unit fclock clock frequency - - 210 MHz tW pulse duration, CK, CK, HIGH or LOW 2.5 - - ns tACT differential inputs active time [1] [2] - - 22 ns tINACT differential inputs inactive time [1] [3] - - 22 ns setup time, fast slew rate data before CK↑, CK↓ [4] [6] 0.65 - - ns data before CK↑, CK↓ [5] [6] 0.75 - - ns hold time, fast slew rate data after CK↑, CK↓ [4] [6] 0.65 - - ns hold time, slow slew rate data after CK↑, CK↓ [5] [6] 0.8 - - ns tsu Conditions setup time, slow slew rate th [1] This parameter is not necessarily production tested. [2] Data inputs must be below a minimum time to tACT(max), after RESET is taken HIGH. [3] Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT(max), after RESET is taken LOW. [4] For data signal input slew rate ≥ 1 V/ns. [5] For data signal input slew rate ≥ 0.5 V/ns and < 1 V/ns. [6] CK, CK signals input slew rates are ≥ 1 V/ns. 9397 750 15157 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 19 July 2005 11 of 23 SSTVF16859 Philips Semiconductors 13-bit 1 : 2 SSTL_2 registered buffer for DDR Table 11: Switching characteristics (PC1600-PC2700) At recommended operating conditions; VDD = 2.5 V ± 0.2 V; Tamb = 0 °C to +70 °C; Class I; Vref = VTT = VDD × 0.5 and CL = 10 pF; unless otherwise specified. See Figure 11. Symbol Parameter fMAX maximum input clock frequency Conditions Min Typ Max Unit 200 - - MHz tPD propagation delay from CK, CK to Qn 1.1 - 2.5 ns tPDMSS propagation delay, simultaneous switching from CK, CK to Qn - - 2.9 ns tPHL HIGH-to-LOW transition time from RESET to Qn 1.1 - 5 ns Table 12: Switching characteristics (PC3200) At recommended operating conditions; VDD = 2.6 V ± 0.1 V; Tamb = 0 °C to +70 °C; Class I; Vref = VTT = VDD × 0.5 and CL = 10 pF; unless otherwise specified. See Figure 11. Symbol Parameter fMAX maximum input clock frequency Conditions Min Typ Max Unit 210 - - MHz tPD propagation delay from CK, CK to Qn 1.1 - 2.2 ns tPDMSS propagation delay, simultaneous switching from CK, CK to Qn - - 2.48 ns tPHL HIGH-to-LOW transition time from RESET to Qn 1.1 - 5 ns 11.1 AC waveforms All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω; input slew rate = 1 V/ns ± 20 %; unless otherwise specified. The outputs are measured one at a time with one transition per measurement. LVCMOS VDD RESET VDD/2 VDD/2 0V tINACT tACT 90 % IDD(1) 10 % 002aaa372 (1) IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA. Fig 6. Inputs active and inactive times tW VIH input Vref Vref VID VIL 002aab623 VIH = Vref + 310 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. VIL = Vref − 310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. Fig 7. Pulse duration 9397 750 15157 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 19 July 2005 12 of 23 SSTVF16859 Philips Semiconductors 13-bit 1 : 2 SSTL_2 registered buffer for DDR CK VICR VICR tPLH tPHL Vi(p-p) CK VOH VTT output 002aab624 VOL VTT = Vref = VDD/2 tPLH and tPHL are the same as tPD. Fig 8. Propagation delay times (clock to output) LVCMOS VIH VDD/2 RESET VIL tPHL VOH VTT output 002aaa376 VOL VTT = Vref = VDD/2 tPLH and tPHL are the same as tPD. VIH = Vref + 310 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. VIL = Vref − 310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. Fig 9. Propagation delay times (reset to output) CK VICR Vi(p-p) CK tsu th VIH input Vref Vref VIL 002aab625 Vref = VDD/2 VIH = Vref + 310 mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. VIL = Vref − 310 mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. Fig 10. Setup and hold times 9397 750 15157 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 19 July 2005 13 of 23 SSTVF16859 Philips Semiconductors 13-bit 1 : 2 SSTL_2 registered buffer for DDR 12. Test information RL = 50 Ω m output under test test point CL = 30 pF(1) 002aab622 (1) CL includes probe and jig capacitance. Fig 11. Load circuit 9397 750 15157 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 19 July 2005 14 of 23 SSTVF16859 Philips Semiconductors 13-bit 1 : 2 SSTL_2 registered buffer for DDR 13. Package outline TSSOP64: plastic thin shrink small outline package; 64 leads; body width 6.1 mm SOT646-1 E D A X c HE y v M A Z 64 33 A2 (A 3) A1 pin 1 index A θ Lp L 1 32 bp e detail X w M 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.27 0.17 0.2 0.1 17.1 16.9 6.2 6.0 0.5 8.3 7.9 1 0.75 0.45 0.2 0.08 0.1 0.89 0.61 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT646-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 00-08-21 03-02-18 MO-153 Fig 12. Package outline SOT646-1 (TSSOP64) 9397 750 15157 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 19 July 2005 15 of 23 SSTVF16859 Philips Semiconductors 13-bit 1 : 2 SSTL_2 registered buffer for DDR LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1 A B D ball A1 index area A A2 E A1 detail X e1 C 1/2 e ∅v M C A B e T R P N M L K J H G F E D C B A ball A1 index area y1 C y ∅w M C b e e2 1/2 e 1 2 3 4 5 6 X 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 b D E e e1 e2 v w y y1 mm 1.5 0.41 0.31 1.2 0.9 0.51 0.41 5.6 5.4 13.6 13.4 0.8 4 12 0.15 0.1 0.1 0.2 OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 00-03-04 03-02-05 SOT536-1 Fig 13. Package outline SOT536-1 (LFBGA96) 9397 750 15157 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 19 July 2005 16 of 23 SSTVF16859 Philips Semiconductors 13-bit 1 : 2 SSTL_2 registered buffer for DDR HVQFN56: plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 x 8 x 0.85 mm A B D SOT684-1 terminal 1 index area A E A1 c detail X C e1 1/2 e e b 15 L y y1 C v M C A B w M C 28 29 14 e e2 Eh 1/2 e 1 42 terminal 1 index area 56 43 X Dh 0 2.5 scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 5 mm c D(1) Dh E(1) Eh 0.2 8.1 7.9 4.45 4.15 8.1 7.9 4.45 4.15 e e1 6.5 0.5 e2 L v w y y1 6.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT684-1 --- MO-220 --- EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-22 Fig 14. Package outline SOT684-1 (HVQFN56) 9397 750 15157 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 19 July 2005 17 of 23 SSTVF16859 Philips Semiconductors 13-bit 1 : 2 SSTL_2 registered buffer for DDR 14. Soldering 14.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 14.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 °C to 270 °C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: • below 225 °C (SnPb process) or below 245 °C (Pb-free process) – for all BGA, HTSSON..T and SSOP..T packages – for packages with a thickness ≥ 2.5 mm – for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called thick/large packages. • below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 14.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; 9397 750 15157 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 19 July 2005 18 of 23 SSTVF16859 Philips Semiconductors 13-bit 1 : 2 SSTL_2 registered buffer for DDR – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 °C and 320 °C. 14.5 Package related soldering information Table 13: Suitability of surface mount IC packages for wave and reflow soldering methods Package [1] Soldering method Wave Reflow [2] BGA, HTSSON..T [3], LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON not suitable suitable DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable [4] suitable PLCC [5], SO, SOJ suitable suitable not recommended [5] [6] suitable SSOP, TSSOP, VSO, VSSOP not recommended [7] suitable CWQCCN..L [8], PMFP [9], WQCCN..L [8] not suitable LQFP, QFP, TQFP [1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. [2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. [3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 9397 750 15157 Product data sheet not suitable © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 19 July 2005 19 of 23 SSTVF16859 Philips Semiconductors 13-bit 1 : 2 SSTL_2 registered buffer for DDR [4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. [6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. [9] Hot bar soldering or manual soldering is suitable for PMFP packages. 15. Abbreviations Table 14: Abbreviations Acronym Description DDR Double Data Rate DIMM Dual In-line Memory Module ESD Electro Static Discharge HBM Human Body Model PRR Pulse Rate Repetition SSTL Stub Series Terminated Logic 9397 750 15157 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 19 July 2005 20 of 23 SSTVF16859 Philips Semiconductors 13-bit 1 : 2 SSTL_2 registered buffer for DDR 16. Revision history Table 15: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes SSTVF16859_2 20050719 Product data sheet - 9397 750 15157 SSTVF16859_1 Modifications: • The format of this data sheet has been redesigned to comply with the new presentation and information standard of Philips Semiconductors. • Table 1 “Quick reference data”: – parameter for tPHL/tPLH changed from ‘propagation delay; CLK to Qn’ to ‘propagation delay; CK/CK to Qn’ – Condition column for input capacitance changed from ‘VCC = 2.5 V’ to ‘VDD = 2.5 V’ • Section 6 “Pinning information”: – Figure 3 “Pin configuration for TSSOP64”: pins 6, 18, 27, 33, 38 47, 59 and 64 changed from ‘VDD’ to ‘VDDQ’ – pin description tables consolidated with columns for package-type • • Symbol ‘VREF’ changed to ‘VREF’ for pin name, and to ‘Vref’ for reference voltage Figure 2 “Pin configuration for HVQFN56” on page 3: – terminals 26, 33, 45 symbols changed from ‘VDDI’ to ‘VDD’ – terminal 56 symbol changed from ‘Q8B’ to ‘Q8A’ • Table 4 “Function selection (each flip-flop)” on page 7: moved definitions above table; added Table note 1. • Table 5 “Limiting values” on page 8: – deleted (old) Table note 1; this information is now placed in Section 18 “Definitions” on page 22. – Added symbol ‘ICCC’ to parameter ‘continuous current through each VDD or GND’ • • Section 9 “Recommended operating conditions” on page 8: under Min and Max columns, values previously expressed with unit ‘mV’ re-written as equivalent ‘V’ value. Table 7 “Static characteristics (PC1600-PC2700)” on page 9: – IDD(max) for ‘static operating’ condition changed from ‘25 mA’ to ‘45 mA’ – IDDD(typ) for ‘clock only’ changed from ‘20 µA’ to ‘15 µA’ – parameter for IDDD modified: added ‘per MHz’ to parameter, changed Unit to ‘µA’ SSTVF16859_1 • Table 8 “Static characteristics (PC3200)” on page 10: parameter for IDDD modified: added ‘per MHz’ to parameter, changed Unit to ‘µA’ • Added Section 14 “Soldering”, Section 15 “Abbreviations”, and Section 20 “Trademarks”. 20040712 Product data sheet - 9397 750 15157 Product data sheet 9397 750 13077 - © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 19 July 2005 21 of 23 SSTVF16859 Philips Semiconductors 13-bit 1 : 2 SSTL_2 registered buffer for DDR 17. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 18. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 20. Trademarks 19. Disclaimers Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 21. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: [email protected] 9397 750 15157 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 02 — 19 July 2005 22 of 23 SSTVF16859 Philips Semiconductors 13-bit 1 : 2 SSTL_2 registered buffer for DDR 22. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 11.1 12 13 14 14.1 14.2 14.3 14.4 14.5 15 16 17 18 19 20 21 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 7 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions. . . . . . . . 8 Static characteristics. . . . . . . . . . . . . . . . . . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . 11 AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 12 Test information . . . . . . . . . . . . . . . . . . . . . . . . 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 18 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 18 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 19 Package related soldering information . . . . . . 19 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 21 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 22 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Contact information . . . . . . . . . . . . . . . . . . . . 22 © Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 19 July 2005 Document number: 9397 750 15157 Published in The Netherlands