PSMN4R0-40YS N-channel LFPAK 40 V 4.2 mΩ standard level MOSFET Rev. 01 — 25 June 2009 Product data sheet 1. Product profile 1.1 General description Standard level N-channel MOSFET in LFPAK package qualified to 175 °C. This product is designed and qualified for use in a wide range of industrial, communications and domestic equipment. 1.2 Features and benefits Advanced TrenchMOS provides low RDSon and low gate charge Improved mechanical and thermal characteristics High efficiency gains in switching power converters LFPAK provides maximum power density in a Power SO8 package 1.3 Applications DC-to-DC convertors Motor control Lithium-ion battery protection Server power supplies Load switching 1.4 Quick reference data Table 1. Quick reference Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 40 V ID drain current Tmb = 25 °C; VGS = 10 V; see Figure 1 - - 100 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - - 106 W Tj junction temperature -55 - 175 °C VGS = 10 V; Tj(init) = 25 °C; ID = 100 A; Vsup ≤ 40 V; unclamped; RGS = 50 Ω - - 77 mJ VGS = 10 V; ID = 25 A; VDS = 20 V; see Figure 14; see Figure 15 - 7 - nC - 38 - nC Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy Dynamic characteristics QGD gate-drain charge QG(tot) total gate charge PSMN4R0-40YS NXP Semiconductors N-channel LFPAK 40 V 4.2 mΩ standard level MOSFET Table 1. Quick reference …continued Symbol Parameter Conditions Min Typ Max Unit VGS = 10 V; ID = 15 A; Tj = 100 °C; see Figure 12 - - 5.6 mΩ VGS = 10 V; ID = 15 A; Tj = 25 °C; see Figure 12; see Figure 13 - 3.2 4.2 mΩ Static characteristics RDSon drain-source on-state resistance 2. Pinning information Table 2. Pinning information Pin Symbol Description 1 S source 3 S source 3 S source 4 G gate mb D drain Simplified outline Graphic symbol D mb G mbb076 S 1 2 3 4 SOT669 (LFPAK) 3. Ordering information Table 3. Ordering information Type number PSMN4R0-40YS Package Name Description Version LFPAK plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669 PSMN4R0-40YS_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 25 June 2009 2 of 13 PSMN4R0-40YS NXP Semiconductors N-channel LFPAK 40 V 4.2 mΩ standard level MOSFET 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 40 V VDGR drain-gate voltage Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ VGS gate-source voltage ID drain current - 40 V -20 20 V VGS = 10 V; Tmb = 100 °C; see Figure 1 - 83 A VGS = 10 V; Tmb = 25 °C; see Figure 1 - 100 A IDM peak drain current tp ≤ 10 µs; pulsed; Tmb = 25 °C; see Figure 3 - 472 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - 106 W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Tsld(M) peak soldering temperature - 260 °C Source-drain diode IS source current Tmb = 25 °C - 100 A ISM peak source current tp ≤ 10 µs; pulsed; Tmb = 25 °C - 472 A - 77 mJ Avalanche ruggedness non-repetitive VGS = 10 V; Tj(init) = 25 °C; ID = 100 A; Vsup ≤ 40 V; drain-source avalanche unclamped; RGS = 50 Ω energy EDS(AL)S 003aad266 120 ID (A) 100 03aa16 120 Pder (%) (1) 80 80 60 40 40 20 0 0 0 Fig 1. 50 100 150 Tmb (°C) 200 0 100 150 200 Tmb (°C) Continuous drain current as a function of mounting base temperature Fig 2. Normalized total power dissipation as a function of mounting base temperature PSMN4R0-40YS_1 Product data sheet 50 © NXP B.V. 2009. All rights reserved. Rev. 01 — 25 June 2009 3 of 13 PSMN4R0-40YS NXP Semiconductors N-channel LFPAK 40 V 4.2 mΩ standard level MOSFET 003aad321 103 ID (A) 10μ s Limit RDSon = VDS / ID 102 (1) 100μ s 10 1ms DC 10ms 100ms 1 10-1 10-1 Fig 3. 1 10 102 VDS (V) Safe operating area; continuous and peak drain currents as a function of drain-source voltage 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Rth(j-mb) thermal resistance from see Figure 4 junction to mounting base Min Typ Max Unit - 0.54 1.42 K/W 003aac657 10 Zth(j-mb) (K/W) 1 δ = 0.5 0.2 0.1 10-1 0.05 0.02 10-2 δ= P tp T single shot t tp 10 T -3 10-6 Fig 4. 10-5 10-4 10-3 10-2 10-1 tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration PSMN4R0-40YS_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 25 June 2009 4 of 13 PSMN4R0-40YS NXP Semiconductors N-channel LFPAK 40 V 4.2 mΩ standard level MOSFET 6. Characteristics Table 6. Symbol Characteristics Parameter Conditions Min Typ Max Unit drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = -55 °C 36 - - V ID = 250 µA; VGS = 0 V; Tj = 25 °C 40 - - V gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = -55 °C; see Figure 10; see Figure 11 - - 4.6 V ID = 1 mA; VDS = VGS; Tj = 175 °C; see Figure 10; see Figure 11 1 - - V ID = 1 mA; VDS = VGS; Tj = 25 °C; see Figure 10; see Figure 11 2 3 4 V Static characteristics V(BR)DSS VGS(th) IDSS IGSS RDSon RG drain leakage current gate leakage current drain-source on-state resistance VDS = 40 V; VGS = 0 V; Tj = 25 °C - - 3 µA VDS = 40 V; VGS = 0 V; Tj = 125 °C - - 40 µA VGS = 20 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = -20 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = 10 V; ID = 15 A; Tj = 100 °C; see Figure 12 - - 5.6 mΩ VGS = 10 V; ID = 15 A; Tj = 175 °C; see Figure 12 - - 8 mΩ VGS = 10 V; ID = 15 A; Tj = 25 °C; see Figure 12; see Figure 13 - 3.2 4.2 mΩ - 0.62 - Ω ID = 0 A; VDS = 0 V; VGS = 10 V - 31 - nC ID = 25 A; VDS = 20 V; VGS = 10 V; see Figure 14; see Figure 15 - 38 - nC internal gate resistance f = 1 MHz (AC) Dynamic characteristics QG(tot) total gate charge QGS gate-source charge QGS(th) pre-threshold gate-source charge QGS(th-pl) ID = 25 A; VDS = 20 V; VGS = 10 V; see Figure 14; see Figure 15 - 12 - nC - 7 - nC post-threshold gate-source charge - 5 - nC QGD gate-drain charge - 7 - nC VGS(pl) gate-source plateau voltage ID = 25 A; VDS = 20 V; see Figure 14 - 4.8 - V Ciss input capacitance 2410 - pF output capacitance VDS = 20 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 16 - Coss - 504 - pF Crss reverse transfer capacitance - 266 - pF td(on) turn-on delay time - 18 - ns tr rise time - 19 - ns td(off) turn-off delay time - 34 - ns tf fall time - 12 - ns VDS = 20 V; RL = 0.8 Ω; VGS = 10 V; RG(ext) = 4.7 Ω PSMN4R0-40YS_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 25 June 2009 5 of 13 PSMN4R0-40YS NXP Semiconductors N-channel LFPAK 40 V 4.2 mΩ standard level MOSFET Table 6. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; see Figure 17 - 0.83 1.2 V trr reverse recovery time - 42 - ns Qr recovered charge IS = 50 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 20 V - 45 - nC [1] Tested to JEDEC standards where applicable. 003aad154 120 ID 20 10 6.5 (A) 100 6 003aad155 100 ID (A) 80 80 5.5 60 60 Tj = 150 °C 40 5 40 Tj = 25 °C VGS (V) = 4.5 0 0 0 Fig 5. Tj = 175 °C 20 20 1 2 3 VDS (V) 0 4 Output characteristics: drain current as a function of drain-source voltage; typical values C (pF) 4 6 8 VGS (V) Fig 6. 003aad159 4000 2 Transfer characteristics: drain current as a function of gate-source voltage; typical values 003aad160 80 gfs (S) Ciss 3000 60 2000 40 Crss 1000 20 0 0 0 Fig 7. 3 6 9 V (V) 12 GS Input and reverse transfer capacitances as a function of gate-source voltage; typical values 0 Fig 8. 40 60 ID (A) 80 Forward transconductance as a function of drain current; typical values PSMN4R0-40YS_1 Product data sheet 20 © NXP B.V. 2009. All rights reserved. Rev. 01 — 25 June 2009 6 of 13 PSMN4R0-40YS NXP Semiconductors N-channel LFPAK 40 V 4.2 mΩ standard level MOSFET 003aad161 15 ID (A) RDSon (mΩ) 12 min 10−2 9 10−3 6 10−4 3 10−5 typ max 10−6 0 0 Fig 9. 03aa35 10−1 5 10 15 VGS (V) 20 0 4 6 VGS (V) Drain-source on-state resistance as a function of gate-source voltage; typical values Fig 10. Sub-threshold drain current as a function of gate-source voltage 003aad280 5 2 VGS(th) (V) 03aa27 2 a 4 max 3 1.5 typ 1 2 min 0.5 1 0 −60 0 60 120 180 Tj (°C) Fig 11. Gate-source threshold voltage as a function of junction temperature 0 −60 60 120 Tj (°C) 180 Fig 12. Normalized drain-source on-state resistance factor as a function of junction temperature PSMN4R0-40YS_1 Product data sheet 0 © NXP B.V. 2009. All rights reserved. Rev. 01 — 25 June 2009 7 of 13 PSMN4R0-40YS NXP Semiconductors N-channel LFPAK 40 V 4.2 mΩ standard level MOSFET 003aad162 12 VGS (V) = 5.5 VDS RDSon (mΩ) ID 9 6 VGS(pl) VGS(th) 6 6.5 VGS 7 8 QGS1 10 20 3 QGS2 QGS QGD QG(tot) 003aaa508 0 0 30 60 90 ID (A) 120 Fig 14. Gate charge waveform definitions Fig 13. Drain-source on-state resistance as a function of drain current; typical values 003aad157 10 VGS (V) VDS = 20V 003aad158 104 C (pF) 8 8V Ciss 6 32V 103 4 Coss 2 Crss 0 0 10 20 30 QG (nC) 40 Fig 15. Gate-source voltage as a function of gate charge; typical values 102 10-1 10 VDS (V) 102 Fig 16. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values PSMN4R0-40YS_1 Product data sheet 1 © NXP B.V. 2009. All rights reserved. Rev. 01 — 25 June 2009 8 of 13 PSMN4R0-40YS NXP Semiconductors N-channel LFPAK 40 V 4.2 mΩ standard level MOSFET 003aad156 100 IS (A) 80 60 40 Tj = 150 °C Tj = 175 °C 20 Tj = 25 °C 0 0 0.3 0.6 0.9 1.2 VSD (V) Fig 17. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values PSMN4R0-40YS_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 25 June 2009 9 of 13 PSMN4R0-40YS NXP Semiconductors N-channel LFPAK 40 V 4.2 mΩ standard level MOSFET 7. Package outline Plastic single-ended surface-mounted package (LFPAK); 4 leads A2 A E SOT669 C c2 b2 E1 b3 L1 mounting base b4 D1 D H L2 1 2 3 e 4 w M A b 1/2 X c e A (A 3) A1 C θ L detail X y C 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) A UNIT A1 A2 A3 b b2 1.20 0.15 1.10 0.50 4.41 0.25 1.01 0.00 0.95 0.35 3.62 mm b3 b4 2.2 2.0 0.9 0.7 c D (1) c2 D1(1) E(1) E1(1) max 0.25 0.30 4.10 4.20 0.19 0.24 3.80 5.0 4.8 3.3 3.1 e H L L1 L2 w y θ 1.27 6.2 5.8 0.85 0.40 1.3 0.8 1.3 0.8 0.25 0.1 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT669 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-10-13 06-03-16 MO-235 Fig 18. Package outline SOT669 (LFPAK) PSMN4R0-40YS_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 25 June 2009 10 of 13 PSMN4R0-40YS NXP Semiconductors N-channel LFPAK 40 V 4.2 mΩ standard level MOSFET 8. Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes PSMN4R0-40YS_1 20090625 Product data sheet - - PSMN4R0-40YS_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 25 June 2009 11 of 13 PSMN4R0-40YS NXP Semiconductors N-channel LFPAK 40 V 4.2 mΩ standard level MOSFET 9. Legal information 9.1 Data sheet status Document status [1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 9.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS — is a trademark of NXP B.V. 10. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PSMN4R0-40YS_1 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 01 — 25 June 2009 12 of 13 PSMN4R0-40YS NXP Semiconductors N-channel LFPAK 40 V 4.2 mΩ standard level MOSFET 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3 Thermal characteristics . . . . . . . . . . . . . . . . . . .4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . .12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Contact information. . . . . . . . . . . . . . . . . . . . . .12 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 25 June 2009 Document identifier: PSMN4R0-40YS_1