PHD108NQ03LT N-channel TrenchMOS logic level FET Rev. 04 — 5 June 2009 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. 1.2 Features and benefits Low conduction losses due to low on-state resistance Suitable for logic level gate drive sources Simple gate drive required due to low gate charge 1.3 Applications DC-to-DC convertors Switched-mode power supplies 1.4 Quick reference data Table 1. Quick reference Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 25 V ID drain current Tmb = 25 °C; VGS = 5 V; see Figure 1; see Figure 3 - - 75 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - - 187 W VGS = 10 V; Tj(init) = 25 °C; ID = 43 A; Vsup ≤ 25 V; unclamped; tp = 0.25 ms; RGS = 50 Ω - - 180 mJ VGS = 4.5 V; ID = 25 A; VDS = 12 V; Tj = 25 °C; see Figure 12; see Figure 13 - 5.6 - nC VGS = 10 V; ID = 25 A; Tj = 25 °C; see Figure 10; see Figure 11 - 5.3 6 mΩ Avalance ruggedness EDS(AL)S non-repetitive drain-source avalanche energy Dynamic characteristics QGD gate-drain charge Static characteristics RDSon drain-source on-state resistance PHD108NQ03LT NXP Semiconductors N-channel TrenchMOS logic level FET 2. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1 G gate 2 D drain 3 S source mb D mounting base; connected to drain Graphic symbol D mb [1] G mbb076 S 2 1 3 SOT428 (SC-63; DPAK) [1] It is not possible to make a connection to pin 2. 3. Ordering information Table 3. Ordering information Type number PHD108NQ03LT Package Name Description Version SC-63; DPAK plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped) SOT428 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 25 V VDGR drain-gate voltage Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ - 25 V VGS gate-source voltage ID drain current -20 20 V VGS = 5 V; Tmb = 25 °C; see Figure 1; see Figure 3 - 75 A VGS = 5 V; Tmb = 100 °C; see Figure 1 - 75 A - 240 A IDM peak drain current tp ≤ 10 µs; pulsed; Tmb = 25 °C; see Figure 3 Ptot total power dissipation Tmb = 25 °C; see Figure 2 - 187 W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Source-drain diode IS source current Tmb = 25 °C - 75 A ISM peak source current tp ≤ 10 µs; pulsed; Tmb = 25 °C - 240 A - 180 mJ Avalance ruggedness EDS(AL)S non-repetitive VGS = 10 V; Tj(init) = 25 °C; ID = 43 A; Vsup ≤ 25 V; drain-source avalanche unclamped; tp = 0.25 ms; RGS = 50 Ω energy PHD108NQ03LT_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 5 June 2009 2 of 12 PHD108NQ03LT NXP Semiconductors N-channel TrenchMOS logic level FET 03ar58 120 03aa16 120 Ider (%) Pder (%) 80 80 40 40 0 0 0 Fig 1. 50 100 150 Tmb (°C) 200 0 50 100 150 200 Tmb (°C) Fig 2. Normalized continuous drain current as a function of mounting base temperature Normalized total power dissipation as a function of mounting base temperature 03ar59 103 ID (A) Limit RDSon = VDS / ID tp = 10 µs 102 100 μ s DC 1 ms 10 10 ms 1 1 Fig 3. 10 102 VDS (V) Safe operating area; continuous and peak drain currents as a function of drain-source voltage PHD108NQ03LT_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 5 June 2009 3 of 12 PHD108NQ03LT NXP Semiconductors N-channel TrenchMOS logic level FET 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Rth(j-mb) Rth(j-a) Conditions Min Typ Max Unit thermal resistance from see Figure 4 junction to mounting base - - 0.8 K/W thermal resistance from minimum footprint; mounted on a junction to ambient printed-circuit board; vertical in still air - 75 - K/W - 50 - K/W mounted on a printed-circuit board; vertical in still air; SOT404 minimum footprint 03ar60 1 δ = 0.5 Zth(j-mb) (K/W) 0.2 0.1 10-1 0.05 δ= P 0.02 tp T single pulse t tp 10 T -2 Fig 4. 10-5 10-4 10-3 10-2 10-1 1 tp (s) Transient thermal impedance from junction to mounting base as a function of pulse duration 6. Characteristics Table 6. Symbol Characteristics Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 25 - - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 22 - - V VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 25 °C; see Figure 8; see Figure 9 1 1.5 2 V ID = 1 mA; VDS = VGS; Tj = 175 °C; see Figure 8; see Figure 9 0.5 - - V ID = 1 mA; VDS = VGS; Tj = -55 °C; see Figure 8; see Figure 9 - - 2.2 V - - 1 µA IDSS drain leakage current VDS = 25 V; VGS = 0 V; Tj = 25 °C VDS = 25 V; VGS = 0 V; Tj = 175 °C - - 500 µA IGSS gate leakage current VGS = 10 V; VDS = 0 V; Tj = 25 °C - 0.02 100 nA VGS = -10 V; VDS = 0 V; Tj = 25 °C - 0.02 100 nA PHD108NQ03LT_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 5 June 2009 4 of 12 PHD108NQ03LT NXP Semiconductors N-channel TrenchMOS logic level FET Table 6. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit RDSon drain-source on-state resistance VGS = 5 V; ID = 25 A; Tj = 25 °C; see Figure 10; see Figure 11 - 6.7 7.5 mΩ VGS = 5 V; ID = 25 A; Tj = 175 °C; see Figure 10; see Figure 11 - 12.1 13.5 mΩ VGS = 10 V; ID = 25 A; Tj = 25 °C; see Figure 10; see Figure 11 - 5.3 6 mΩ - 1.2 - Ω ID = 25 A; VDS = 12 V; VGS = 4.5 V; Tj = 25 °C; see Figure 12; see Figure 13 - 16.3 - nC ID = 0 A; VDS = 0 V; VGS = 4.5 V; Tj = 25 °C - 12.5 - nC ID = 25 A; VDS = 12 V; VGS = 4.5 V; Tj = 25 °C; see Figure 12; see Figure 13 - 4 - nC - 2.5 - nC - 1.5 - nC RG internal gate resistance f = 1 MHz; Tj = 25 °C (AC) Dynamic characteristics QG(tot) total gate charge QGS gate-source charge QGS1 pre-threshold gate-source charge QGS2 post-threshold gate-source charge QGD gate-drain charge - 5.6 - nC VGS(pl) gate-source plateau voltage ID = 25 A; VDS = 12 V; Tj = 25 °C; see Figure 12; see Figure 13 - 2.4 - V Ciss input capacitance VDS = 12 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 14 - 1375 - pF VDS = 0 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 14 - 2120 - pF VDS = 12 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 14 - 640 - pF - 250 - pF - 15 - ns - 38 - ns Coss output capacitance Crss reverse transfer capacitance td(on) turn-on delay time tr rise time td(off) turn-off delay time - 32 - ns tf fall time - 25 - ns VDS = 12 V; RL = 0.5 Ω; VGS = 4.5 V; RG(ext) = 5.6 Ω; Tj = 25 °C Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; see Figure 15 - 0.86 1.2 V trr reverse recovery time - 34 - ns Qr recovered charge IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 25 V; Tj = 25 °C - 21 - nC PHD108NQ03LT_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 5 June 2009 5 of 12 PHD108NQ03LT NXP Semiconductors N-channel TrenchMOS logic level FET 03ar67 4000 C (pF) 03ar63 80 ID (A) Ciss 3000 60 Crss 2000 40 1000 20 25 °C Tj = 175 °C 0 0 0 Fig 5. 2 4 6 8 VGS (V) 10 Input and reverse transfer capacitances as a function of gate-source voltage; typical values 0 Fig 6. 03ar61 80 VGS (V) = ID (A) 10 6 5 4.5 1 2 3 4 Transfer characteristics: drain current as a function of gate-source voltage; typical values 03aa33 2.5 4 VGS (V) VGS(th) (V) 3.5 2 max 60 3 1.5 typ 1 min 40 2.5 20 0.5 2 0 0 Fig 7. 0.2 0.4 0.6 0.8 VDS (V) 0 -60 1 Output characteristics: drain current as a function of drain-source voltage; typical values Fig 8. 60 120 Tj (°C) 180 Gate-source threshold voltage as a function of junction temperature PHD108NQ03LT_4 Product data sheet 0 © NXP B.V. 2009. All rights reserved. Rev. 04 — 5 June 2009 6 of 12 PHD108NQ03LT NXP Semiconductors N-channel TrenchMOS logic level FET 03aa36 10-1 ID (A) 03ar62 15 VGS (V) = 3.5 RDSon (mΩ) 10-2 10 4 10-3 min typ 4.5 5 6 10 max 10-4 5 10-5 10-6 0 0 Fig 9. 1 2 Sub-threshold drain current as a function of gate-source voltage 03af18 2 0 3 VGS (V) 40 60 ID (A) 80 Fig 10. Drain-source on-state resistance as a function of drain current; typical values 03ar64 10 VGS (V) a 20 ID = 25 A Tj = 25 °C 8 1.5 6 VDS = 19 V 12 V 1 4 0.5 2 0 -60 0 60 120 Tj (°C) 180 Fig 11. Normalized drain-source on-state resistance factor as a function of junction temperature 0 0 20 30 QG (nC) 40 Fig 12. Gate-source voltage as a function of gate charge; typical values PHD108NQ03LT_4 Product data sheet 10 © NXP B.V. 2009. All rights reserved. Rev. 04 — 5 June 2009 7 of 12 PHD108NQ03LT NXP Semiconductors N-channel TrenchMOS logic level FET 03ar66 104 VDS C (pF) ID VGS(pl) Ciss VGS(th) 103 VGS QGS1 Coss QGS2 QGS QGD QG(tot) Crss 003aaa508 102 10-1 Fig 13. Gate charge waveform definitions 1 10 VDS (V) 102 Fig 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values 03ar65 80 IS (A) 60 40 175 °C Tj = 25 °C 20 0 0.2 0.4 0.6 0.8 1 VSD (V) 1.2 Fig 15. Source current as a function of source-drain voltage; typical values PHD108NQ03LT_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 5 June 2009 8 of 12 PHD108NQ03LT NXP Semiconductors N-channel TrenchMOS logic level FET 7. Package outline Plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped) SOT428 y E A A A1 b2 E1 mounting base D2 D1 HD 2 L L2 1 L1 3 b1 b w M c A e e1 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b b1 b2 c D1 D2 min E E1 min e e1 HD L L1 min L2 w y max mm 2.38 2.22 0.93 0.46 0.89 0.71 1.1 0.9 5.46 5.00 0.56 0.20 6.22 5.98 4.0 6.73 6.47 4.45 2.285 4.57 10.4 9.6 2.95 2.55 0.5 0.9 0.5 0.2 0.2 OUTLINE VERSION SOT428 REFERENCES IEC JEDEC JEITA TO-252 SC-63 EUROPEAN PROJECTION ISSUE DATE 06-02-14 06-03-16 Fig 16. Package outline SOT428 (DPAK) PHD108NQ03LT_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 5 June 2009 9 of 12 PHD108NQ03LT NXP Semiconductors N-channel TrenchMOS logic level FET 8. Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes PHD108NQ03LT_4 20090605 Product data sheet - PHB_PHD_PHU108NQ03LT_3 Modifications: PHB_PHD_PHU108NQ03LT_3 (9397 750 14707) • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Type number PHD108NQ03LT separated from data sheet PHB_PHD_PHU108NQ03LT_3. 20050418 Product data sheet 2004070095 PHP_PHB_PHD108NQ03LT-02 PHP_PHB_PHD108NQ03LT-02 20020911 (9397 750 10159) Product data - PHP_PHB_PHD108NQ03LT-01 PHP_PHB_PHD108NQ03LT-01 20011218 (9397 750 09065) Product data - - PHD108NQ03LT_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 5 June 2009 10 of 12 PHD108NQ03LT NXP Semiconductors N-channel TrenchMOS logic level FET 9. Legal information 9.1 Data sheet status Document status [1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 9.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS — is a trademark of NXP B.V. 10. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PHD108NQ03LT_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 5 June 2009 11 of 12 PHD108NQ03LT NXP Semiconductors N-channel TrenchMOS logic level FET 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2 Thermal characteristics . . . . . . . . . . . . . . . . . . .4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .10 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information. . . . . . . . . . . . . . . . . . . . . . 11 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 5 June 2009 Document identifier: PHD108NQ03LT_4