Philips Semiconductors Product specification Octal D-type flip-flop; positive-edge trigger (3-State) FEATURES 74ABT374A DESCRIPTION • 8-bit positive edge triggered register • 3-State output buffers • Output capability: +64mA/–32mA • Latch-up protection exceeds 500mA per Jedec Std 17 • ESD protection exceeds 2000 V per MIL STD 883 Method 3015 The 74ABT374A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT374A is an 8-bit, edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by the clock (CP) and Output Enable (OE) control gates. and 200 V per Machine Model The register is fully edge triggered. The state of each D input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flop’s Q output. • Power-up 3-State • Power-up reset • Live insertion/extraction permitted The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all eight 3-State buffers independent of the clock operation. When OE is Low, the stored data appears at the outputs. When OE is High, the outputs are in the High-impedance “OFF” state, which means they will neither drive nor load the bus. QUICK REFERENCE DATA SYMBOL CONDITIONS Tamb = 25°C; GND = 0V PARAMETER tPLH tPHL Propagation delay CP to Qn CL = 50pF; VCC = 5V CIN TYPICAL UNIT 3.4 3.8 ns pF Input capacitance VI = 0V or VCC 4 COUT Output capacitance Outputs disabled; VO = 0V or VCC 7 pF ICCZ Total supply current Outputs disabled; VCC =5.5V 110 µA ORDERING INFORMATION TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 20-Pin Plastic DIP PACKAGES –40°C to +85°C 74ABT374A N 74ABT374A N SOT146-1 20-Pin plastic SO –40°C to +85°C 74ABT374A D 74ABT374A D SOT163-1 20-Pin Plastic SSOP Type II –40°C to +85°C 74ABT374A DB 74ABT374A DB SOT339-1 20-Pin Plastic TSSOP Type I –40°C to +85°C 74ABT374A PW 74ABT374APW DH SOT360-1 PIN CONFIGURATION PIN DESCRIPTION OE 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 PIN NUMBER SYMBOL 1 OE 3, 4, 7, 8, 13, 14, 17, 18 D0-D7 Data inputs 2, 5, 6, 9, 12, 15, 16, 19 Q0-Q7 Data outputs FUNCTION Output enable input (active-Low) D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 11 CP D3 8 13 D4 10 GND Ground (0V) Q3 9 12 Q4 20 VCC Positive supply voltage 11 CP GND 10 Clock pulse input (active rising edge) SA00110 1995 Sep 06 1 853-1448 15704 Philips Semiconductors Product specification Octal D-type flip-flop; positive-edge trigger (3-State) LOGIC SYMBOL 74ABT374A LOGIC SYMBOL (IEEE/IEC) 3 4 7 8 13 14 17 18 1 EN 11 C1 D0 D1 D2 D3 D4 D5 D6 D7 11 CP 3 1 OE 4 5 7 6 2 1D Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 8 2 5 6 9 12 15 16 19 SA00111 9 13 12 14 15 17 16 18 19 SA00112 FUNCTION TABLE CP Dn INTERNAL REGISTER OUTPUTS OE INPUTS L ↑ l L L L ↑ h H H L ↑ X NC NC H ↑ X NC Z H H = h = L = l = NC= X = Z = ↑ = ↑ = OPERATING MODE Q0 – Q7 Latch and read register Hold Disable outputs ↑ Dn Dn Z High voltage level High voltage level one set-up time prior to the Low-to-High clock transition Low voltage level Low voltage level one set-up time prior to the Low-to-High clock transition No change Don’t care High impedance “off” state Low-to-High clock transition not a Low-to-High clock transition LOGIC DIAGRAM D1 D0 3 D2 4 D3 7 D4 8 D5 13 D6 14 D7 17 18 D D D D D D D D CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q 11 CP 1 OE 2 Q0 5 Q1 6 9 Q2 Q3 12 Q4 15 Q5 16 Q6 19 Q7 SA00113 1995 Sep 06 2 Philips Semiconductors Product specification Octal D-type flip-flop; positive-edge trigger (3-State) 74ABT374A ABSOLUTE MAXIMUM RATINGS1, 2 PARAMETER SYMBOL VCC IIK CONDITIONS RATING UNIT –0.5 to +7.0 V –18 mA –1.2 to +7.0 V VO < 0 –50 mA output in Off or High state –0.5 to +5.5 V 128 mA –65 to 150 °C DC supply voltage DC input diode current VI < 0 voltage3 VI DC input IOK DC output diode current voltage3 VOUT DC output IOUT DC output current Tstg Storage temperature range output in Low state NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL VCC PARAMETER UNIT DC supply voltage MIN MAX 4.5 5.5 V 0 VCC V VI Input voltage VIH High-level input voltage VIL Low-level input voltage 0.8 V IOH High-level output current –32 mA IOL Low-level output current 64 mA 0 10 ns/V –40 +85 °C ∆t/∆v Input transition rise or fall rate Tamb Operating free-air temperature range 1995 Sep 06 2.0 3 V Philips Semiconductors Product specification Octal D-type flip-flop; positive-edge trigger (3-State) 74ABT374A DC ELECTRICAL CHARACTERISTICS LIMITS PARAMETER SYMBOL TEST CONDITIONS MIN VIK VOH Input clamp voltage High-level output voltage Tamb = –40°C to +85°C Tamb = +25°C VCC = 4.5V; IIK = –18mA TYP MAX –0.9 –1.2 MIN UNIT MAX –1.2 V VCC = 4.5V; IOH = –3mA; VI = VIL or VIH 2.5 2.9 2.5 V VCC = 5.0V; IOH = –3mA; VI = VIL or VIH 3.0 3.4 3.0 V VCC = 4.5V; IOH = –32mA; VI = VIL or VIH 2.0 2.4 2.0 V VOL Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or VIH 0.42 0.55 0.55 V VRST Power-up output low voltage3 VCC = 5.5V; IO = 1mA; VI = GND or VCC 0.13 0.55 0.55 V Input leakage current VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA Power-up/down 3-State output current VCC = 0.0V; IO = 1mA; VI = GND or VCC; V OE = Don’t Care ±5.0 ±50 ±50 µA IOZH 3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or VIH 5.0 50 50 µA IOZL 3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or VIH –5.0 –50 –50 µA ICEX Output High leakage current VCC = 5.5V; VO = 0.5V; VI = GND or VCC 5.0 50 50 µA –100 –180 –180 mA VCC = 5.5V; Outputs High, VI = GND or VCC 110 250 250 µA VCC = 5.5V; Outputs Low, VI = GND or VCC 24 30 30 mA VCC = 5.5V; Outputs 3–State; VI = GND or VCC 110 250 250 µA VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND 0.5 1.5 1.5 mA II IOFF IPU/IPD IO Output current1 ICCH ICCL Quiescent supply current ICCZ ∆ICC Additional supply current per input pin2 VCC = 5.5V; VO = 2.5V –50 –50 NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. AC CHARACTERISTICS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = -40 to +85oC VCC = +5.0V ±0.5V Tamb = +25oC VCC = +5.0V WAVEFORM Min Typ fMAX Maximum clock frequency 1 200 300 tPLH tPHL Propagation delay CP to Qn 1 1.7 2.0 3.4 3.8 4.5 4.9 1.7 2.0 5.1 5.2 ns tPZH tPZL Output enable time to High and Low level 3 4 1.2 2.2 3.5 4.3 4.5 5.4 1.2 2.2 5.4 6.2 ns tPHZ tPLZ Output disable time from High and Low level 3 4 1.8 1.5 3.6 3.0 4.7 4.1 1.8 1.5 5.2 4.3 ns 1995 Sep 06 4 Max Min UNIT Max 200 ns Philips Semiconductors Product specification Octal D-type flip-flop; positive-edge trigger (3-State) 74ABT374A AC SETUP REQUIREMENTS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = +25oC VCC = +5.0V WAVEFORM Tamb = -40 to +85oC VCC = +5.0V ±0.5V UNIT Min Typ Min 2 1.5 1.2 0.6 0.3 1.5 1.2 ns Hold time, High or Low Dn to CP 2 1.0 1.0 –0.3 –0.5 1.0 1.0 ns CP pulse width High or Low 1 2.0 2.8 0.8 1.0 2.0 2.8 ns ts(H) ts(L) Setup time, High or Low Dn to CP th(H) th(L) tw(H) tw(L) AC WAVEFORMS VM = 1.5V, VIN = GND to 3.0V 1/fMAX CP VM VM OE VM VM VM tPZH tw(H) tPHL tPLH Qn tPHZ tw(L) VM Qn VOH–0.3V VM VM 0V SA00056 SA00066 Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency Waveform 3. 3-State Output Enable Time to High Level and Output Disable Time from High Level ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ VM Dn VM ts(H) VM th(H) VM ts(L) OE VM VM th(L) tPZL tPLZ CP VM VM Qn VM VOL+0.3V 0V NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SA00107 SA00067 Waveform 2. Data Setup and Hold Times 1995 Sep 06 Waveform 4. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level 5 Philips Semiconductors Product specification Octal D-type flip-flop; positive-edge trigger (3-State) 74ABT374A TEST CIRCUIT AND WAVEFORM VCC 7.0V PULSE GENERATOR VIN tW 90% VOUT VM NEGATIVE PULSE CL 10% 0V RL tTHL (tF) tTLH (tR) tTLH (tR) tTHL (tF) 90% POSITIVE PULSE Test Circuit for 3-State Outputs AMP (V) 90% VM VM 10% 10% tW SWITCH POSITION TEST SWITCH tPLZ closed tPZL closed All other open AMP (V) VM 10% RL D.U.T. RT 90% 0V VM = 1.5V Input Pulse Definition INPUT PULSE REQUIREMENTS DEFINITIONS FAMILY RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 74ABT Amplitude Rep. Rate tW tR tF 3.0V 1MHz 500ns 2.5ns 2.5ns SA00012 1995 Sep 06 6