Philips Semiconductors Product specification Octal registered transceiver, inverting (3-State) FEATURES 74ABT2953 DESCRIPTION • 8-bit registered transceiver • Independent registers for A and B buses • Output capability: +64mA/–32mA • Latch-up protection exceeds 500mA per Jedec Std 17 • ESD protection exceeds 2000V per MIL STD 883 Method 3015 The 74ABT2953 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT2953 device is an 8-bit registered inverting transceiver. Two 8-bit back-to-back registers store data flowing in both directions between two bidirectional buses. Data applied to the inputs is entered and stored on the rising edge of the Clock (CPXX) provided that the Clock Enable (CEXX) is Low. The data is then present at the 3-State output buffers, but is only accessible when the Output Enable (OEXX) is Low. Data flow from A inputs to B outputs is the same as for B inputs to A outputs. and 200V per Machine Model • Live insertion/extraction permitted • Power-up 3-State • Power-up reset QUICK REFERENCE DATA SYMBOL CONDITIONS Tamb = 25°C; GND = 0V PARAMETER TYPICAL UNIT 5.0 ns tPLH tPHL Propagation delay CPBA to An or CPAB to Bn CL = 50pF; VCC = 5V CIN Input capacitance VI = 0V or VCC 4 pF CI/O I/O capacitance Outputs disabled; VO = 0V or VCC 7 pF ICCZ Total supply current Outputs disabled; VCC =5.5V 500 nA ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 24-Pin Plastic DIP –40°C to +85°C 74ABT9253 N 74ABT2953 N SOT222-1 24-Pin plastic SO –40°C to +85°C 74ABT2953 D 74ABT2953 D SOT137-1 24-Pin Plastic SSOP Type II –40°C to +85°C 74ABT2953 DB 74ABT2953 DB SOT340-1 24-Pin Plastic TSSOP Type I –40°C to +85°C 74ABT2953 PW 74ABT2953PW DH SOT355-1 PIN CONFIGURATION PIN DESCRIPTION B7 1 24 VCC B6 2 23 A7 B5 3 22 A6 B4 4 21 A5 B3 5 20 A4 B2 6 19 A3 B1 7 18 A2 B0 8 17 A1 OEAB 9 16 A0 CPAB 10 15 OEBA CEAB 11 14 CPBA GND 12 13 CEBA PIN NUMBER SYMBOL NAME AND FUNCTION 10, 14 CPAB / CPBA Clock input A to B / Clock input B to A 11, 13 CEAB / CEBA Clock enable input A to B / Clock enable input B to A 16, 17, 18, 19, 20, 21, 22, 23 A0 – A7 Data inputs/outputs (A side) 1, 2, 3, 4, 5, 6, 7, 8 B0 – B7 Data outputs/outputs (B side) 9, 15 OEAB / OEBA Output enable inputs 12 GND Ground (0V) 24 VCC Positive supply voltage TOP VIEW SA00305 1995 Sep 06 1 853-1555 15702 Philips Semiconductors Product specification Octal registered transceiver, inverting (3-State) LOGIC SYMBOL 74ABT2953 LOGIC SYMBOL (IEEE/IEC) 11 EN1 13 16 17 18 19 20 21 22 23 EN2 15 EN3 9 C5 14 10 CPAB 11 CEAB OEBA 15 14 CPBA OEAB 9 13 CEBA 7 6 5 4 3 2 C6 16 B0 B1 B2 B3 B4 B5 B6 B7 8 EN4 10 A0 A1 A2 A3 A4 A5 A6 A7 1 2, 3, 6 8 1, 4, 5 17 7 18 6 19 5 20 4 21 3 22 2 23 1 SA00306 SA00307 FUNCTION TABLE for Register An or Bn INPUTS FUNCTION TABLE for Output Enable INTERNAL OPERATING MODE An or Bn CPXX CEXX Q X X H NC L H ↑ ↑ L L L H INPUTS INTERNAL An or Bn OPERATING OEXX Q OUTPUTS MODE H X Z Disable outputs L L L H H L Enable outputs Hold data Load data H = High voltage level L = Low voltage level X = Don’t care XX = AB or BA Z = High impedance ”off” state H = High voltage level L = Low voltage level ↑ = Low-to-High transition X = Don’t care XX = AB or BA NC= No change ABSOLUTE MAXIMUM RATINGS1, 2 SYMBOL VCC IIK PARAMETER CONDITIONS RATING UNIT –0.5 to +7.0 V –18 mA –1.2 to +7.0 V VO < 0 –50 mA output in Off or High state –0.5 to +5.5 V output in Low state 128 mA –65 to 150 °C DC supply voltage DC input diode current VI < 0 voltage3 VI DC input IOK DC output diode current voltage3 VOUT DC output IOUT DC output current Tstg Storage temperature range NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1995 Sep 06 2 Philips Semiconductors Product specification Octal registered transceiver, inverting (3-State) 74ABT2953 LOGIC DIAGRAM CEAB CPAB OEAB 11 10 9 DETAIL A CE A0 Q 16 D CP Q CE D 8 B0 CP A1 A2 A3 A4 A5 A6 A7 CEBA CPBA OEBA 17 7 18 6 19 5 20 DETAIL A X 7 4 21 3 22 2 23 1 B1 B2 B3 B4 B5 B6 B7 13 14 15 SA00308 1995 Sep 06 3 Philips Semiconductors Product specification Octal registered transceiver, inverting (3-State) 74ABT2953 RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER LIMITS DC supply voltage UNIT Min Max 4.5 5.5 V 0 VCC V VI Input voltage VIH High-level input voltage VIL Low-level Input voltage 0.8 V IOH High-level output current –32 mA IOL Low-level output current 64 mA 0 10 ns/V –40 +85 °C 2.0 ∆t/∆v Input transition rise or fall rate Tamb Operating free-air temperature range V DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Min VIK VOH Input clamp voltage High-level output voltage Tamb = –40°C to +85°C Tamb = +25°C VCC = 4.5V; IIK = –18mA Typ Max –0.9 –1.2 Min UNIT Max –1.2 V VCC = 4.5V; IOH = –3mA; VI = VIL or VIH 2.5 3.2 2.5 V VCC = 5.0V; IOH = –3mA; VI = VIL or VIH 3.0 3.7 3.0 V VCC = 4.5V; IOH = –32mA; VI = VIL or VIH 2.0 2.3 2.0 V VOL Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or VIH 0.42 0.55 0.55 V VRST Power-up output low voltage3 VCC = 5.5V; IO = 1mA; VI = GND or VCC 0.13 0.55 0.55 V Input leakage Control pins VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA current Data pins VCC = 5.5V; VI = GND or 5.5V ±5 ±100 ±100 µA II Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA Power-up/down 3-State output current4 VCC = 2.1V; VO = 0.5V; VI = GND or VCC; V OE = Don’t care ±5.0 ±50 ±50 µA IOZH 3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or VIH 5.0 50 50 µA IOZL 3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or VIH –5.0 –50 –50 µA ICEX Output High leakage current VCC = 5.5V; VO = 5.5V; VI = GND or VCC 5.0 50 50 µA –65 –180 –180 mA VCC = 5.5V; Outputs High, VI = GND or VCC 110 250 250 µA VCC = 5.5V; Outputs Low, VI = GND or VCC 20 30 30 mA VCC = 5.5V; Outputs 3-State; VI = GND or VCC 110 250 250 µA VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND 0.3 1.5 1.5 mA IOFF IPU/IPD IO Output current1 ICCH ICCL Quiescent supply current ICCZ ∆ICC Additional supply current per input pin2 VCC = 5.5V; VO = 2.5V –50 –50 NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V, with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10% a transition time of up to 100µsec is permitted. 1995 Sep 06 4 Philips Semiconductors Product specification Octal registered transceiver, inverting (3-State) 74ABT2953 AC CHARACTERISTICS GND = 0V; tR = tF = 2.5ns; CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = +25°C VCC = +5.0V WAVEFORM Tamb = –40°C to +85°C VCC = +5.0V ±0.5V Max Min UNIT Min Typ fMAX Maximum clock frequency 1 150 200 Max tPLH tPHL Propagation delay CPBA to An, CPAB to Bn 1 2.0 2.5 5.1 5.7 6.6 7.2 2.0 2.5 7.6 8.2 ns tPZH tPZL Output enable time OEBA to An, OEAB to Bn 3 4 1.0 2.2 4.0 5.3 4.8 6.2 1.0 2.2 5.8 7.5 ns tPHZ tPLZ Output disable time OEBA to An, OEAB to Bn 3 4 2.0 1.5 6.1 5.6 7.6 7.1 2.0 1.5 8.1 7.6 ns 150 MHz AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER Tamb = +25°C VCC = +5.0V WAVEFORM Tamb = –40°C to +85°C VCC = +5.0V ±0.5V UNIT Min Typ Min 2 4.0 3.0 2.5 1.1 4.0 3.0 ns Hold time An to CPAB or Bn to CPBA 2 0.0 0.0 –1.0 –2.0 0.0 0.0 ns ts(H) ts(L) Setup time CEAB to CPAB, CEBA to CPBA 2 3.5 2.5 2.0 0.9 3.5 2.5 ns th(H) th(L) Hold time CEAB to CPAB, CEBA to CPBA 2 0.0 0.0 –0.5 –1.0 0.0 0.0 ns tw(H) tw(L) CPAB or CPBA pulse width, High or Low 1 3.0 3.5 2.0 1.1 3.0 3.5 ns tS(H) ts(L) Setup time An to CPAB or Bn to CPBA th(H) th(L) AC WAVEFORMS ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ VM = 1.5V, VIN = GND to 3.0V 1/fMAX CPBA or CPAB VM VM tw(H) VM VM VM th(H) CPAB, CPBA tPLH VM VM ts(H) tw(L) tPHL An or Bn An, Bn CEAB, CEBA VM ts(L) VM th(L) VM SA00309 VM Waveform 2. Data Setup and Hold Times SA00087 Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency OEAB, OEBA VM tPZH An, Bn OEAB, OEBA VM VOH –0.3V An, Bn 0V SA00310 tPLZ VM VOL +0.3V 0V SA00311 Waveform 3. 3-State Output Enable Time to High Level and Output Disable Time from High Level 1995 Sep 06 VM tPZL tPHZ VM VM Waveform 4. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level 5 Philips Semiconductors Product specification Octal registered transceiver, inverting (3-State) 74ABT2953 TEST CIRCUIT AND WAVEFORMS VCC 7.0V PULSE GENERATOR VIN tW 90% VOUT VM NEGATIVE PULSE 10% 0V tTLH (tR) tTHL (tF) CL tTLH (tR) RL tTHL (tF) 90% POSITIVE PULSE Test Circuit for 3-State Outputs AMP (V) 90% VM VM 10% 10% tW SWITCH POSITION TEST SWITCH tPLZ closed tPZL closed All other open AMP (V) VM 10% RL D.U.T. RT 90% 0V VM = 1.5V Input Pulse Definition INPUT PULSE REQUIREMENTS DEFINITIONS FAMILY RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 74ABT Amplitude Rep. Rate tW tR tF 3.0V 1MHz 500ns 2.5ns 2.5ns SA00012 1995 Sep 06 6