PSMN5R0-30YL N-channel TrenchMOS logic level FET Rev. 03 — 4 January 2010 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in industrial and communications applications. 1.2 Features and benefits High efficiency due to low switching and conduction losses Suitable for logic level gate drive sources 1.3 Applications Class-D amplifiers Motor control DC-to-DC converters Server power supplies 1.4 Quick reference data Table 1. Quick reference Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 30 V ID drain current Tmb = 25 °C; VGS = 10 V; see Figure 1 - - 91 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - - 61 W Dynamic characteristics QGD gate-drain charge VGS = 4.5 V; ID = 10 A; VDS = 12 V; see Figure 14 and 15 - 3.8 - nC QG(tot) total gate charge VGS = 4.5 V; ID = 10 A; VDS = 12 V; see Figure 14 - 14.1 - nC VGS = 10 V; ID = 15 A; Tj = 25 °C - 3.63 5 mΩ Static characteristics RDSon drain-source on-state resistance PSMN5R0-30YL NXP Semiconductors N-channel TrenchMOS logic level FET 2. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline 1 S source 2 S source 3 S source 4 G gate mb D mounting base; connected to drain Graphic symbol D mb G S mbb076 1 2 3 4 SOT669 (LFPAK) 3. Ordering information Table 3. Ordering information Type number Package Name Description Version PSMN5R0-30YL LFPAK plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 30 V VDGR drain-gate voltage Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ - 30 V VGS gate-source voltage ID drain current -20 20 V VGS = 10 V; Tmb = 100 °C; see Figure 1 - 64 A VGS = 10 V; Tmb = 25 °C; see Figure 1 - 91 A - 336 A IDM peak drain current tp ≤ 10 µs; pulsed; Tmb = 25 °C; see Figure 3 Ptot total power dissipation Tmb = 25 °C; see Figure 2 - 61 W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Source-drain diode IS source current Tmb = 25 °C - 84 A ISM peak source current tp ≤ 10 µs; pulsed; Tmb = 25 °C - 336 A - 32 mJ Avalanche ruggedness EDS(AL)S non-repetitive VGS = 10 V; Tj(init) = 25 °C; ID = 84 A; Vsup ≤ 30 V; drain-source avalanche RGS = 50 Ω; unclamped energy PSMN5R0-30YL_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 4 January 2010 © NXP B.V. 2010. All rights reserved. 2 of 14 PSMN5R0-30YL NXP Semiconductors N-channel TrenchMOS logic level FET 003aac553 100 ID (A) 03aa16 120 Pder (%) 80 80 60 40 40 20 0 0 0 Fig 1. 50 100 150 200 Tmb (°C) Continuous drain current as a function of mounting base temperature 0 50 100 150 200 Tmb (°C) Fig 2. Normalized total power dissipation as a function of mounting base temperature 003aac588 103 ID (A) 10 μs Limit RDSon = VDS / ID 102 100 μs 10 1 ms DC 1 10-1 10-1 Fig 3. 1 10 10 ms 100 ms VDS (V) 102 Safe operating area; continuous and peak drain currents as a function of drain-source voltage PSMN5R0-30YL_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 4 January 2010 © NXP B.V. 2010. All rights reserved. 3 of 14 PSMN5R0-30YL NXP Semiconductors N-channel TrenchMOS logic level FET 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base see Figure 4 - 1.39 2 K/W 003aac558 10 Zth(j-mb) (K/W) 1 δ = 0.5 0.2 0.1 10-1 δ= P 0.05 tp T 0.02 t tp single shot T 10-2 10-6 Fig 4. 10-5 10-4 10-3 10-2 10-1 tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration PSMN5R0-30YL_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 4 January 2010 © NXP B.V. 2010. All rights reserved. 4 of 14 PSMN5R0-30YL NXP Semiconductors N-channel TrenchMOS logic level FET 6. Characteristics Table 6. Symbol Characteristics Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS VGS(th) drain-source breakdown voltage gate-source threshold voltage ID = 20 A; VGS = 0 V; Tj < 25 °C; tav= 100 ns 35 - - V ID = 250 µA; VGS = 0 V; Tj = 25 °C 30 - - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 27 - - V ID = 1 mA; VDS= VGS; Tj = 25 °C; see Figure 11 and 12 1.3 1.7 2.15 V ID = 1 mA; VDS= VGS; Tj = 150 °C; see Figure 12 0.65 - - V ID = 1 mA; VDS= VGS; Tj = -55 °C; see Figure 12 - - 2.45 V - - 1 µA IDSS drain leakage current VDS = 30 V; VGS = 0 V; Tj = 25 °C VDS = 30 V; VGS = 0 V; Tj = 150 °C - - 100 µA IGSS gate leakage current VGS = 16 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = -16 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = 4.5 V; ID = 15 A; Tj = 25 °C - 5.08 6.7 mΩ VGS = 10 V; ID = 15 A; Tj = 150 °C; see Figure 13 - - 8.7 mΩ VGS = 10 V; ID = 15 A; Tj = 25 °C - 3.63 5 mΩ f = 1 MHz - 0.69 1.5 Ω ID = 10 A; VDS = 12 V; VGS = 4.5 V; see Figure 14 - 14.1 - nC ID = 10 A; VDS = 12 V; VGS = 10 V; see Figure 14 and 15 - 29 - nC ID = 0 A; VDS = 0 V; VGS = 10 V - 27 - nC ID = 10 A; VDS = 12 V; VGS = 4.5 V; see Figure 14 and 15 - 4.3 - nC - 2.9 - nC RDSon RG drain-source on-state resistance gate resistance Dynamic characteristics QG(tot) total gate charge QGS gate-source charge QGS(th) pre-threshold gate-source charge QGS(th-pl) post-threshold gate-source charge - 1.4 - nC QGD gate-drain charge - 3.8 - nC VGS(pl) gate-source plateau voltage VDS = 12 V; see Figure 14 and 15 - 2.5 - V Ciss input capacitance - 1760 - pF Coss output capacitance VDS = 12 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 16 - 373 - pF Crss reverse transfer capacitance - 171 - pF td(on) turn-on delay time - 19 - ns tr rise time - 35 - ns td(off) turn-off delay time - 29 - ns tf fall time - 12 - ns PSMN5R0-30YL_3 Product data sheet VDS = 12 V; RL = 0.5 Ω; VGS = 4.5 V; RG(ext) = 4.7 Ω All information provided in this document is subject to legal disclaimers. Rev. 03 — 4 January 2010 © NXP B.V. 2010. All rights reserved. 5 of 14 PSMN5R0-30YL NXP Semiconductors N-channel TrenchMOS logic level FET Table 6. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; see Figure 17 - 0.84 1.2 V trr reverse recovery time 30 - ns recovered charge IS = 20 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 20 V - Qr - 21 - nC [1] Tested to JEDEC standards where applicable. 003aac548 120 ID 10 (A) 4.5 100 003aac550 10 RDSon (mΩ) VGS (V) = 3.2 V 8 80 VGS (V) = 3.2 60 3 40 2.8 6 4.5 10 4 2.6 20 2 2.4 2.2 0 0 0 Fig 5. 2 4 6 8 0 10 VDS (V) Output characteristics: drain current as a function of drain-source voltage; typical values Fig 6. 003aac552 80 20 40 ID (A) Drain-source on-state resistance as a function of drain current; typical values 003aac555 80 gfs (S) ID (A) 60 70 60 60 40 50 20 Tj = 150 °C 40 25 °C 0 0 Fig 7. 1 2 3 Transfer characteristics: drain current as a function of gate-source voltage; typical values PSMN5R0-30YL_3 Product data sheet 30 VGS (V) 4 0 Fig 8. 10 20 30 ID (A) 40 Forward transconductance as a function of drain current; typical values All information provided in this document is subject to legal disclaimers. Rev. 03 — 4 January 2010 © NXP B.V. 2010. All rights reserved. 6 of 14 PSMN5R0-30YL NXP Semiconductors N-channel TrenchMOS logic level FET 003aac556 3000 Ciss 003aac549 7 RDSon (mΩ) C (pF) 6 2000 Crss 5 1000 4 0 0 Fig 9. 2 4 6 8 VGS (V) 10 Input and reverse transfer capacitances as a function of gate-source voltage; typical values 003aab271 10-1 ID (A) 10-2 3 2 4 6 8 VGS (V) 10 Fig 10. Drain-source on-state resistance as a function of gate-source voltage; typical values 003a a c337 3 VGS (th) (V) min typ max max 2 10-3 typ 10-4 min 1 10-5 10-6 0 1 2 VGS (V) 3 Fig 11. Sub-threshold drain current as a function of gate-source voltage PSMN5R0-30YL_3 Product data sheet 0 -60 0 60 120 Tj (°C) 180 Fig 12. Gate-source threshold voltage as a function of junction temperature All information provided in this document is subject to legal disclaimers. Rev. 03 — 4 January 2010 © NXP B.V. 2010. All rights reserved. 7 of 14 PSMN5R0-30YL NXP Semiconductors N-channel TrenchMOS logic level FET 03aa27 2 VDS a ID 1.5 VGS(pl) VGS(th) 1 VGS QGS1 0.5 QGS2 QGS QGD QG(tot) 003aaa508 0 −60 0 60 120 Tj (°C) 180 Fig 13. Normalized drain-source on-state resistance factor as a function of junction temperature 003aac551 10 VGS (V) Fig 14. Gate charge waveform definitions 003aac557 2500 C (pF) Ciss 2000 8 VDS = 12 (V) VDS = 19 (V) 6 1500 4 1000 2 500 Coss Crss 0 0 10 20 30 Q (nC) 40 G Fig 15. Gate-source voltage as a function of gate charge; typical values PSMN5R0-30YL_3 Product data sheet 0 10-1 1 10 VDS (V) 102 Fig 16. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values All information provided in this document is subject to legal disclaimers. Rev. 03 — 4 January 2010 © NXP B.V. 2010. All rights reserved. 8 of 14 PSMN5R0-30YL NXP Semiconductors N-channel TrenchMOS logic level FET 003aac554 80 IS (A) 60 40 Tj = 150 °C 20 25 °C 0 0.0 0.2 0.4 0.6 0.8 1.0 VSD (V) Fig 17. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values PSMN5R0-30YL_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 4 January 2010 © NXP B.V. 2010. All rights reserved. 9 of 14 PSMN5R0-30YL NXP Semiconductors N-channel TrenchMOS logic level FET 7. Package outline Plastic single-ended surface-mounted package (LFPAK); 4 leads A2 A E SOT669 C c2 b2 E1 b3 L1 mounting base b4 D1 D H L2 1 2 3 e 4 w M A b 1/2 X c e A (A 3) A1 C θ L detail X y C 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) A UNIT A1 A2 A3 b b2 1.20 0.15 1.10 0.50 4.41 0.25 1.01 0.00 0.95 0.35 3.62 mm b3 b4 2.2 2.0 0.9 0.7 c D (1) c2 D1(1) E(1) E1(1) max 0.25 0.30 4.10 4.20 0.19 0.24 3.80 5.0 4.8 3.3 3.1 e H L L1 L2 w y θ 1.27 6.2 5.8 0.85 0.40 1.3 0.8 1.3 0.8 0.25 0.1 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT669 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-10-13 06-03-16 MO-235 Fig 18. Package outline SOT669 (LFPAK) PSMN5R0-30YL_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 4 January 2010 © NXP B.V. 2010. All rights reserved. 10 of 14 PSMN5R0-30YL NXP Semiconductors N-channel TrenchMOS logic level FET 8. Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes PSMN5R0-30YL_3 20100104 Product data sheet - PSMN5R0-30YL_2 Modifications: • Various changes to content. PSMN5R0-30YL_2 20090105 Product data sheet - PSMN5R0-30YL_1 PSMN5R0-30YL_1 20080910 Preliminary data sheet - - PSMN5R0-30YL_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 4 January 2010 © NXP B.V. 2010. All rights reserved. 11 of 14 PSMN5R0-30YL NXP Semiconductors N-channel TrenchMOS logic level FET 9. Legal information 9.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URLhttp://www.nxp.com. 9.2 Definitions Draft— The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet— A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification— The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 9.3 Suitability for use— NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications— Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Quick reference data— The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Disclaimers Limited warranty and liability— Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with theTerms and conditions of commercial saleof NXP Semiconductors. Right to make changes— NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. PSMN5R0-30YL_3 Product data sheet Limiting values— Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale— NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published athttp://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license— Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 03 — 4 January 2010 © NXP B.V. 2010. All rights reserved. 12 of 14 PSMN5R0-30YL NXP Semiconductors N-channel TrenchMOS logic level FET Export control— This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Non-automotive qualified products— Unless the data sheet of an NXP Semiconductors product expressly states that the product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS— is a trademark of NXP B.V. 10. Contact information For more information, please visit:http://www.nxp.com For sales office addresses, please send an email to:[email protected] PSMN5R0-30YL_3 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 03 — 4 January 2010 © NXP B.V. 2010. All rights reserved. 13 of 14 PSMN5R0-30YL NXP Semiconductors N-channel TrenchMOS logic level FET 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2 Thermal characteristics . . . . . . . . . . . . . . . . . . .4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . .12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Contact information. . . . . . . . . . . . . . . . . . . . . .13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 4 January 2010 Document identifier: PSMN5R0-30YL_3