INFINEON TC1910

Da ta S he et , V 1. 0, O ct . 20 03
T C 1 91 0
3 2 - B i t S i n g le - C h i p M ic r o c o n t r o l l e r
M i c ro c o n t ro l l e rs
N e v e r
s t o p
t h i n k i n g .
Edition 2003-10
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 2003.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
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circuits, descriptions and charts stated herein.
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Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
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list).
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approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
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devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Da ta S he et , V 1. 0, O ct . 20 03
T C 1 91 0
3 2 - B i t S i n g le - C h i p M ic r o c o n t r o l l e r
M i c ro c o n t ro l l e rs
N e v e r
s t o p
t h i n k i n g .
TC1910
PRELIMINARY
Revision History:
2003-10
V 1.0
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TC1910
PRELIMINARY
TC1910 Features
The TC1910 offers a 32 bit TriCore based microcontroller/DSP, which is mainly designed
for automotive telematics applications. Due to its high integration, this microcontroller/
DSP offers high system performance at minimized cost. Typical telematics functions
processed by RISC-, DSP- and speech- (CODEC) modules are now combined in one
component. This combination of dedicated speech peripherals (CODEC) and standard
peripherals (SSC/SPI, ASC and IIC), makes this microcontroller/DSP the engine tailored
for a wide variety of telematics applications such as navigation, emergency call, speech
interface or communication interface.
• TriCore CPU/DSP with 4-Stage Pipeline:
– 66 MHz max. CPU clock frequency, 50 MHz max. FPI Bus clock frequency.
– 32-bit super-scalar TriCore main CPU
– 4-GByte unified memory space support
– Fast context-switching
– Dual 16 x 16 Multiply-accumulate (MAC) unit
– 64-bit Local Memory Bus (LMB)
– 32-bit Flexible Peripheral Interface Bus (FPI)
– 32-bit wide External Bus Unit (EBU)
• On-chip memories:
– 24 KByte Code Scratch-Pad RAM (CSRAM)
– 8 KByte Instruction Cache (ICACHE)
– 24 KByte Data Scratch-Pad RAM (DSRAM)
– 8 KByte Data Cache (DCACHE)
– 64 KByte fast LMB SRAM
– 16 KByte FPI SRAM (of which 8 KByte Stand-By SRAM)
• Product Specific Peripherals:
– 14-bit double CODEC with flexible sample rates and FIFO support
– 8 External Interrupt Inputs
• Standard Peripherals:
– 2 x asynchronous serial interface (ASC) with IrDa-support
– 1 SPI-compatible synchronous serial interface
– IIC module
– 3 x 32 bit timer
• General Peripherals:
– Real time clock (RTC)
– Watchdog timer (WDT)
• Clock Generation Unit with PLL
• Debug Support: OCDS Level 1 with JTAG interface
• Dual voltage supply (1.8V core, 3.3V I/O)
• Power saving features
• -40°C to +85°C temperature range
• LBGA-208 package
Data Sheet
1
V 1.0, 2003-10
TC1910
PRELIMINARY
Block Diagram.
LFI
Bridge
SRA M
6 4 kB
E BU
C O DE C
(IIS)
6 4 -b it L o ca l M e m o ry B u s (L M B )
IIC
G P TU
PM U
24KB
CSRAM
8KB
IC A C H E
Port
C ontrol
TriCore
(T C 1 .3 )
DM U
24KB
D SRAM
8KB
DCACHE
AS C0
AS C1
CPS
O CDS
D ebug/
JTA G
S SC
3 2-b it F lexible P erip he ra l In te rface (F P I)B u s
S RAM
1 6 kB
R TC
STM
S CU
TC1910
Figure 1
TC1910 Device Block Diagram
Target applications
• Bluetooth gateway (host for BT stack e.g. for Handsfree with EC/NR or remote
diagnostics)
• Stand-alone speech Human Machine Interface
• Basic communication gateway
• Digital Audio processing (MP3 player, shock proof controller etc.)
Data Sheet
2
V 1.0, 2003-10
TC1910
PRELIMINARY
Logic Symbol
PLL_CTRL
TE S T
CLKOU T
HDRST
PORST
G P IO /E X Ix,
C o d ec B yp ass
P o rt 0
8 -b it
G P IO
P o rt 1
8 -b it
IIC, SSC
ASC0
P o rt 2
1 6 -b it
ASC1
G P TU
P o rt 3
1 6 -b it
G e n e ra l
C o n tro l
NMI
BYPASS
XTAL1
XTAL2
10
XTAL3
XTAL4
VD D O S C 1
VS S O S C 1
VD D O S C 2
VS S O S C 2
VD D P L L
C O D E C 0 /1
O scilla to rs
PLL
83
E xte rn a l B u s
TC1910
VS S P L L
VD D
VD D P
VD D S B
O C D S /JT A G
C o n tro l
D ig ita l C ircu itry
P o w er S u pp ly
VS S
8
VD D _ C O D 0
VS S _ C O D 0
CODEC
A n a lo g P o w e r
S u p p ly
VD D _ C O D 1
VS S _ C O D 1
V R E F_ C O D
VG N D _ C O D
Figure 2
Data Sheet
TC1910 Device Logic Symbol
3
V 1.0, 2003-10
TC1910
PRELIMINARY
Pin Configuration
1
2
3
4
A
A D 2 0 A D 26 A D 28 A D 2 9
B
A D 1 7 A D 25 A D 27 A D 3 0
C
A D 1 3 A D 23 A D 24 A D 3 1
D
AD9
E
AD8
A D 18 A D 16 A D 1 9
F
AD7
A D 15 A D 14 A D 1 2
G
AD5
A D 11 A D 10
H
AD2
5
11
12
13
14
15
16
V D D_
VSSA_
CLK
OU T
P 2 .3
P 2 .0
C O D 0 /1
BY
PASS
NMI
C O D 0 /1
A
A I1 -
A O 1+
A O 0- H R S T E X IN 4
P 2 .5
P 3 .15
B
TM_
T M _ V S S_ V A GN D _
A I1+
C T R L1 X T A L 4 C T R L 0 G U A R D C O D
A O 0+
CODE PORS SSC_
C _ D IS
T
M TSR
IIC _
SDA
E X IN 7
C
S S C _ A S C 0 _ A S C 1_
S C LK
RX
TX
D
V DD _
6
7
X T A L 1 X T A L2
R TC
V S SA
_32K
A D 21 A D 22
VDD_
PW R
AD4
AD3
V S S_
V DD _
PL L
P LL
P LL
P LL
A I0-
10
GU A RD
V D D _ P LL C T
V A RE F_
A I0 +
AO1- CE XT
O S C I R L _A 0
CO D
AD6
AD0
AD1
K
BF
CLK0
A22
L
A 17
A18
A16
A 13
M
A 15
A14
A12
A 11
N
A 10
A9
A8
VDD_
P
A7
A6
A5
A1
R
A4
A3
A0
RD
BC1
T
A2
CAS
BC3
BC2
1
2
3
4
P 2.1
P 2.2
E X IN 6 P 3 .10
G
V D D_
GND
P W R2
VDD_
VSS_
V SS _
HS5
PW R
GND
GND
G P T U . G P T U . G P T U . A S C 1_
4
5
7
RX
H
VSS_
V SS _
HS4
GND
GND
GPT U . SC AN G PTU . G PTU .
MODE
0
6
3
J
GPTU . GPTU .
2
1
K
V D D S B E X IN 3 S C L K M U T E 0
L
E X IN 0 E X IN 1 E X IN 2
M
V D D_
HS14 HS13
LR C K M U T E 1
P W R2
P 1.7
BC0
F
V SS _
PW R2
RAS
E X IN 5
P 2 .4
GND
VDD_
A 19
P 2.9
E
VSS_
H S 15
A 21
P 2.8
P 3 .11
PW R2
C S 1 C S G LB A D V
H S 11
HS7
HS0
V DD _
P 1.4
P 1 .5
P 1 .6
N
PWR
CS2
BAA
CKE
H S 10
HS6
BRK
OUT
TMS
P 1.0
P 1 .2
P 1 .3
P
CS4
CS0
CS
EMU
M R /W
ALE
HS8
HS2
B RK
IN
TD O
TC K
P 1 .1
R
CS5
CS3
W A IT
CS
CM
O V L D E L A Y H S 12
HS9
HS3
HS1 OCDSE
TD I
TR ST
T
5
6
7
11
12
15
16
R D /W R C S 6
8
9
T O P V IE W
Data Sheet
PWR
VDD_
PW R
Figure 3
V DD _
S S C _ A S C 0 _ IIC _
M RST TX
SCL
EBU
CLK
A20
9
V D DP _ V SS P _ V D D_
XTAL3 VDDR
J
A23
8
10
13
14
LBG A 208
TC1910 Pinning
4
V 1.0, 2003-10
TC1910
PRELIMINARY
Pin List
Table 0-1
Symbol
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
Data Sheet
Pin Definitions and Functions
BGA
BALL
H4
J2
H1
H3
H2
G1
G4
F1
E1
D1
G3
G2
F4
C1
F3
F2
E3
B1
E2
E4
A1
D2
D3
C2
C3
B2
A2
B3
A3
A4
B4
C4
In/
Out1)
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
Functions
External Bus Unit Interface
external address/data bus (multiplexed bus mode) or
data bus (demultiplexed bus mode) for the EBU:
AD0
Address/data bus / Data bus line 0
AD1
Address/data bus / Data bus line 1
AD2
Address/data bus / Data bus line 2
AD3
Address/data bus / Data bus line 3
AD4
Address/data bus / Data bus line 4
AD5
Address/data bus / Data bus line 5
AD6
Address/data bus / Data bus line 6
AD7
Address/data bus / Data bus line 7
AD8
Address/data bus / Data bus line 8
AD9
Address/data bus / Data bus line 9
AD10
Address/data bus / Data bus line 10
AD11
Address/data bus / Data bus line 11
AD12
Address/data bus / Data bus line 12
AD13
Address/data bus / Data bus line 13
AD14
Address/data bus / Data bus line 14
AD15
Address/data bus / Data bus line 15
AD16
Address/data bus / Data bus line 16
AD17
Address/data bus / Data bus line 17
AD18
Address/data bus / Data bus line 18
AD19
Address/data bus / Data bus line 19
AD20
Address/data bus / Data bus line 20
AD21
Address/data bus / Data bus line 21
AD22
Address/data bus / Data bus line 22
AD23
Address/data bus / Data bus line 23
AD24
Address/data bus / Data bus line 24
AD25
Address/data bus / Data bus line 25
AD26
Address/data bus / Data bus line 26
AD27
Address/data bus / Data bus line 27
AD28
Address/data bus / Data bus line 28
AD29
Address/data bus / Data bus line 29
AD30
Address/data bus / Data bus line 30
AD31
Address/data bus / Data bus line 31
5
V 1.0, 2003-10
TC1910
PRELIMINARY
Table 0-1
Symbol
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
CS0
CS1
CS2
CS3
CS4
CS5
CS6
CSEMU
CSOVL
Data Sheet
Pin Definitions and Functions
BGA
BALL
R3
P4
T1
R2
R1
P3
P2
P1
N3
N2
N1
M4
M3
L4
M2
M1
L3
L1
L2
K4
K3
J4
K2
J3
R7
N7
P7
T6
R6
T5
P6
R8
T8
In/
Out1)
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
I/O,s
O,u
O,u
O,u
O,u
O,u
O,u
O,u
O,u
O,u
Functions
External Bus Unit Interface (continued)
external address bus for the EBU or chip select
output lines.
A0
Address bus line 0
A1
Address bus line 1
A2
Address bus line 2
A3
Address bus line 3
A4
Address bus line 4
A5
Address bus line 5
A6
Address bus line 6
A7
Address bus line 7
A8
Address bus line 8
A9
Address bus line 9
A10
Address bus line 10
A11
Address bus line 11
A12
Address bus line 12
A13
Address bus line 13
A14
Address bus line 14
A15
Address bus line 15
A16
Address bus line 16
A17
Address bus line 17
A18
Address bus line 18
A19
Address bus line 19
A20
Address bus line 20
A21
Address bus line 21
A22
Address bus line 22
A23
Address bus line 23
CS0
Chip select output 0
CS1
Chip select output 1
CS2
Chip select output 2
CS3
Chip select output 3
CS4
Chip select output 4
CS5
Chip select output 5
CS6
Chip select output 6
CSEMU
Chip select for emulator region
CSOVL
Chip select for emulator overlay
memory
6
V 1.0, 2003-10
TC1910
PRELIMINARY
Table 0-1
Symbol
RD
RD/WR
ALE
ADV
BC0
BC1
BC2
BC3
WAIT
BAA
EBUCLK
BFCLK0
CSGLB
CMDELAY
MR/W
CKE
RAS
CAS
Pin Definitions and Functions
BGA
BALL
R4
P5
R10
N9
N6
R5
T4
T3
T7
P8
J1
K1
N8
T9
R9
P9
N5
T2
In/
Out1)
I/O,u
I/O,u
O,d
O,u
I/O,u
I/O,u
I/O,u
I/O,u
I/O,u
O,u
O,u
O,u
O,u
I,u
O,u
O,u
O,u
O,u
P0
Functions
External Bus Unit Interface (continued)
control bus for the EBU control lines.
RD
Read control line
RD/WR
Write control line
ALE
Address latch enable
ADV
Address valid output
Byte control line 0
BC0
BC1
Byte control line 1
BC2
Byte control line 2
BC3
Byte control line 3
Wait input
WAIT
BAA
Burst address advance output
EBUCLK
External Bus Clock
BFCLK0
Additional clock
CSGLB
Chip Select Global
CMDELAY Command Delay
MR/W
Motorola-style Read/Write
CKE
Clock Enable
RAS
Row Address Strobe
CAS
Column Address Strobe
Port 0
Port 0 is an 8-bit general purpose I/O port, overlaid
with codec digital signals and external interrupt
inputs (P0.[3:0]).
P0.0
P0.1
P0.2
M14
M15
M16
I/O
I/O
I/O
EXI0IN
EXI1IN
EXI2IN
P0.3
P0.4
P0.5
P0.6
P0.7
L14
L15
K13
L16
K14
I/O
I/O
I/O
I/O
I/O
EXI3IN
SCLK
LRCK
MUTE0
MUTE1
Data Sheet
External Interrupt Input 0
External Interrupt Input 1 or DATA_IN
External Interrupt Input 2 or
DATA_OUT
External Interrupt Input 3 or MCLK
7
V 1.0, 2003-10
TC1910
PRELIMINARY
Table 0-1
Symbol
Pin Definitions and Functions
BGA
BALL
In/
Out1)
Port 1
Port 1 is a 8-bit bidirectional General Purpose I/O
port
P1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P14
R16
P15
P16
N14
N15
N16
M13
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Data Sheet
GPIO only
GPIO only
GPIO only
GPIO only
GPIO only
GPIO only
GPIO only
GPIO only
Port 2
Port 2 is a 16-bit bidirectional general purpose I/O
port and input/output for serial interfaces (IIC, ASC0,
SSC)
P2
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P2.8
P2.9
P2.10
P2.11
P2.12
P2.13
P2.14
P2.15
Functions
A16
G13
G14
A15
F15
B15
E15
C15
F13
F14
D15
E14
D14
E13
C14
B14
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO only
GPIO only
GPIO only
GPIO only
GPIO only
GPIO only
SCL
IIC Serial Port Clock
SDA
IIC Serial Port Data
Open Drain GPIO
Open Drain GPIO
RXD0
ASC0 receiver input/output
TXD0
ASC0 transmitter output
SCLK
SSC clock line
MRST
SSC Master Receive / Slave Transmit
MTSR
SSC Master Transmit / Slave Receive
GPIO/EXI4IN/PLL_CLC.LOCK Monitoring of the
PLL_CLC.LOCK
8
V 1.0, 2003-10
TC1910
PRELIMINARY
Table 0-1
Symbol
Pin Definitions and Functions
BGA
BALL
In/
Out1)
Port 3
Port 3 is a 16-bit bidirectional general purpose I/O
port which is also used as input/output for serial
interfaces (ASC1) and timer (GPTU)
P3
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3.8
P3.9
P3.10
P3.11
P3.12
P3.13
P3.14
P3.15
J13
K16
K15
J16
H13
H14
J15
H15
H16
D16
G16
E16
F16
G15
C16
B16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Data Sheet
GPTU.0
GPTU I/O line 0
GPTU.1
GPTU I/O line 1
GPTU.2
GPTU I/O line 2
GPTU.3
GPTU I/O line 3
GPTU.4
GPTU I/O line 4
GPTU.5
GPTU I/O line 5
GPTU.6
GPTU I/O line 6
GPTU.7
GPTU I/O line 7
RXD1
ASC1 receiver input/output
TXD1
ASC1 transmitter output
GPIO only
GPIO only / OSCBYP Latch-In Input Pin
EXI5IN/ HWCFG0 Latch-InExternal Interrupt Input 5
EXI6IN/ HWCFG1 Latch-InExternal Interrupt Input 6
EXI7IN/ HWCFG2 Latch-InExternal Interrupt Input 7
GPIO only
CODEC
CODEC
AI0+
AI0AO0+
AO0AI1+
AI1AO1+
AO1CEXT
CODEC_DIS
Functions
D9
B9
C11
B12
C10
B10
B11
D11
D12
C12
I
I
O
O
I
I
O
O
I
I
CODEC 0 Non-Inverting Input
CODEC 0 Inverting Input
CODEC 0 Non-Inverting Output
CODEC 0 Inverting Output
CODEC 1 Non-Inverting Input
CODEC 1 Inverting Input
CODEC 1 Non-Inverting Output
CODEC 1 Inverting Output
Codec External Clock Input
Codec Disable (power saving)
9
V 1.0, 2003-10
TC1910
PRELIMINARY
Table 0-1
Pin Definitions and Functions
Symbol
BGA
BALL
In/
Out1)
DEBUG
Functions
DEBUG (OCDS/JTAG Control)
TRST
TCK
TDI
TDO
TMS
OCDSE
BRKIN
BRKOUT
T16
R15
T15
R14
P13
T14
R13
P12
I,d
I,u
I,u
O
I,u
I,u
I,u
O
Reset/module enable
JTAG clock input
Serial data input
Serial data output
State machine control signal
OCDS enable input
OCDS break input
OCDS break output
Test
SCAN_MODE
PLLCTRL_AO
TM_CTRL0
TM_CTRL1
J14
D8
C7
C5
I
I
I
I
Test Pins
Scan Mode
Control current of different analog stages
Test Mode Control 0
Test Mode Control 1
HS0
HS1
HS2
HS3
HS4
HS5
HS6
HS7
HS8
HS9
HS10
HS11
HS12
HS13
HS14
HS15
N12
T13
R12
T12
J10
H10
P11
N11
R11
T11
P10
N10
T10
K9
K8
J7
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Reserved Internal Test and Heat Sink Pins.
Must be routed as isolated pads on the PCB.
Heat Sink 0
Heat Sink 1
Heat Sink 2
Heat Sink 3
Heat Sink 4
Heat Sink 5
Heat Sink 6
Heat Sink 7
Heat Sink 8
Heat Sink 9
Heat Sink 10
Heat Sink 11
Heat Sink 12
Heat Sink 13
Heat Sink 14
Heat Sink 15
BYPASS
A12
I,d
PLL Bypass Control Input
NMI
A13
I,u
Non-Maskable Interrupt Input
HRST
B13
I/O,u
Bidirectional Hardware Reset
Reserved Pins
Data Sheet
10
V 1.0, 2003-10
TC1910
PRELIMINARY
Table 0-1
Pin Definitions and Functions
Symbol
BGA
BALL
In/
Out1)
Functions
PORST
C13
I,u
Power-on Reset Input (must be active during power
up)
CLKOUT
A14
O
CPU Clock Output
XTAL1
XTAL2
A6
A7
I
O
PLL/Oscillator Input/Output
XTAL3
XTAL4
D5
C6
I
O
Real Time Clock Oscillator input/output (32 KHz)
VAREF_COD
D10
-
Codec 0,1 Reference Voltage
VAGND_COD
C9
-
Codec 0,1 Reference Ground
VDD_COD0/1
A10
-
Codec Pad and Analog Power Supply (3.3V)
VSSA_COD0/1
A11
-
Codec Pad and Analog Ground
VDD_GUARD
B8
-
Guard Ring Supply (1.8V)
VSS_GUARD
C8
-
Guard Ring Ground (1.8V)
VDD_OSCI
D7
-
Main Oscilator Power Supply (1.8V)
VDD_RTC
A5
-
RTC Oscilator Core Supply (1.8V)
VSSA_32K
B5
-
RTC and Main Osc. Core Ground (1.8V)
VDDP_PLL
B6
-
RTC and Main Osc. Supply (3.3V)
VSSP_PLL
B7
-
RTC and Main Osc. Ground (3.3V)
VDDPLL
A9
-
PLL Supply (1.8V)
VSSPLL
A8
-
PLL Ground (1.8V)
VDDR
D6
-
SRAM Power Supply (1.8V)
VDDSB
L13
-
SRAM Stand-By Power Supply (1.8V)
VDD_PWR
D4
D13
H7
N4
N13
-
3.3V Power Supply
VDD_PWR2
G7
G10
K7
K10
-
1.8V Power Supply
Data Sheet
11
V 1.0, 2003-10
TC1910
PRELIMINARY
Table 0-1
Pin Definitions and Functions
Symbol
BGA
BALL
In/
Out1)
Functions
VSS_GND
G8
G9
H8
H9
J8
J9
-
Digital Power Ground
1)
The notification ’,u’ after the input/output type defines an internal pull-up resistor. An internal pull-down resistor
is indicated by ’,d’. For the lines AD[31:0] and A[23:0], the type of the pull device can be selected ’s’.
Data Sheet
12
V 1.0, 2003-10
TC1910
PRELIMINARY
System Architecture and Control
32-Bit TriCore CPU
•
•
•
•
•
•
•
•
•
•
32-bit architecture with 4-GByte unified data, program and input/output address space
Fast automatic context-switch
Dual 16 x 16 Multiply-accumulate (MAC) unit
Saturating integer arithmetic
Register based design with multiple variable register banks
Bit handling
Packed data operations
Zero overhead loop
Precise exceptions
Flexible power management
Instruction Set with High Efficiency:
• 16/32-bit instructions for reduced code size
• Little endian byte ordering with support for big and little endian byte ordering at bus
interface
• Boolean, array of bits, character, signed and unsigned integer, integer with saturation,
signed fraction, double word integers and IEEE-754 single precision floating-point
data types
• Bit, 8-bit byte, 16-bit half word, 32-bit word and 64-bit double word data formats
• Powerful instruction set
• Flexible and efficient addressing mode for high code density
Data Sheet
13
V 1.0, 2003-10
TC1910
PRELIMINARY
On-chip Code Memories
Local Memory Bus Memory (LMBRAM):
Address range of the 64 KByte Local Memory Bus Memory:
• C000 0000H - C000 FFFFH (in segment 12 for cached operation)
• E800 0000H - E800 FFFFH (in segment 14 for non-cached operation)
PMU Scratch-Pad SRAM (CSRAM):
The Program Memory Unit (PMU) memory consists of 24-KByte Code Scratchpad RAM
(CSRAM) and 8-KByte Instruction Cache (ICACHE).
Address range of the CSRAM:
• D400 0000H - D400 5FFFH
On-chip Data Memories
DMU Scratch-Pad SRAM (DSRAM):
The Data Memory Unit (DMU) memory consists of 24-KByte Data Scratchpad RAM
(DSRAM) and 8-KByte Data Cache (DCACHE).
Address range of the DSRAM:
• D000 0000H - D000 5FFFH
FPI-Bus Data Memory (FPIDRAM):
The FPI-Bus Data Memory (FPIDRAM) is a 16-KByte static RAM located on the FPIBus. It contains two parts: FPIDRAM0 and FPIDRAM1. One half of it (FPIDRAM1) can
be used for standby power operation.
Address range of the FPI Data Memory:
• 9FFF 8000H - 9FFF BFFFH (in segment 9 for cached operation)
• BFFF 8000H - BFFF BFFFH (in segment 11 for non-cached operation)
Data Sheet
14
V 1.0, 2003-10
TC1910
PRELIMINARY
System Control Unit (SCU)
The System Control Unit of the TC1910 basically handles all system control tasks. All
these system functions are tightly coupled and therefore they are handled physically by
one unit, the SCU. The system tasks of the SCU are:
•
•
•
•
•
•
•
Clock Generation and Control
Reset control
Power Management control and wake-up
Watchdog timer
Device identification
Standby SRAM control
External interrupt capability (8 sources)
System timer (STM)
The System Timer is designed for global system timing applications requiring both high
precision and long range. It is used by the CPU for software operating system issues.
Features:
•
•
•
•
•
•
Free-running 56-bit counter
All 56 bits can be read synchronously
Different 32-bit portions of the 56-bit counter can be read synchronously
Driven by clock, f STM (normally identical with the system clock).
Counting begins at power-on reset
Continuous operation is not affected by any reset condition except power-on reset
External Bus Interface (EBU_LMB)
EBU_LMB is connected to the Local Memory Bus (LMB) of the TC1910 and also to the
FPI Bus. EBU_LMB is always a slave on the LMB and a master/slave on the FPI bus.
Any LMB masters thus can access external memories or devices through EBU_LMB.
Currently the maximum length of the bursts are according to the size of program and
data cache lines, i.e. 8 x 32-bit words. Single transfers (non-burst) are supported for 8bit, 16-bit and 32-bit wide access.
Data Sheet
15
V 1.0, 2003-10
TC1910
PRELIMINARY
E B U _L M B
XBC
External Bus 32-bit
L M B B us 64 -bit
DME
F P I B us 32 -bit
XM I
SDRAM
B uffer
S lo w e r
D evices
50 M H z
E xterna l
M aster
E xte rn al B us U nit
E B U L 30 4 5 _L
Figure 4
EBU_LMB block diagram
Features supported in EBU_LMB:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Local Memory Bus (LMB 64-bit) support.
External bus frequency: LMB frequency = 1:1 or 1:2 or 1:4.
Highly programmable access parameters.
Intel-style and Motorola-style peripheral/device support.
SDRAM support (burst access, multibanking, precharge, refresh).
16- and 32-bit SDRAM data bus and support of 64, 128 and 256MBit devices.
Burst flash support.
Multiplexed access (address & data on the same bus) when DRAM is not present on
the External Bus.
Data Buffering: Code Prefetch Buffer, Read/Write Buffer.
External master arbitration (compatible to C166 and other TriCore devices).
8 programmable address regions (1 dedicated for emulator).
Little-Endian and Big-Endian support.
CSglb signal, dedicated pin, bit programmable to combine one or more CS lines, for
buffer control.
RMW signal reflecting a read-modify-write action.
Signal for controlling data flow of slow-memory buffer.
Slave unit for external (off-chip) master to access devices on the FPI bus.
Master unit for FPI master to access external (off-chip) devices.
Data Mover Engine.
Data Sheet
16
V 1.0, 2003-10
TC1910
PRELIMINARY
Interrupt System
• Flexible interrupt prioritizing scheme with 256 interrupt priority levels
• Fast interrupt response
C P U In te rru p t
A rb itra tio n B u s
M o d u le A
M o d u le
K e rn e l
n S e rvice
R e q u e st
Nodes
M a in In te rru p t C o n tro l
CPU
In te rru p t
C o n tro l
U n it
(IC U )
M o d u le B
M o d u le
K e rn e l
n S e rvice
R e q u e st
Nodes
4 S e rvice
R e q u e st
Nodes
CPU
C o re
4
M o d u le C
M o d u le
K e rn e l
Figure 5
Data Sheet
n S e rvice
R e q u e st
Nodes
Block Diagram Interrupt System
17
V 1.0, 2003-10
TC1910
PRELIMINARY
FPI-Bus
The Flexible Peripheral Interconnect Bus is designed with the requirements of highperformance Systems-on-Chip in mind.
Key Features:
•
•
•
•
•
•
•
•
•
•
Core independent
Multi-master capability
Demultiplexed operation
Clock synchronous
Peak transfer rate of up to 200 MBytes/s (@ 50 MHz bus clock)
Address and data bus scalable (32 bit address bus, 32 bit data bus )
8-/16- and 32 bit data transfers
Broad range of transfer types from single to multiple data transfers
Burst transfer capability
EMI and power consumption minimized
LMB-Bus
The Local Memory Bus is a synchronous, pipelined, split bus with variable block size
transfer support. All signals relate to the positive clock edge.
The protocol supports 8,16,32 & 64 bits single beat transactions and variable length 64
bits block transfers.
Key Features:
The LMB provides the following features:
•
•
•
•
•
•
•
Optimized for high speed and high performance
32 bit address, 64 bit data busses
Central simple per cycle arbitration
Slave controlled wait state insertion
Address pipelining (max depth - 2)
Split transactions
Variable block length - 2, 4 or 8 beats of 64 bit data
Data Sheet
18
V 1.0, 2003-10
TC1910
PRELIMINARY
On-Chip Debug System (OCDS)
The TC1910 architecture is supporting OCDS Level 1. This means access to FPI Bus
and the whole FPI address space via the JTAG interface pins.
On-Chip Peripheral Units
The TC1910 offers several on-chip peripheral units such as serial controllers, timer units,
and Codec module. Within the TC1910 all these peripheral units are connected to the
TriCore CPU/system via the FPI (Flexible Peripheral Interconnect) Bus. Several IO lines
on the TC1910 ports are reserved for these peripheral units to communicate with the
external world.
Peripheral Units of the TC1910:
• Three Asynchronous/Synchronous Serial Channels with baudrate generator, parity,
framing and overrun error detection, IrDA mode, FIFO buffers.
• One High Speed Synchronous Serial Channels with programmable data length and
shift direction
• IIC module
• One multi-functional General Purpose Timer Units with three 32-bit timer/counter
• Dual channel Codec interface
• GPIO blocks
Table 1
Peripheral Modules
Module
Address Range
I/O Lines
Interrupt Nodes
Asynchronous
Serial Channel 0
(ASC0)
F000 0A00H F000 0AFFH
RDX0, TDX0
ASC0_TSRC
ASC0_RSRC
ASC0_ESRC
ASC0_TBSRC
Asynchronous
Serial Channel 1
(ASC1)
F000 0B00H F000 0BFFH
RDX1, TDX1
ASC1_TSRC
ASC1_RSRC
ASC1_ESRC
ASC1_TBSRC
Synchronous Serial F000 0800H Channel (SSC)
F000 08FFH
SCLK, MRST,
MTSR
SSC_TSRC
SSC_RSRC
SSC_ESRC
Inter-IC Bus (IIC)
F000 0500H F000 05FFH
SCL,
SDA
IIC_XP0SRC
IIC_XP1SRC
IIC_XP2SRC
Real Time Clock
(RTC)
F000 0100H F000 01FFH
-
RTC_SRC
Data Sheet
19
V 1.0, 2003-10
TC1910
PRELIMINARY
Table 1
Peripheral Modules (cont’d)
Module
Address Range
I/O Lines
Interrupt Nodes
System Timer Unit
(STM)
F000 0300H F000 03FFH
-
-
General Purpose
Timer (GPTU)
F000 0700H F000 07FFH
GPTU
GPTU_SRC0..7
Speech Interface
(Codec)
F000 2400H F000 24FFH
2*2 analog IN,
2*2 analog OUT,
CEXT,
CODEC_DIS
CODEC_SRC0..5
Data Sheet
20
V 1.0, 2003-10
TC1910
PRELIMINARY
Asynchronous/Synchronous Serial Interfaces (ASC 0/1)
The Asynchronous/Synchronous Serial Interface ASC provides serial communication
between the TriCore and other microcontrollers, microprocessors or external
peripherals.
Features:
• Full duplex asynchronous operating modes
– 8- or 9-bit data frames, LSB first
– Parity bit generation/checking
– One or two stop bits
– Baudrate from 3.125 MBaud to 0.74 Baud (@ 50 MHz module clock)
– Multiprocessor mode for automatic address/data byte detection
– Loop-back capability
• Half-duplex 8-bit synchronous operating mode
– Baudrate from 6.25 MBaud to 637 Baud (@ 50 MHz module clock)
• Double buffered transmitter/receiver
• Interrupt generation
– on a transmitter buffer empty condition
– on a transmit last bit of a frame condition
– on a receiver buffer full condition
– on an error condition (frame, parity, overrun error)
• Support for IrDA
• Automatic Baudrate Detection
• 8 Byte FIFO
C lo c k
C on tro l
f hw _c lk
A d d re s s
D e c od e r
Interru p t
C on tro l
RXD
T IR
T B IR
R IR
E IR
A B S TIR
A B D E T IR
ASC
M od u le
(K e rn e l)
TX D
RXD
P o rt
C o n tro l
TX D
M C A 05 2 53
Figure 6
Data Sheet
General Block Diagram of the ASC Interface
21
V 1.0, 2003-10
TC1910
PRELIMINARY
High-Speed Synchronous Serial Interface (SSC)
The High Speed Synchronous Serial Interface SSC provides serial communication
between microcontrollers, microprocessors or external peripherals. The SSC supports
full-duplex and half-duplex synchronous communication up to 25 MBaud (@ 50 MHz
module clock). The serial clock signal can be generated by the SSC itself (master mode)
or be received from an external master (slave mode). Data width, shift direction, clock
polarity and phase are programmable. This allows communication with SPI-compatible
devices. Transmission and reception of data are double-buffered. A 16-bit baud rate
generator provides the SSC with a separate serial clock signal.
Features:
• Master and slave mode operation
– Full-duplex or half-duplex operation
• Flexible data format
– Programmable number of data bits : 2 to 16 bit
– Programmable shift direction : LSB or MSB shift first
– Programmable clock polarity : idle low or high state for the shift clock
– Programmable clock/data phase : data shift with leading or trailing edge of SCLK
• Maximum baudrate: 25 MBaud in Master, 12.5 in Slave mode (@ 50 MHz module
clock)
Interrupt generation
– on a transmitter empty condition
– on a receiver full condition
– on an error condition (receive, phase, baudrate, transmit error)
• Three pin interface
f h w _c lk
A d d re s s
D e c o de r
Slave Master
C lo c k
C on tro l
SSC
M o d ule
(K erne l)
Interru p t
C on tro l
SCLK
E IR
R IR
RXD
M TSR
TXD
RXD
TXD
P o rt
C o n tro l
M RST
S la v e
M a s te r
SCLK
T IR
M C B 04 5 0 5_ m o d
Figure 7
Data Sheet
General Block Diagram of the SSC Interface
22
V 1.0, 2003-10
TC1910
PRELIMINARY
Inter-IC Interface (IIC)
IIC supports a certain protocol to allow devices to communicate directly with each other
via two wires. One line is responsible for clock transfer and synchronization (SCL), the
other is responsible for the data transfer (SDA).
The on-chip IIC Bus module connects the platform buses to other external controllers
and/or peripherals via the two-line serial IIC interface. The IIC Bus module provides
communication at data rates of up to 400 kBit/s and features 7-bit addressing as well as
10-bit addressing. This module is fully compatible to the IIC bus protocol.
The module can operate in three different modes:
Master mode, where the IIC controls the bus transactions and provides the clock signal.
Slave mode, where an external master controls the bus transactions and provides the
clock signal.
Multimaster mode, where several masters can be connected to the bus, i.e. the IIC can
be master or slave.
The on-chip IIC bus module allows efficient communication via the common IIC bus. The
module unloads the CPU of low level tasks like:
•
•
•
•
•
(De)Serialization of bus data.
Generation of start and stop conditions.
Monitoring the bus lines in slave mode.
Evaluation of the device address in slave mode.
Bus access arbitration in multimaster mode.
IIC Features:
•
•
•
•
•
Extended buffer allows up to 4 send/receive data bytes to be stored.
Selectable baud rate generation.
Support of standard 100 kBaud and extended 400 kBaud data rates.
Operation in 7-bit addressing mode or 10-bit addressing mode.
Flexible control via interrupt service routines or by polling.
Data Sheet
23
V 1.0, 2003-10
TC1910
PRELIMINARY
Timer Unit (GPTU)
Figure 8 shows a global view of all functional blocks of the GPTU module.
C lo c k
C on tro l
fG P T U
A d d re s s
D e c od e r
Interru p t
C on tro l
SR0
SR1
SR2
SR3
SR4
SR5
SR6
SR7
G PTU
M od u le
(K e rn e l)
IN 0
IN 1
IN 2
IN 3
IN 4
IN 5
IN 6
IN 7
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
IO 0
IO 1
IO 2
IO 3
P o rt
C o ntro l
IO 4
IO 5
IO 6
IO 7
P 0.0 / G P T 0
P 0.1 / G P T 1
P 0.2 / G P T 2
P 0.3 / G P T 3
P 0.4 / G P T 4
P 0.5 / G P T 5
P 0.6 / G P T 6
P 0 .7 / G P T 7
M C B 0 5 0 52 _ m o d ifie d
Figure 8
General Block Diagram of the GPTU Interface
The GPTU consists of three 32-bit timers designed to solve such application tasks as
event timing, event counting, and event recording. The GPTU communicates with the
external world via eight inputs and eight outputs.
The three timers of the GPTU module T0, T1, and T2, can operate independently from
each other, or can be combined:
General Features:
•
•
•
•
All timers are 32-bit precision timers with a maximum input frequency of fGPTU/2.
Events generated in T0 or T1 can be used to trigger actions in T2
Timer overflow or underflow in T2 can be used to clock either T0 or T1
T0 and T1 can be concatenated to form one 64-bit timer
Features of T0 and T1:
• Each timer has a dedicated 32-bit reload register with automatic reload on overflow
• Timers can be split into individual 8-, 16-, or 24-bit timers with individual reload
registers
• Overflow signals can be selected to generate service requests, pin output signals, and
T2 trigger events
• Two input pins can determine a count option
Data Sheet
24
V 1.0, 2003-10
TC1910
PRELIMINARY
Features of T2:
• Optionally count up or down
• Operating modes:
– Timer
– Counter
– Incremental Interface Mode
• Options:
– External start/stop, one-shot operation, timer clear on external event
– Count direction control through software or an external event
– Two 32-bit reload/capture registers
• Reload modes:
– Reload on overflow or underflow
– Reload on external event: positive transition, negative transition, or both transitions
• Capture modes:
– Capture on external event: positive transition, negative transition, or both
transitions
– Capture and clear timer on external event: positive transition, negative transition, or
both transitions
• Can be split into two 16-bit counter/timers
• Timer count, reload, capture, and trigger functions can be assigned to input pins. T0
and T1 overflow events can also be assigned to these functions.
• Overflow and underflow signals can be used to trigger T0 and/or T1 and to toggle
output pins
• T2 events are freely assignable to the service request nodes.
Real Time Clock Unit RTC
The Real Time Clock (RTC) module is basically an independent timer chain and counts
clock ticks. The base frequency of the RTC can be programmed via a reload counter.
The RTC can work fully asynchronous to the system frequency and is optimized on low
power consumption.
Features:
The RTC serves different purposes:
•
•
•
•
Absolute system clock to determine the current time and date
Cyclic time based interrupt
Alarm interrupt for wake up on a defined time
48-bit timer for long term measurements
Data Sheet
25
V 1.0, 2003-10
TC1910
PRELIMINARY
Codec Interface
The speech A/D and D/A converters (called codec) is designed for telephone and
speech recognition quality. They can be used for microphone / earpiece applications.
The TC1910 configuration implements a dual channel speech codec connected to the
FPI bus.
VDD
VSS
V DD V SS
C O D0
COD0
CO D 1 CO D 1
ch0 n on -inv. inpu t
C lock
C on trol
f pe r
ch0 in v. inp ut
ch0 n on -inv. outp ut
ch0 in v. ou tp ut
A d dre ss
D e co de r
ch1 n on -inv. inpu t
ch1 in v. inp ut
In terrup t
C on trol
SR0
SR1
SR2
SR3
SR4
SR5
CO DEC
M o dule
K e rn el
ch1 n on -inv. outp ut
ch1 in v. ou tp ut
A O 0+
A O 0A I1 +
A I1 A O 1+
A O 1C O D E C _ D IS
external clock inp ut
CEXT
m ute ch ann el 1
COD
A I0 -
clock disab le
m ute ch ann el 0
V RE F
A I0 +
M UTE0
M UTE1
VGND
COD
Figure 9
5
C od ec b ypass
IIS
sig na ls
General Codec Overview
General Purpose I/Os (GPIO)
•
•
•
•
Push/pull output drivers
3.3 Volt operation for GPIO
Programmable pull-up/-down devices at all pins
Optional Open Drain Output Mode
Data Sheet
26
V 1.0, 2003-10
TC1910
PRELIMINARY
ID Register Table
Table 2
List of TC1910 ID registers
Short Name Description
Address
Reset Value
SCU_ID
SCU Identification Register
F000 0008H
0019 C002H
MANID
Manufacturer Identification Register
F000 0070H
0000 1820H
CHIPID
Chip Identification Register
F000 0074H
0000 8902H
RTID
Redesign Tracing Identification Register F000 0078H
0000 0000H
RTC_ID
RTC Module Identification Register
F000 0108H
0000 5A04H
BCU_ID
BCU Identification Register
F000 0208H
0000 6A06H
STM_ID
System Timer Module Identification
Register
F000 0308H
0000 C002H
JDP_ID
JTAG/OCDS Module Identification
Register
F000 0408H
0000 6305H
IIC_ID
IIC Module Identification Register
F000 0508H
0000 4604H
GPTU_ID
GPTU Module Identification Register
F000 0708H
0001 C002H
SSC_ID
SSC Module Identification Register
F000 0808H
0000 4503H
ASC0_ID
ASC Module Identification Register
F000 0A08H
0000 44E1H
ASC1_ID
ASC Module Identification Register
F000 0B08H
0000 44E1H
CODEC_ID
Codec Identification Register
F000 2408H
001C C002H
CPS_ID
CPU Module Identification Register
F7E0 FF08H
0015 C004H
CPU_ID
CPU Identification Register
F7E1 FE18H
000A C003H
EBU_ID
EBU_LMB Module Identification
Register
F800 0008H
0014 C003H
DMU_ID
DMU Identification Register
F87F FC08H
0008 C002H
PMU_ID
PMU Module Identification Register
F87F FD08H
000B C002H
LCU_ID
LCU Identification Register
F87F FE08H
000F C003H
LFI_ID
LFI Identification Register
F87F FF08H
000C C003H
Data Sheet
27
V 1.0, 2003-10
TC1910
PRELIMINARY
Power Supply
Figure 10 shows the TC1910 power supply concept, where certain logic modules are
individually supplied with power. In this way, the noise margin is improved in the
especially sensitive modules, like the A/D converter and the CODEC.
V D DA
V D DA
V DD A
V DD A
V D DA
V DD A
V SSA
V SS A
V SSA
V SSA
V SS A
V SSA
M A IN
OSC
RTC
OSC
PLL
(ana log)
ADC
(ana log)
CO DEC 0
(a na lo g)
CODEC 1
(ana log)
V D DP
V SS P
X
V D DP
B atte ry
B acked
S ta nd- B y
S RAM
A LL D IG IT A L C O R E
CO MPO NENTS
V SS P
Y
V D D_SB
V D DR
V SS
Figure 10
Data Sheet
V DD
VDD
V SS
V SS
TC1910 Power Supply Concept
28
V 1.0, 2003-10
TC1910
PRELIMINARY
Power-Up Sequence
During Power-Up reset pin PORST has to be held active until both power supply
voltages have reached at least their minimum values.
During the Power-Up time (rising of the supply voltages from 0 to their regular operating
values) it has to be ensured, that the core VDD power supply reaches its operating value
first, and then the GPIO VDDP power supply. During the rising time of the core voltage it
must be ensured that 0< VDD-VDDP <0.5 V.
During power-down, the core and GPIO power supplies VDD and VDDP respectively,
have to be switched off until all capacitances are discharged to zero, before the next
power-up.
Note: The states of the pins are undefined when only the port voltage VDDP is on.
Data Sheet
29
V 1.0, 2003-10
TC1910
PRELIMINARY
Electrical characteristics
Parameter Interpretation
The parameters listed in the following partly represent the characteristics of the TC1910
and partly its demands on the system. To aid in interpreting the parameters right, when
evaluating them for a design, they are marked in column “Symbol”:
CC (Controller Characteristics):
The logic of the TC1910 will provide signals with the respective characteristics.
SR (System Requirement):
The external system must provide signals with the respective characteristics to the
TC1910.
Data Sheet
30
V 1.0, 2003-10
TC1910
PRELIMINARY
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
min.
Unit Notes
max.
TA
TST
Storage temperature
Junction temperature
TJ
Voltage on I/O Supply pins with VDDP
respect to ground (VSS)
Voltage on Core Supply pins
VDD
with respect to ground (VSS)
VDDPLL
Voltage on PLL Supply pins
with respect to ground (VSS)
Voltage between Oscillator
VDDOSC
Supply Pins and ground (VSS).
Voltage on any pin with respect VIN
to ground (VSS)
-40
85
°C
-65
150
°C
–
125
°C
-0.5
4.2
V
-0.3
2.1
V
-0.3
2.1
V
-0.3
2.1
V
-0.5
4.2
V
Input current on any pin during IOV
overload condition
-10
10
mA
Ambient temperature
Absolute sum of all input
currents at overload condition
ΣIOV
–
|100|
mA
Power dissipation
PDISS
–
1.0
W
under bias
under bias
PLL
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
During absolute maximum rating overload conditions (VIN>VDD or VIN<VSS) the
voltage on VDD pins with respect to ground (VSS) must not exceed the values
defined by the absolute maximum ratings.
Data Sheet
31
V 1.0, 2003-10
TC1910
PRELIMINARY
Package Parameters (P-LBGA-208)
Parameter
Symbol
Limit Values
PDISS
RTHA
Power dissipation
Thermal resistance
Unit Notes
min.
max.
–
1.0
W
–
30
K/W Chip to ambient
–
Operating Conditions
The following operating conditions must not be exceeded in order to ensure correct
operation of the TC1910. All parameters specified in the following sections refer to these
operating conditions, unless otherwise noted.
Parameter
Symbol
Limit Values
min.
Supply voltage
Ground voltage
Input current on any pin
during overload
condition
Unit Notes
max.
VDDP
VDD
VDDPLL
VDDOSC
VSS
3.0
3.61)
V
I/O supply
1.71
1.892)
V
Core supply
1.71
1.89
V
PLL supply
1.71
1.89
V
Oscillator supply
IOV
-5
5
mA
–
|50|
mA
Absolute sum of all input Σ| IOV|
currents at overload
condition
0
V
Ambient temperature
under bias
TA
-40
85
°C
CPU clock
fCPU
CL
–
66
MHz
–
50
pF
External Load
Capacitance
VOV > VDDP + 0.3V
VOV < VSS - 0.3V
1)
Voltage overshoot to 4 V is permissible, provided the pulse duration is less than 100 µs and the cumulated
summary of the pulses does not exceed 1 h
2)
Voltage overshoot to 2 V is permissible, provided the pulse duration is less than 100 µs and the cumulated
summary of the pulses does not exceed 1 h
Data Sheet
32
V 1.0, 2003-10
TC1910
PRELIMINARY
DC Characteristics
GPIO pins
Parameter
Symbol
Limit values
min.
max.
Unit
Test
Conditions
Output low voltage
(strong driver)
VOL
-
1
0.4
V
IOL = 10 mA
IOL = 2.5 mA
Output high voltage
(strong driver)
VOH
2.4
-
V
IOH = - 2.5 mA
Output low voltage
(medium driver)1)
VOL
-
0.4
V
IOL = 1 mA
Output high voltage
(medium driver)1)
VOH
2.4
-
V
IOH = - 1 mA
Output low voltage
(weak driver)1)
VOL
-
0.4
V
IOL = 100 µA
Output high voltage
(weak driver)1)
VOH
2.4
-
V
IOH = - 100 µA
Input low voltage
VIL
-0.3
0.8
V
LVTTL
Input high voltage
VIH
2.0
VDDP+0.3 V
or
3.7V
whatever is
lower
Input leakage current
IOZ1
-
±500
nA
0V< Vin <
VDDP
Pull-up current 2)
|IPUH |
-
1
µA
VOUT = 2.0V
Pull-up current 3)
|IPUL|
20
-
µA
VOUT = 0.8V
Pull-down current
|IPDL|
-
0.8
µA
VOUT = 0.8V
Pull-down current
|IPDH|
20
-
µA
VOUT = 2.0V
CIO
-
10
pF
f = 1MHz @
TA = 25oC
Pin capacitance
1)
1)
Not subject to production test, verified by design/characterization.
2)
The maximum current that may be drawn while the respective signal line remains inactive.
3)
The minimum current that must be drawn in order to drive the respective signal line active.
Data Sheet
33
V 1.0, 2003-10
TC1910
PRELIMINARY
NMI Pin
NMI Pin is an input pin with different Pull-Up characteristics than other pins. The related
characteristics are given in the following table
Parameter
Symbol
Limit values
Unit
Test
Conditions
min.
max.
Max. current allowed
|IPUH |
through the Pull-Up
device while pin (input)
voltage remains still at the
high level
-
4
uA
VOUT=2.0V
Min. current needed
|IPUL |
through the Pull-Up
device so that pin voltage
is driven to the low level.
100
-
uA
VOUT=0.8V
Note: NMI Pin does not have a Pull-Down device.
Oscillator Pins
Parameter
Symbol
Limit values
min.
max.
Unit
Test
Conditions
Input leakage current
(analog input) at
XTAL11)
IOZ1
CC
-
±200
nA
0V< Vin < VDDP
Input low voltage
XTAL1
VILX
SR
-
0.3
V
-
Input high voltage
XTAL12)
VIHX
SR
0.8
VDD-0.3
VDD-0.35
VDD-0.4
VDD-0.43
V
fOSC=4MHz
fOSC=8MHz
fOSC=12MHz
fOSC=16MHz
XTAL1 input current
IIX1
CC
-
± 20
µA
0V < VIN < VDD
XTAL3 input current2)
IIX3
CC
-
± 0.5
µA
0V < VIN < VDD
1)
Only applicable in deep sleep mode
2)
Not subject to production test, verified by design/characterization.
Data Sheet
34
V 1.0, 2003-10
TC1910
PRELIMINARY
IIC Pins
Each IIC Pin is an open drain output pin with different characteristics than other pins. The
related characteristics are given in the following table
Parameter
Symbol
Limit values
min.
max.
Unit
Test
Conditions
Output low voltage
VOL
CC
-
0.4
0.6
V
3 mA
6 mA
Input high voltage1)
VIH
SR
0.7VDDP
3.6
V
-
Input low voltage1)
VIL
SR
-0.3
0.3VDDP
V
-
Input leakage current
IOZ2
CC
-
+ - 500
nA
Pin capacitance1)
CIO
CC
-
10
pF
1)
f=1MHz@
TA=25oC
Not subject to production test, verified by design/characterization.
Note: No 5 V IIC interface is supported with these pads. Only voltages lower than 3.60
V must be applied to these pads.
Note: IIC pins have no Pull-Up and Pull-Down devices.
Data Sheet
35
V 1.0, 2003-10
TC1910
PRELIMINARY
Codec Electrical Characteristics
Parameter
Symbol
Limit values
Unit
min.
typ.
max.
Digital supply voltage
VDD
1.71
1.8
1.89
V
Analog supply voltage
VDDA
3.0
3.3
3.6
V
Analog supply ground
VSSA
-0.1
0.0
+0.1
V
External reference voltage VAREF1)
1.14
1.2
+1.262) V
Analog reference ground
VAGND
VSSA- VSSA
0.05
Analog input voltage
(RMS)
VSSA+
0.05
V
VAIN
0.775
Vrms
Analog output voltage
(RMS)
VAOUT
0.775
Vrms
Input Resistace of the
Analog Inputs4)
Rain
Internal Reference
Voltage Vref (Bandgap
Voltage)5)
VBGP
Test
Conditions
3)
-
30
-
kOhm differential
input, gain:
-12,-6, 0 dB
-
15
-
kOhm single-ended
input, gain:
-12,-6, 0 dB
-
60
-
kOhm differential
input, gain:
6 to 30 dB
-
30
-
kOhm single-ended
input, gain:
6 to 30 dB
1.1
1.2
1.3
V
AGCCR.
BGPSEL[1,0]
=00
1)
Reference voltage outside the nominal range causes reduced dynamic range, decreased distortion/clipping
margins, increased/decreased gain.
2)
VSSA=VAGND=0V
3)
Please take the gain settings of the analog preamplifier into account, therefore Vimaxreal=Vimax/gain
4)
Simulation value.
5)
For external usage, Bandgap reference voltage is strongly dependent on the external load (<500 MOhm). In
this case, high impedance buffer must be used.
Data Sheet
36
V 1.0, 2003-10
TC1910
PRELIMINARY
Codec ADC and DAC path characteristics
Parameters
Attenuation distortion
(ref. freq. 1014 Hz)
(ref. level 0dBm0)2)
min.
0
-0.25
-0.25
-0.25
0
(ref. level 0dBm0)2)
max.
Unit
dB
dB
dB
dB
dB
0.25
0.45
-55
Signal to total distortion
Gain tracking
(ref. freq. 1014 Hz)
typ.
-0.3
-0.6
-1.6
Test conditions1)
< 0.025
0.025-0.0375
0.0375-0.3
0.3-0.425
> 0.425
-45
dB
at 0dBm0
0.3
0.6
1.6
dB
dB
dB
+3 to -40 dBm0
-40 to -50 dBm0
-50 to -55 dBm0
receive &transmit
Idle channel noise
-80
-75
dBm
0
Cross talk
-80
-75
dB
Harmonic distortion
-60
-50
dB
at 0dBm0
-0.8
0
0.8
dB
receive &transmit
-
-60
-40
-35
-35
dB
dB
Receive (0.0375-0.425)3)
Transmit(0.0375-0.425)3)
Gain
(ref. freq. 1014 Hz)
(ref. level 0dBm0)2)
Power supply
rejection ratio (PSRR)
1)
Values given in this table are valid for all sampling frequencies.
2)
0dBm0 is equivalent to -12dBm is equal to 194.7 mVRMS.
3)
Supply ripple 70 mV.
Note: Numbers without units in the test conditions column are relative frequency values
to the chosen sampling frequency. e.g. 0.425 equals 3.4 kHz @ 8 kHz sampling
frequency.
Data Sheet
37
V 1.0, 2003-10
TC1910
PRELIMINARY
Power Supply Current
Parameter
Symbol
Limit values
typ. 1)
max.
Unit
Test Conditions
Active mode supply
current
IDD
180
–
mA
Sum of all IDD.
Idle mode supply current
IID
IDS
90
–
mA
at 1.8V Core Supply
0.25
–
mA
at 1.8V Core Supply
Deep sleep mode supply
current
1)
Typical values are measured at 25°C, CPU clock at 66 MHz and nominal supply voltage, i.e. 3.3V for VDDP
and 1.8V for VDD, VDDPLL, VDDOSC
Note: The Power Supply Current values refer to the total current at 1.8V power supply,
at LMB/FPI bus frequency ratio of 2:1, while running an average application.
These numbers are estimation based on average device measurements.
Data Sheet
38
V 1.0, 2003-10
TC1910
PRELIMINARY
AC Characteristics
Operating Conditions apply.
Output Rise/Fall Times
GPIO pins
Rise/fall time measurements are made between 10% and 90%.
The following table is valid for the GPIO pins pad drivers. Output pad characteristics are
controllable via DRVCTRx registers.
Pad Modus
rise / fall time
Strong driver
• sharp edge
• medium edge1)
• soft edge1)
1)
Symbol
SF
SM
SS
Limit values
min.
max.
Temp Unit
Comp
-
3
6
12
yes
yes
yes
ns
ns
ns
Test
Conditions
@50pF
@50pF
@50pF
Not subject to production test, verified by design/characterization.
Data Sheet
39
V 1.0, 2003-10
TC1910
PRELIMINARY
Timing Characteristics
(Operating Conditions apply)
Note: Timing parameters are not subject to production test, they are verified by design/
characterization.
2 .4 V
2 .0 V
2 .0 V
T e st P oin ts
0 .4 V
0 .8 V
0 .8 V
M C T 0 4 88 0
AC inputs during testing are driven at 2.4V for a logic “1” and 0.4V for a logic “0”.
Timing measurements are made at VIHmin for a logic “1” and VILmax for a logic “0”.
Figure 11
Data Sheet
Input/Output Waveforms for AC Tests
- for GPIO, Dedicated and EBU pins
40
V 1.0, 2003-10
TC1910
PRELIMINARY
External Oscillator at XTAL1 Timing Requirements
(Operating Conditions apply)
Parameter
Symbol
Main Oscillator XTAL frequency
1)
Frequency of an external oscillator
driving at XTAL12)
Limits
min.
max.
Unit
with/without
PLL
fOSC SR
4
16
MHz
with PLL3)
without PLL4)
fOSCDD
4
-
25
25
MHz
SR
t1
t2
t3
t4
Input Clock high time
Input Clock low time
Input Clock rise time
Input Clock fall time
SR 16
−
ns
SR 16
−
ns
SR −
7
ns
SR −
7
ns
1)
Oscillator Bypass Pin P3.11 latch-in value high. Internal oscillator provides the input clock signal.
2)
Oscillator Bypass Pin P3.11 latch-in value low. Internal oscillator disabled. External oscillator provides the input
clock signal.
3)
Internal PLL provides the system clock. BYPASS pin latch-in value low. PLL prescaler value P=1.
4)
Internal PLL bypassed. BYPASS pin latch-in value high. External oscillator provides the system clock directly.
When CODEC modules is active its frequency limitations must be taken into consideration. Otherwise,
minimum frequency in this mode can go as low as zero.
tO SC
In p u t C lo c k
at XTAL1
0 .5 V D D O S C
t1
t2
t4
t3
V IH X
V IL X
M C T 04 8 8 2
Figure 12
External Clock at XTAL1 Requirements
Note: VDDOSC, VIHX and VIHL are defined in the Oscillator Pins DC Characteristics
Chapter.
Note: It is strongly recommended to measure the oscillation allowance (negative
resistance) in the final target system (layout) to determine the optimal parameters
for the oscillator operation. Please refer to the limits specified by the crystal
supplier.
Data Sheet
41
V 1.0, 2003-10
TC1910
PRELIMINARY
CPU Clock Timing
(Operating Conditions apply; CL = 50 pF)
Parameter
Symbol
Limits
min.
tCLKOUT 15
CLKOUT period
Unit
max.
−
ns
CC
t1
t2
t3
t4
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
CC
6
−
ns
CC
6
−
ns
CC
−
3
ns
CC
−
3
ns
t C P U C LK
C LK OU T
0 .5 V D D
t1
t2
t4
t3
0 .9 V D D
0 .1 V D D
M C T 0 4 88 3
Figure 13
Data Sheet
CLKOUT Timing
42
V 1.0, 2003-10
TC1910
PRELIMINARY
PLL Parameters
Parameter
Limit Values1)
Symbol
min.
Accumulated jitter
VCO frequency range
PLL base frequency
PLL lock-in time
DN
fVCO
fPLLBASE
tL
Unit
max.
see Figure 14
–
100
1502)
MHz
150
2003)
MHz
200
2504)
MHz
250
3005)
MHz
2)
20
80
MHz
20
1303)
MHz
20
1804)
MHz
20
2305)
MHz
–
200
µs
1)
Not subject to production test, verified by design/characterization.
2)
@ vcosel = ’00’
3)
@ vcosel = ’01’
4)
@ vcosel = ’10’
5)
@ vcosel = ’11’
Note: When TC1910 starts-up with the PLL not bypassed, first user instructions are
executed with the frequency defined by the VCO free-running frequency
(fPLLBASE) and by the reset value of the PLL_CLC register (the K-divider and
VCOSEL bitfields). It is software responsibility to initialize its own appropriate
values in the bitfields in this register, before giving the command for the VCO to
lock to the input frequency. For more information, see the Users Manual, System
Units, System Control Unit chapter.
Data Sheet
43
V 1.0, 2003-10
TC1910
PRELIMINARY
TC191x_pll_jitter
±5.0
ns
DN
±4.0
±3.0
fSYS =
fSYS =
fSYS =
fSYS =
fSYS =
±2.0
66 MHz (K = 4)
60 MHz (K = 5)
50 MHz (K = 6)
40 MHz (K = 7)
33 MHz (K = 8)
±1.0
±0.0
0
5
10
15
20
25
P
DN = Max. jitter
P = Number of consecutive fSYS periods
K = K-divider of PLL
Figure 14
35
30
Approximated Maximum Accumulated PLL Jitter
The following two formulas define the (absolute) approximate maximum value of jitter DN
in [ns] dependent on the K-factor, the system clock frequency fSYS in [MHz], and the
number P of consecutive fSYS periods.
735
for P < 0.25× fSYS
DN [ns] = ± [(
+ 0.9) ×
fSYS × K
for P > 0.25× fSYS
DN [ns] = ± [
735
+ 1.4 ]
fSYS × K
P
fSYS × 0.25
+ 0.5 ] [1]
[2]
With rising number P of clock cycles the maximum jitter increases linearly up to a specific
value of P. Beyond this value of P the maximum accumulated jitter remains at a constant
value.
Data Sheet
44
V 1.0, 2003-10
TC1910
PRELIMINARY
Timing for EBU_LMB Clock Outputs
(Operating Conditions apply; CL = 50 pF)
Parameter
Symbol
Limits
min.
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
EBUCLK period
EBUCLK high time
EBUCLK low time
EBUCLK rise time
EBUCLK fall time
BFCLK0 period
BFCLK0 high time
BFCLK0 low time
BFCLK0 rise time
BFCLK0 fall time
Unit
max.
CC
15
−
ns
CC
6
−
ns
CC
6
−
ns
CC
−
2.5
ns
CC
−
2.5
ns
CC
20
−
ns
CC
9
−
ns
CC
9
−
ns
CC
−
3.5
ns
CC
−
2.5
ns
t 1 (t 6 )
EBU CLK/
BFC LK 0
0 .9 V D D
0 .1 V D D
0 .5 V D D
t 2 (t 7 )
Figure 15
Data Sheet
t 3 (t 8 )
t 5 (t 1 0 )
t 4 (t 9 )
M C T 0 4 88 4
EBU_LMB Clock Output Timing
45
V 1.0, 2003-10
TC1910
PRELIMINARY
Timing for SDRAM Access Signals
(Operating Conditions apply; CL = 50 pF)
Parameter
Symbol
Limits
min.
Unit
max.
AD(31:0) input setup to EBUCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
SR 2.0
-
ns
AD(31:0) input hold from EBUCLK
t18 SR 4.0
-
ns
CKE high from EBUCLK
CKE low from EBUCLK
A(23:0) output valid from EBUCLK
A(23:0) output hold from EBUCLK
CS(6:0) low from EBUCLK
CS(6:0) high from EBUCLK
RAS low from EBUCLK
RAS high from EBUCLK
CAS low from EBUCLK
CAS high from EBUCLK
RD/WR low from EBUCLK
RD/WR high from EBUCLK
BC(3:0) low from EBUCLK
BC(3:0) high from EBUCLK
AD(31:0) output valid from EBUCLK
AD(31:0) output hold from EBUCLK
Data Sheet
46
CC -
7.0
ns
CC 2.0
-
ns
CC -
7.0
ns
CC 2.0
-
ns
CC -
7.0
ns
CC 2.0
-
ns
CC -
7.0
ns
CC 2.0
-
ns
CC -
7.0
ns
CC 2.0
-
ns
CC -
7.0
ns
CC 2.0
-
ns
CC -
7.0
ns
CC 2.0
-
ns
CC -
7.7
ns
CC 2.0
-
ns
V 1.0, 2003-10
TC1910
PRELIMINARY
Write Access:
EBUCLK
t1
CKE
t3
t4
Row
A(23:0)
Column
t5
t6
CSx
t8
RAS
t7
t10
CAS
t9
t12
RD/WR
t11
t14
BC(3:0)
t13
Data
(0)
AD(31:0)
Data
(n-1)
t15
t16
Read Access:
EBUCLK
t2
CKE
A(23:0)
t3
Row
t4
Column
t6
CSx
RAS
t9
t10
CAS
RD/WR
t13
t14
BC(3:0)
t17
t18
Data
(0)
AD(31:0)
Data
(n-1)
MCT05319
Figure 16
Data Sheet
SDRAM Access Timing
47
V 1.0, 2003-10
TC1910
PRELIMINARY
Timing for Burst Flash Access Signals
Operating Conditions apply; CL = 50 pF)
Parameter
Symbol
Limits
min.
t1
t2
t3
t5
t6
t7
t8
t9
t11
t12
A(23:0) output valid from BFCLK0
A(23:0) output hold from BFCLK0
CS(6:0) low from BFCLK0
ADV low from BFCLK0
ADV high from BFCLK0
BAA low from BFCLK0
BAA high from BFCLK0
RD low from BFCLK0
AD(31:0) input setup to BFCLK0
AD(31:0) input hold from BFCLK0
Data Sheet
48
Unit
max.
CC −
11.0
ns
CC 0.0
−
ns
CC −
9.0
ns
CC −
10.0
ns
CC 3.0
−
ns
CC −
10.0
ns
CC 3.0
−
ns
CC −
10.0
ns
SR 6.0
−
ns
SR 3.0
−
ns
V 1.0, 2003-10
TC1910
PRELIMINARY
BFCLK0
t1
t2
A[23:0]
Address Valid
t5
t6
ADV
t3
CSx
t9
RD
t7
t8
BAA
t11
t12
D[31:0]
Valid
Valid
Note: Between the end of the Address Phase (ADV goes high) and the beginning of the Command
Phase (RD goes low) several cycles of Command Delay Phase can be inserted.
mct04889_mod_la
Figure 17
Data Sheet
Burst Flash Access Timing (Instruction Read)
49
V 1.0, 2003-10
TC1910
PRELIMINARY
Timing for Demultiplexed Access Signals1)
(Operating Conditions apply; CL = 50 pF)
Parameter
Symbol
Limits
min.
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
ALE low from EBUCLK
ALE high from EBUCLK
A(23:0) output valid from EBUCLK
A(23:0) output hold from EBUCLK
CS(6:0) low from EBUCLK
CS(6:0) high from EBUCLK
MR/W low from EBUCLK
MR/W high from EBUCLK
RMW low from EBUCLK
RMW high from EBUCLK
RD low from EBUCLK
RD high from EBUCLK
RD/WR low from EBUCLK
RD/WR high from EBUCLK
CMDELAY input setup to EBUCLK
CMDELAY hold from EBUCLK
WAIT input setup to EBUCLK
WAIT hold from EBUCLK
BC(3:0) low from EBUCLK
BC(3:0) high from EBUCLK
AD(31:0) output valid from EBUCLK
AD(31:0) output hold from EBUCLK
AD(31:0) input setup to EBUCLK
AD(31:0) input hold from EBUCLK
1)
Unit
max.
CC −
8.0
ns
CC 2.0
−
ns
CC −
8.0
ns
CC 2.0
−
ns
CC −
8.0
ns
CC 2.0
−
ns
CC −
8.0
ns
CC 2.0
−
ns
CC −
8.0
ns
CC 1.0
−
ns
CC −
8.0
ns
CC 0.0
−
ns
CC −
8.0
ns
CC 2.0
ns
SR 4.0
−
ns
SR 3.0
−
ns
SR 4.0
−
ns
SR 3.0
−
ns
CC −
8.0
ns
CC 2.0
−
ns
CC −
8.0
ns
CC 0.0
−
ns
SR 4.0
−
ns
SR 4.0
−
ns
It is user responsibility to program an appropriate whole number of clock cycles to generate the correct phase
length according to the particular asynchronous memory/peripheral device specification.
Data Sheet
50
V 1.0, 2003-10
TC1910
PRELIMINARY
EBUCLK
t1
ALE
t2
t3
t4
Address
A(23:0)
t5
t6
CSx
t7
MR/W
t14
RD/WR
t16
t15
t13
CMDELAY
t18
t17
WAIT
t20
t19
t19
t20
t21
t22
BC(3:0)
Data Out
AD(31:0)
MCT05320
Figure 18
Demultiplexed Write Access
Data Sheet
51
V 1.0, 2003-10
TC1910
PRELIMINARY
EBUCLK
t1
ALE
t2
t3
t4
Address
A(23:0)
t6
CSx
t5
MR/W
t8
t10
t9
t12
RMW
RD
t16
t15
t11
CMDELAY
t18
t17
WAIT
t19
t19
t20
BC(3:0)
t23
t24
Data
AD(31:0)
Note: RMW signal is available only during Read-Modify-Write Access.
MCT05321
Figure 19
Demultiplexed Read Access
Data Sheet
52
V 1.0, 2003-10
TC1910
PRELIMINARY
Timing for Multiplexed Access Signals1)
(Operating Conditions apply; CL = 50 pF)
Parameter
Symbol
Limits
min.
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
ALE high from EBUCLK
ALE low from EBUCLK
AD(31:0) output valid from EBUCLK
AD(31:0) output hold from EBUCLK
AD(31:0) input setup to EBUCLK
AD(31:0) input hold from EBUCLK
CS(6:0) low from EBUCLK
CS(6:0) high from EBUCLK
MR/W low from EBUCLK
MR/W high from EBUCLK
RMW low from EBUCLK
RMW high from EBUCLK
RD/WR low from EBUCLK
RD/WR high from EBUCLK
RD low from EBUCLK
RD high from EBUCLK
CMDELAY input setup to EBUCLK
CMDELAY hold from EBUCLK
WAIT input setup to EBUCLK
WAIT hold from EBUCLK
BC(3:0) low from EBUCLK
BC(3:0) high from EBUCLK
1)
Unit
max.
CC −
8.0
ns
CC 2.0
−
ns
CC −
8.0
ns
CC 0.0
−
ns
SR 4.0
−
ns
SR 4.0
−
ns
CC −
8.0
ns
CC 1.0
−
ns
CC −
8.0
ns
CC 2.0
−
ns
CC −
8.0
ns
CC 1.0
−
ns
CC −
8.0
ns
CC 2.0
−
ns
CC −
8.0
ns
CC 0.0
−
ns
SR 4.0
−
ns
SR 3.0
−
ns
SR 4.0
−
ns
SR 3.0
−
ns
CC −
8.0
ns
CC 2.0
−
ns
It is user responsibility to program an appropriate whole number of clock cycles to generate the correct phase
length according to the particular asynchronous memory/peripheral device specification.
Data Sheet
53
V 1.0, 2003-10
TC1910
PRELIMINARY
EBUCLK
t1
ALE
t2
t3
t4
Address
AD(31:0)
t7
Data
t4
t8
t3
CSx
t9
MR/W
t14
RD/WR
t18
t17
t13
CMDELAY
t20
t19
WAIT
t22
t21
t21
t22
BC(3:0)
MCT05322
Figure 20
Data Sheet
Multiplexed Write Access
54
V 1.0, 2003-10
TC1910
PRELIMINARY
EBUCLK
t1
ALE
t2
t5
t3
t6
Address
AD(31:0)
Data
t4
t8
CSx
t7
MR/W
t10
t12
t11
t16
RMW
RD
t18
t17
t15
CMDELAY
t20
t19
WAIT
t21
t21
t22
BC(3:0)
Note: RMW signal is only available during Read-Modify-Write Access.
Figure 21
Data Sheet
MCT05323
Multiplexed Read Access
55
V 1.0, 2003-10
TC1910
PRELIMINARY
Timing for External Bus Arbitration Signals
(Operating Conditions apply; CL = 50 pF)
Parameter
Symbol
Limits
min.
t1
t2
t3
t4
t5
t6
t7
t8
HOLD input setup to EBUCLK
HOLD input hold from EBUCLK
HLDA low from EBUCLK
HLDA high from EBUCLK
HLDA input setup to EBUCLK
HLDA input hold from EBUCLK
BREQ low from EBUCLK
BREQ high from EBUCLK
Unit
max.
SR 6.0
−
ns
SR 8.0
−
ns
CC −
10.0
ns
CC −
9.0
ns
SR 8.0
−
ns
SR 8.0
−
ns
CC −
10.0
ns
CC −
9.0
ns
Note: The signals HOLD, HLDA and BREQ are alternate function of the CS5, CS6 and
CSOVL Pins.
Data Sheet
56
V 1.0, 2003-10
TC1910
PRELIMINARY
External M aster M ode
EBU C LK
t1
t2
H OLD
t4
H LDA
t3
t8
BREQ
t7
External S lave M ode
EBU C LK
t7
t8
BREQ
t5
t6
H LDA
t1
t2
H OLD
M C T 05324_m od
Figure 22
Data Sheet
External Bus Arbitration Timing
57
V 1.0, 2003-10
TC1910
PRELIMINARY
SSC Master Mode Timing
(Operating Conditions apply; CL = 50 pF)
Parameter
Symbol
Limit Values
min.
Unit
max.
SCLK period
tSCLK
CC
40
ns
MTSR low/high from SCLK edge
t5
CC
-
2.0
ns
MRST setup to SCLK edge
t6
SR
15
-
ns
MRST hold from SCLK edge
t7
SR
15
-
ns
tSCLK
SCLK
(CON.PO,CON.PH=00 or 11)
0.9 VDD
0.1 VDD
0.5 VDD
t2
SCLK
(CON.PO,CON.PH=01 or 10)
t2
t4
t3
0.9 VDD
0.1 VDD
0.5 VDD
t3
t4
t5
MTSR
State n-1
State n
t6
MRST
State n+1
t7
Data valid
Data valid
MCT04885
Figure 23
Data Sheet
SSC Master Mode Timing
58
V 1.0, 2003-10
TC1910
PRELIMINARY
Package Outlines
Figure 24
P-LBGA-208 Package
You can find all of our packages, sorts of packing and other in our Infineon Internet Page
“Products”: http://www.infineon.com/products
•
Data Sheet
59
V 1.0, 2003-10
TC1910
PRELIMINARY
Data Sheet
60
V 1.0, 2003-10
((49))
http://www.infineon.com
Published by Infineon Technologies AG