STA001 RF FRONT-END FOR DIGITAL RADIO PRODUCT PREVIEW ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ SINGLE CHIP RECEIVER FOR SATELLITE DIGITAL TRANSMISSION SUPERHETERODYNE RECEIVER WITH IF OUTPUT HIGH INPUT INTERCEPT POINT, LOW MIXER NOISE 54dB IF VGA GAIN RANGE ADJUSTABLE RF GAIN ADJUSTABLE IF GAIN INTEGRATED RF VCO INTEGRATED IF VCO INTEGRATED SYNTHESIZER TQFP44 ORDERING NUMBER: STA001 I2CBUS COMPATIBLE PROGRAMMING INTERFACE UNREGULATED 2.7 V TO 3.3V VOLTAGE SUPPLY LOW COST EXTERNAL COMPONENTS HSB2 High Speed Bipolar Technology for one chip solution for the Starman digital satellite radio receiver. The STA001 is assembled in a TQFP44 package. The frontend architecture is a double conversion receiver (see block diagram) . The chip includes all the RF functions up to low IF and manages the signals to and from the baseband. DESCRIPTION The STA001 is an RF IC using STMicroelectronics BLOCK DIAGRAM AGC1, AGC2 CE PADJ1, PADJ2 SIP, SIN SOP, SON GADJ1, GADJ2 VDD1 SUPPLY1 :RF SUPPLY4 :IF1, IF2 &PLL2 RF MIXER VSS1 IF1 to IF2 MIXER LNI, NLNI VDD4 VSS4 IF2 BUFFER RXI, NRXI LNA 1.8366 Mhz FLT2 IF1 BUFFER VGA 1338.14 - 1375.4 MHz TK2, NTK2 117.0806 MHz FLT1 113.23KHz TK1, NTK1 PHASE DETECTOR 1st PLL CHARGE PUMP VCO DIFFERENTIAL SINGLE ENDED 3.68MHz VCO CHARGE PUMP : 1034 PHASE DETECTOR ENRFOSC :130 LOCK DETECTOR TLCK 2nd PLL :4 14.72MHz :363.625- 373.75 BUFFER VDD2 SUPPLY2 :PLL1 + Crystal osc . VSS2 M_CLK VDD3 MUX OSC I2CBUS INTERFACE SUPPLY3 :DIG. VSS3 CHANNEL SELECTION XTAL1, XTAL2 SDA SCL XOSEL REF November 2002 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/20 STA001 VSS4 SOP SON VSS4 AGC1 AGC2 VDD4 NTK2 TK2 VDD4 FLT2 PIN CONNECTION (Top view) 44 43 42 41 40 39 38 37 36 35 34 5 29 CE NLNI 6 28 VDD3 VSS1 7 27 SCL N.C. 8 26 SDA PADJ1 9 25 VSS3 PADJ2 10 24 M_CLK1 ENRFOSC 11 23 M_CLK2 12 13 14 15 16 17 18 19 20 21 22 TLCK GADJ2 LNI XOSEL 30 REF 4 XTAL2 GADJ1 VSS1 XTAL1 31 VSS2 3 FLT1 NRXI SIN VDD2 32 NTK1 RXI 2 TK1 33 SIP VDD2 VDD1 1 PIN FUNCTION N° Pin 1 VDD1 2 SIP SAW filter input connection 3 SIN SAW filter input connection 4 VSS1 5 LNI RF input 6 NLNI RF input 7 VSS1 Negative supply 1 8 NC 9 PADJ1 RF gain adjust connection 1 10 PADJ2 RF gain adjust connection 2 11 12 Function Positive supply 1 Negative supply 1 Not connected ENRFOSC RF Oscillator enable VDD2 Positive supply 2 13 TK1 1st PLL tank connection 1 14 NTK1 1st PLL tank connection 2 15 VDD2 Positive supply 2 16 FLT1 1st PLL loop filter connection 17 VSS2 Negative supply 2 18 XTAL1 Quartz oscillator connection 1 19 XTAL2 Quartz oscillator connection 2 20 REF External optional TCXO input 21 XOSEL 22 TLCK 2/20 Internal/external XO selection Lock detector output D97AU602 STA001 PIN FUNCTION (continued) N° Pin Function 23 M_CLK2 Master clock differential output 1 24 M_CLK1 Master clock differential output 2 25 VSS3 Negative supply 3 26 SDA Data serial input 27 SCL Clock input 28 VDD3 Positive supply 3 29 CE 30 GADJ2 Chip Enable IF gain adjust connection 2 31 GADJ1 IF gain adjust connection 1 32 NRXI Low IF Signal output 2 33 RXI Low IF Signal output 1 34 FLT2 2nd PLL loop filter connection 35 VDD4 Positive supply 4 36 TK2 2nd PLL tank connection 37 NTK2 2nd PLL tank connection 38 VDD4 Positive supply 4 39 AGC2 VGA control pin 2 40 AGC1 VGA control pin 1 41 VSS4 Negative supply 4 42 SON SAW filter output connection 43 SOP SAW filter output connection 44 VSS4 Negative supply 4 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Tstg Storage temperature -40 , +125 °C Toper Operative ambient temperature -20 , +85 °C Vmax Maximum voltage on any pin (with the exception of CE, SDA, SDL) VDD+0.3 V Vmin Minimum voltage on any pin GND-0.3 V Vmaxi Maximum voltage on pins CE, SDA, SDL VDD+0.6 V -0.3/5.5 V 2 KV Value Unit VDDmax Vesd Minimum/Maximum power supply between VDD1,2,3,4 and VSS1,2,3,4 Electrostatic Discharge Voltage (ESD) OPERATING CONDITIONS Symbol Parameter VDD Operating voltage 2.7, 3.3 V Tjun Junction temperature -30, +95 °C 3/20 STA001 THERMAL DATA Symbol Parameter RTh j-amb Thermal Resistance Junction to Ambient (1) Value Unit 45 °C/W (1) According to JEDEC specification on a 4 layers board ELECTRICAL CHARACTERISTCS Symbol Parameter Test Condition Min. Typ. Max. Unit SUPPLY CURRENTS (Tamb = 25°, VDD = 3V) ICC1 Current supplied by VDD1 Powered circuits: LNA, RF mixer, IF buffer 9.5 14 17 mA ICC2 Current supplied by VDD2 Powered circuits: RF pll, Crystal Oscillator. ENRFOSC=high (IC RF Osc. Enabled), XOSEL=high (IC XO Enabled) 8.5 10 12 mA ENRFOSC=low (IC RF Osc. Disabled), XOSEL=high (IC XO Enabled) 3 5 6 mA ENRFOSC=high (IC RF Osc. Enabled), XOSEL=low (IC XO Disabled) 7.5 9 11 mA ENRFOSC=low (IC RF Osc. Disabled), XOSEL=low (IC XO Disabled) 2 4 5 mA 12 15 18 mA 7 11 14 mA ICC3 Current supplied by VDD3 Powered circuits: Digital cells ICC4 Current supplied by VDD4 Powered circuits: VGA, IF mixer, output buffer, IF pll. V(AGC1)=V(AGC2)=1.2 (IFgain=75dB) ITOT ICC1+ ICC2+ ICC3+ ICC4 ENRFOSC=high (IC RF Osc. Enabled), XOSEL=high (IC XO Enabled) 40 50 61 mA ENRFOSC=low (IC RF Osc. Disabled), XOSEL=high (IC XO Enabled) 34 45 55 mA ENRFOSC=high (IC RF Osc. Enabled), XOSEL=low (IC XO Disabled) 39 49 60 mA ENRFOSC=low (IC RF Osc. Disabled), XOSEL=low (IC XO Disabled) 34 44 54 mA 100 µA 1452 1492 MHz 114 116.5 MHz 33 dB ITOTSB Standby ICC1+ ICC2+ ICC3+ ICC4 CE=GND LNA, RF MIXER AND IF1 BUFFER (T = 25°, VDD-VSS = 3V) BWi Input signal BW BWo Output signal BW GV 4/20 Voltage Gain Input LNI, NLNI pins; output SIP, NIP pins. RL = 200Ω, PADJ1, PADJ2 floating 28 30 STA001 ELECTRICAL CHARACTERISTCS (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit 22 25 28 dB GVtrim Minimum Voltage Gain Input LNI, NLNI pins; output SIP, NIP pins. RL = 200Ω, Rext=0 Zi Input impedance R || C Balanced, LNI, NLNI pins 75 0.2 Ω pF Zo Output impedance Balanced, SIP, SIN pins 50 Ω Rl Input Return Loss LNI, NLNI pins 14 dB Input IP3 Input LNI, NLNI pins; output SIP, NIP pins, Rl=200Ω, PADJ1, PADJ2 floating -20 -15 dBm IIP3trim Input IP3 minimum gain Input LNI, NLNI pins; output SIP, NIP pins, Rl=200Ω, Rext=0 on PADJ1, PADJ2 -19.5 -11.5 dBm 1dBcp Input 1 dB compression point Input LNI, NLNI pins; output SIP, NIP pins, Rl=200Ω, PADJ1, PADJ2 floating -26 dBm 1dBcptri Input 1 dB compression point Input LNI, NLNI pins; output SIP, NIP pins, Rl=200Ω, PADJ1, PADJ2 Rext=0 on PADJ1, PADJ2 -24 dBm m NF Noise figure contribution Measurement conditions: Input LNI, NLNI pins; output SIP, NIP pins. Rs=50Ω, Rl=200Ω, DSB, PADJ1, PADJ2 floating 5 dB NFtrim Noise figure contribution minimum gain Measurement conditions: Input LNI, NLNI pins; output SIP, NIP pins. Rs=50Ω, Rl=200Ω, DSB, Rext=0 on PADJ1, PADJ2 6.5 dB IF1leak LO1 to IF1 leakage -100 -25 dBm RFleak LO1 to RF leakage -100 -30 dBm VDC LNI, NLNI common mode AC coupled to the Balun DC voltage VDD1.2 VDD-1 VDD0.8 V VDC SIP, SIN common mode DC voltage VDD1.3 VDD1.1 VDD0.9 V IIP3 AC coupled to the SAW filter IF VGA AMPLIFIER, IF MIXER AND OUTPUT BUFFER (T = 25°, VDD-VSS = 3V) BWi Input signal BW 114 116.5 MHz BWo Output signal BW 0.6 3.1 MHz Gmin Minimum gain Input LNI, NLNI pins; output SIP, NIP pins. Rl=high impedance V(AGC1,2)=0V 37 dB Gmax Maximum gain Input LNI, NLNI pins; output SIP, NIP pins. Rl=high impedance V(AGC1,2)=3V IAGC ZAGC 32 71 86 dB Input current in AGC control pin 10 µA AGC pin input impedance 600 KΩ 5/20 STA001 ELECTRICAL CHARACTERISTCS (continued) Symbol Parameter Test Condition Min. NF Noise figure contribution Measurement conditions: Input SIP, NIP pins; output SOP, NOP pins. Rs=50Ω, Rl=200Ω, DSB, Gain = 65dB 1dBcp Input 1 dB compression point 1dBcpfg Typ. Max. Unit 9 dB Gain = 65dB -50 dBm Input 1 dB compression point full gain Gain = 81dB -66 dBm Input IP3 Gain = 65dB -41 dBm IIP3fg Input IP3 full gain Gain = 81dB -57 dBm Zin Input impedance Balanced, SOP, SON pins 50 Ω Zout Output impedance Balanced, RXI, NRXI pins (see fig. 9) 200 Ω VDC SOP, SON common mode DC voltage AC coupled to the SAW filter VDC RXI, NRXI common mode DC voltage VDD2.1 VDC GADJ1, GADJ2 common mode DC voltage VDD0.15 Zadj Gain adjustment pins impedance Balanced, GADJ1, GADJ2 pins 800 Ω BBleak LO2 to BB leakage Obtained using low pass filter at the output -45 dBm IF2leak LO2 to IF2 leakage Obtained with SAW filter connected to IF port Third order IM product Vout=1VDDp IIP3 IM3 VDD1.2 VDD-1 VDD0.12 -100 VDD0.8 V VDD1.36 V VDD V -30 dBm -30 dBc IF TOTAL VOLTAGE GAIN (dB) IF TOTAL VOLTAGE GAIN (dB) input SOP,NOP output RXI,NRXI input SOP,NOP output RXI,NRXI 60 90 55 85 IF TOTAL VOLTAGE GAIN (dB) IF TOTAL VOLTAGE GAIN (dB) Figure 1. Typical IF Overall Gain vs Control Voltage IF gain (dB) 50 45 40 80 IF gain (dB) 75 70 65 35 60 30 1 0.7 0.75 0.77 0.79 0.8 0.82 0.84 V(AGC1, AGC2) (Volt) 6/20 0.86 0.88 0.9 1.2 1.1 1.4 1.3 1.6 1.5 1.8 1.7 2 1.9 2.2 2.1 V(AGC1, AGC2) (Volt) 2.4 2.3 2.6 2.5 2.7 STA001 ELECTRICAL CHARACTERISTCS (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit VDD0.68 V CRYSTAL OSCILLATOR (T = 25°, VDD-VSS = 3V) VDC XTAL1, XTAL2 common mode DC voltage XOSEL high VDD1.1 PLLs, SYNTHESIZERS (T = 25°, VDD-VSS = 3V) ts RF pll loop settling time within 1 KHz final freq. Offset, by using the loop filter of Application board Pn Total phase noise contribution 100Hz < ∆f < 1.84Mhz, Qrf_tank≥20, Qif_tank≥20 1 ms 1.6 degrms fREF1 RF pll comparation frequency 3.68 MHz fREF2 IF pll comparation frequency 113.23 KHz PSP Spurious power level*** RF pll, ∆fc=n*460KHz n=1,2.. IF pll, ∆fc=113.23KHz -50 -100 -45 Nprog1 RF PLL selectable division ratios from REF1 to LO1, range covered by a 0.5 step, using a 14.72MHz quartz 1443 (first used 1454.5) 1506.5 (last used 1495) Nprog2 RF PLL selectable division ratios from REF1 to LO1, range covered by a 0.5 step, using a 14.725MHz quartz 1443 (first used 1454) 1506.5 (last used 1494.5) Nfix IF PLL fixed division ratios from REF2 to LO2, 1 fixed +2 testing values 987 1034 NREF1 REF1 division ratio from Crystal oscillator to REF1 4 NREF2 REF2 division ratio from Crystal oscillator to REF2 130 dBc dBc 1081 *** Using loop filter as suggested in application board schematics RF VCO (T = 25°, VDD-VSS = 3V) fLO1_1 LO Freq. range Using 14.72Mhz quartz 1338.14 1375.4 MHz fLO1_2 LO Freq. range Using 14.725Mhz quartz 1338.134375 to 1375.407031 MHz VFLT1 Freq. control voltage range Pin FLT1 VSS + 0.2 VDC TK1, NTK1 DC voltage ENRFOSC high VDD1.3 Zi Input impedance R || C Balanced, TK1, NTK1 pins VDD1.1 300 0.2 VDD 0.2 V VDD0.65 V Ω pF 7/20 STA001 ELECTRICAL CHARACTERISTCS (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit IF VCO (T = 25°, VDD-VSS = 3V) fLO2_1 LO Freq. Using a 14.72MHz quartz, Min. and Max. Values are optional fixed frequency usable for testing purposes. 111.76 117.08 122.4 MHz fLO2_2 LO Freq. Using a 14.725MHz quartz, Min. and Max. Values are optional fixed frequency usable for testing purposes. 111.8 117.12 122.44 MHz VFLT2 Freq. control voltage range FLT2 pin VSS + 0.2 VDD 0.2 V DIGITAL INTERFACE TO MP (SCL, SDA, TLCK) AND XOSEL INTERFACE (T = 25°, VDD-VSS = 3V) INPUT PARAMETERS (SCL, SDA) VIH digital input signals VIL high VDD-1 VDD V low VSS VSS+0. 7 V IIH Input current High 10 µA IIL Input current Low -40 µA Tt Input edge transition 0.1 µs/V Rin Input resistance 190K Ω OUTPUT PARAMETERS (TLCK) VOH digital output signals VOL high VDD0.5 VDD V low VSS VSS+0. 5 V tr Rise time Cl=5pF 0.4 µs/V tf Fall time Cl=5pF 0.4 µs/V high 0.2 V low -0.2 V DIFFERENTIAL DIGITAL INTERFACE (M_CLK1, M_CLK2) (T = 25°, VDD-VSS = 3V) VOH VOL VDC M_CLK1, M_CLK2 common mode DC voltage VDD1.12 VDD0.7 V tr Rise time Cl=5pF each pin 10 ns tf Fall time Cl=5pF each pin 10 ns Output impedance balanced 500 Ω Zout 8/20 digital output signals, V(M_CLK1) V(M_CLK2) STA001 ELECTRICAL CHARACTERISTCS (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit fM_CLK1 M_CLK frequency Using a 14.72MHz quartz 14.72 MHz fM_CLK2 M_CLK frequency Using a 14.725MHz quartz 14.725 MHz ADDITIONAL DIGITAL INTERFACE (CE) (T = 25°, VDD-VSS = 3V) (LOW=GND, HIGH=VDD) digital input signals VIH high VSS+1. 8 V low VIL VSS+1. 3 V tr CE power up time 2 µs tf CE power down time 6 µs XOSEL, CE, TLCK, ENRFOSC TRUTH TABLE (LOW = GND, HIGH = VDD) Pin CE XOSEL ENRFOSC TLCK Type input input input output Level Result high Chip enabled low Chip disabled high Internal Crystal oscillator selected low External TCXO connected on REF selected high Internal RF oscillator selected low External RF oscillator connected on TK1, NTK1 pins high Synth. locked low Synth. unlocked ADDITIONAL OPTIONAL INTERFACE INFORMATION (REF) Symbol Parameter Test Condition VDC REF DC voltage XOSEL low Rin Input resistance XOSEL low Min. Typ. Max. Unit VDD1.1 VDD0.9 VDD0.7 V 70K Ω 9/20 STA001 FUNCTIONAL DESCRIPTION Receiver chain The receiver chain transforms the RF frequency signals to an IF signal at 1.84 MHz Carrier directly usable by the Channel decoder. In front of the STA001 IC it can be placed an external LNA and a bandpass filter; the bandpass filter limitates the input bandwidth and guarantees a suitable rejection to the image frequency. The STA001 input stage is a LNA working in the 1452-1492 MHz band. The RF signal is downconverted, using an active mixer, to a first IF of 115.244 MHz. The first LO is tunable with a frequency step of 460 KHz. The RF can be reduced 5dB by an external trimmer/resistor connected between PADJ1 and PADJ2 pins. An IF variable gain amplifier guarantees 54 dB typical of gain range. Using pins GADJ1, GADJ2, the output RX signal level can be decreased to the desired value by an external trimmer/resistor. Moreover, the IF chain can be configured to have a fixed gain by fixing statically control voltages on AGC1 and AGC2 pins (i.e. V(AGC1)=VCC and V(AGC2)=GND), and by trimming the gain through connecting an external resistor between GADJ1 and GADJ2. By using an 800 Ohm resistor connected between GADJ1 and GADJ2, for example, a typical 56 dBs IF static gain is obtained. The first IF signal, having a bandwidth of 2.5 MHz, shaped by an external SAW filter, is downconverted to a second IF of 1.84 MHz. A differential clock output at 14.72 MHz is available to be used from the baseband. Synthesizers, PLL, charge pump and VCOs The first Voltage controlled Oscillator is controlled by an integrated PLL and it's able to cover a frequency range of 37MHz with a step size of 460 KHz. The second Voltage controlled oscillator produces a fixed 117.08MHz frequency controlled by a second integrated PLL. Moreover, the 2nd PLL is able to select 2 other fixed frequencies, i.e. 111.76MHz and 122.4MHz, suitable for application test. The other components of the first PLL synthesizer are a low frequency programmable divider and a dual modulus prescaler; a fixed dividers is instead used to synthesize the second VCO frequency. Other fixed internal dividers are used to get the comparation frequencies of both loops. Channel selection is made through the I2CBUS interface , directly from the µP. POWER SUPPLIES The chip operates from an unregulated power supply of 2.7 to 3.3 Volts. All interface circuits to the baseband chips are operating between these supplies unless otherwise specified. INTERFACE SPECIFICATION All the interface voltage levels to the micro controller are referenced to the supply voltage of the interface power supply (GND) . The interface voltage levels are therefore fully compatible with the base band circuits. The digital levels are all CMOS threshold compatible with the exception of M_CLK1, M_CLK2 pins (ECL type). For completeness all other interface signals are also included. I2C BUS INTERFACE Data transmission from microprocessor to the STA001 takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected to SDA and SCL). 10/20 STA001 Data Validity The data on the SDA line must be stable during the high period of the clock. The HIGH to LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop conditions A start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte format Every byte transferred on the SDA line must contains bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. Acknowledge The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse. The peripheral (STA001) that acknowledges has to pull-down (LOW) the SDA line during the clock pulse. The STA001 which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at at the HIGH level during the ninth clock pulse time. In this case the µP can generate the STOP information in order to abort the transfer. Transmission without acknwoledge Avoiding to detect the acknowlegde of the STA001, the µP can use a simpler transmission: simply it waits one clock period without checking the STA001 acknowledging, and sends the new data. This approach of course is less protected from misworking. Figure 2. Validity on the I2CBUS SDA SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED D99AU1031 Figure 3. Timing Diagram of the I2CBUS SCL I2CBUS SDA START D99AU1032 STOP 11/20 STA001 Figure 4. Acknowledge on the I2CBUS SCL 1 2 3 7 8 9 SDA MSB START ACKNOWLEDGMENT FROM RECEIVER D99AU1033 TIMING SPECIFICATION Figure 5. Data and clock SDA SCL tcwl tcs tch Symbol tcwh Parameter Minimum time (ns) tcs Data to clock set up time 100 tch Data to clock hold time 50 tcwh Clock pulse width high 100 tcwl Clock pulse width low 100 Figure 6. Start and stop SDA SCL tstop2tstop1 tstart1 tstart2 Symbol 12/20 Parameter Minimum time (ns) Tstart1,2 Clock to data start time 100 Tstop1,2 Data to clock down stop time 100 STA001 Figure 7. SDA SCL 8 9 td2 td1 Symbol Parameter Maximum time (ns) td1 Ack begin delay 200 td2 Ack end delay 200 SOFTWARE SPECIFICATION Interface protocol The interface protocol comprises: - A start condition (S) - A chip address byte - A two data bytes - A stop condition (P) MSB S chip address 1 1 0 0 0 0 LSB MSB 1st data byte LSB MSB 2nd data byte LSB 0 ack 1 D6 D5 D4 D3 D2 D1 D0 ack 0 D6 D5 D4 D3 D2 D1 D0 ack 0 P ack = Acknowledge S = Start P = Stop "Byte by byte" option A "byte by byte" programming mode is also possible when there is no need to use both data bytes to program the chip (for example during the setup of 2nd PLL). To use this feature remember that first bit of both data bytes is reserved to chose the destination of the remaining 7 bits. MSB S chip address 1 1 0 0 0 LSB 0 0 0 MSB ack K 1st data byte D6 D5 D4 D3 LSB D2 D1 D0 ack P ack = Acknowledge S = Start 13/20 STA001 P = Stop K= destination of the remaining 7bit: K=1 the data byte has the same function of the 1st data byte in the normal programming mode. K=0 the data byte has the same function of the 2nd data byte in the normal programming mode. Table 1. First data byte selection table (selection of synthesizer channel) using a 14.72Mhz quartz MSB LSB RF LO freq. selected Units Division ratio selected on synthesizer Notes from REF1 to LO1 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 1 1 0 1324.8+6*0.46 (1327.56) MHz 360.75 0 0 0 0 1 1 1 1324.8+7*0.46 MHz 360.875 0 0 0 1 0 0 0 1324.8 + 8*0.46 MHz 361 - - - - - - - 0 0 1 1 1 0 1 1338.14 MHz 363.625 first used freq. - - - - - - - 1324.8 + N*0.46 N=(D6..D0) represented decimal number MHz 360 + N*0.125 general freq. generation rule 1 1 0 1 1 1 0 1375.4 MHz 373.75 Last used freq. - - - - - - - 1 1 1 1 1 1 1 1383.22 MHz 375.875 0 0 0 0 0 0 0 1383.68 MHz 376 - - - - - - - 0 0 0 0 1 0 1 1324.8+133*0.46 (1385.98) MHz 376.625 Highest selectable freq. 1 0 0 0 1 0 1 1356.54 MHz 368.625 Startup presetted data 14/20 Lowest selectable freq. STA001 Table 2. First data byte selection table (selection of synthesizer channel) using a 14.725Mhz quartz MSB LSB RF LO freq. selected Units Division ratio selected on synthesizer Notes D6 D5 D4 D3 D2 D1 D0 from REF1 to LO1 0 0 0 0 1 1 0 1325.25 +6*0.46015625 (1328.010938) MHz 360.75 0 0 0 0 1 1 1 1325.25 +7*0.46015625 MHz 360.875 0 0 0 1 0 0 0 1325.25+ 8*0.46015625 MHz 361 - - - - - - - 0 0 1 1 1 0 0 1338.134375 MHz 363.5 first used freq. - - - - - - - 1325.25+ N*0.46015625 N=(D6..D0) represented decimal number MHz 360 + N*0.125 general freq. generation rule 1 1 0 1 1 0 1 1375.407031 MHz 373.625 Last used freq. - - - - - - - 1 1 1 1 1 1 0 1383.229688 MHz 375.75 1 1 1 1 1 1 1 1383.689844 MHz 375.875 - - - - - - - 0 0 0 0 1 0 1 1325.25 +133*0.46015625 (1386.450781) MHz 376.625 Highest selectable freq. 1 0 0 0 1 0 1 1357.000781 MHz 368.625 Startup presetted data Lowest selectable freq. Table 3. Second data byte selection table (LOCK test on both pll, dividers test and IF pll test) MSB LSB Working mode Notes 0 Lock test on RF pll lock flag to be tested: TLCK; Startup presetted data 0 0 Lock test on IF pll lock flag to be tested: TLCK 0 0 1 Lock test on RF and IF pll lock flag to be tested: TLCK 0 1 0 First pll programmable divider test output freq. divided by 16 available on TLCK 1 0 1 0 First pll reference divider test output freq. divided by 8 available on TLCK 1 0 1 1 0 Second pll fixed divider test output freq. divided by 2 available on TLCK 0 1 1 1 1 0 Second pll reference divider test output freq. available on TLCK 1 0 0 0 0 0 0 Test frequency on IF pll divider by 1034 Division ratio changed to 987 1 1 0 0 0 0 0 Test frequency on IF pll divider by 1034 Division ratio changed to 1081 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 15/20 C41 100pF VCC C39 100pF VCC C33 100pF VCC C26 100pF VCC C22 100pF VCC C19 100pF VCC RF IN IF1 OUT IF2 IN J2 2 J5 2 2 SMA 1 C34 8pF C12 C35 1nF L3 R7 50 SMA 1 R3 50 1 SMA C36 100nF 1:1 6 4 2 1:4 T2 6 4 2 1:1 T3 6 4 2 + C31 10uF VCC LDB20C500A1500 5 1 NEOSID 553210 5 1 NEOSID 553200 5 1 T1 C14 C13 C10 C8 C4 C2 8pF 8pF 1nF 1nF 1nF 1nF R16 1K R13 1K L5 1nH C37 8pF HVU355 D4 HVU355 D3 C17 8pF L4 1nH VCC AGC1 AGC2 1 3 2 4 C30 JUMPER2 JP1 R10 VP1 VP2b VP2a R14 0 100K R4 100K R1 R2 VP1 SIP SIN VN1 LNI NLNI VN1 NC PADJ1 PADJ2 ENRFOSC C29 150nF R15 390 1 2 3 4 5 6 7 8 9 10 11 U1 C6 100nF C3 100nF MA372J D1 L1 68nH STA001 C24 15nF CRYSTAL Y1 C27 C23 C28 10nF RXI NRXI GADJ1 GADJ2 CE VP3 SCL SDA VN3 M_CLK1 M_CLK2 VP4a 33 32 31 30 29 28 27 26 25 24 23 R17 50 5.6 K R5 L2 68nH VP4b MA372J D2 680pF C1 44 43 42 41 40 39 38 37 36 35 34 VN4 SOP SON VN4 AGC1 AGC2 VP4 NTK2 TK2 VP4 FLT2 VP2 TK1 NTK1 VP2 FLT1 VN2 XTAL1 XTAL2 REF XOSEL TLCK 12 13 14 15 16 17 18 19 20 21 22 J1 1 330pF J6 JP2 SMA 1 3 VP3 C7 3.3 nF C5 2 R12 4.7K 2 4 C20 10nF C16 10nF R11 4.7K R6 18 k VCC R8 220nF VCC VCC C11 C9 220nF T_LOCK CLK2 CLK1 SCL SDA 1 J4 1 J3 2 16/20 RXI OUT R9 1K NRXI OUT SMA SMA C15 10nF 2 VCC CE STA001 TEST AND APPLICATION BOARD SCHEMATIC Figure 8. Test Board Schematic Diagram NOTE: Connect a resistor from10K to 100K between pins PADJ1 (9) and PADJ2 (10) so to obtain intermediate gain between 25 and 30dB RF IN SMA C34 100pF C33 100pF C30 100pF C25 100pF C22 100pF VCC VCC VCC VCC VCC 10n C17 1 L5 100nH 100p C10 100p C18 5p C11 L6 7.5nH C6 10n C5 100p 22p C8 3 I O ANT +B U3 C32 1nF VCC 100p 4 C12 S+M B69813-N1477-A840 33 R4 GND GND GND GND 1 2 5 6 J3 2 VCC R5 33K L7 1 3 2 2SC5096 Q1 L4 56nH C13 6.8p 1K R11 1K R8 L8 6.8nH 2.2p C15 100nH L3 1:1 6 4 T1 2 C16 C14 2.2nH L10 2.2nH C31 8pF HVC355B D4 HVC355B D3 C19 8pF L9 LDB20C500A1500 5 1 18 17 16 15 14 13 12 11 10 GND IN IN GND GND GND NC NC GND 8pF 8pF VP1 1 2 3 4 5 6 7 8 9 C28 GND NC NC GND GND GND OUT OUT GND S+M Y012B U1 R9 0 VP2b VP2a VCC C27 150nF R10 390 1 2 3 4 5 6 7 8 9 10 11 VP1 SIP SIN VN1 LNI NLNI VN1 NC PADJ1 PADJ2 ENRFOSC U2 10K C2 100nF VCC MA2S372 D1 L1 68nH AGC 44 43 42 41 40 39 38 37 36 35 34 STA001 C24 15nF CRYSTAL Y1 C26 C23 VCC RXI NRXI GADJ1 GADJ2 CE VP3 SCL SDA VN3 M_CLK1 M_CLK2 VP4a 33 32 31 30 29 28 27 26 25 24 23 5.6 K R2 L2 68nH VP4b MA2S372 D2 680pF C1 VN4 SOP SON VN4 AGC1 AGC2 VP4 NTK2 TK2 VP4 FLT2 VP2 TK1 NTK1 VP2 FLT1 VN2 XTAL1 XTAL2 REF XOSEL TLCK 12 13 14 15 16 17 18 19 20 21 22 VCC VP3 VCC 330pF C4 3.3 nF C3 C21 10nF C20 10nF R6 4.7K R3 18 k C7 C9 R7 4.7K VCC 150nF 150nF T_LOCK CLK2 CLK1 SCL SDA 1 J2 1 2 2 R1 J1 SMA SMA NRX RXI O STA001 Figure 9. Application Board Schematic Diagram Suggested minimum differential RLoad on RXI and NRXI output 3K 17/20 STA001 Application note: the crystal oscillator must have the following features: Symbol Parameter Test Condition Min. Typ. Max. Unit CRYSTAL OSCILLATOR (T = 25°, VP-VN = 3V) fxtal1 Quartz frequency - Resonance mode: series - Using a 14.72 14.72 MHz fxtal2 Quartz frequency - Resonance mode: series - using a 14.725 quartz 14.725 MHz Phase noise ∆f = 1 KHz XTAL1, XTAL2 common mode DC voltage XOSEL high Pn VDC 18/20 VP-1.1 -120 -118 dBc/Hz VP-0.9 VP-0.7 V STA001 mm DIM. MIN. TYP. A inch MAX. MIN. TYP. 1.60 A1 0.05 A2 1.35 B 0.30 C 0.09 0.063 0.15 0.002 0.006 1.40 1.45 0.053 0.055 0.057 0.37 0.45 0.012 0.014 0.018 0.20 0.004 0.008 D 12.00 0.472 D1 10.00 0.394 D3 8.00 0.315 e 0.80 0.031 E 12.00 0.472 E1 10.00 0.394 E3 8.00 0.315 L 0.45 0.60 0.75 OUTLINE AND MECHANICAL DATA MAX. 0.018 0.024 L1 1.00 K 0°(min.), 3.5˚(typ.), 7°(max.) 0.030 0.039 TQFP44 (10 x 10) D D1 A A2 A1 33 23 34 22 0.10mm .004 B E B E1 Seating Plane 12 44 11 1 C L e K TQFP4410 19/20 STA001 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 20/20