INTEGRATED CIRCUITS 74F1604 Latch Product specification IC15 Data Handbook 1990 Oct 04 Philips Semiconductors Product specification Latch 74F1604 FEATURES PIN CONFIGURATION • High impedance NPN base inputs for reduced loading LE 1 (20µA in high and low state) • Stores 16–bit wide data inputs, multiplexed 8–bit outputs 28 V CC SELECT A/B 2 27 A4 A0 3 26 B4 B0 4 25 A5 A1 5 24 B5 B1 6 23 A6 DESCRIPTION A2 7 22 B6 The 74F1604 is a dual octal transparent latch. Organized as 8–bit A and B latches, the latch outputs are connected by pairs to eight 2–input multiplexers. A select (SELECT A/B) input determines whether the A or B latch contents are multiplexed to the eight outputs. Data from the B inputs are selected when SELECT A/B is low; data from the A inputs are selected when SELECT A/B is high. Data enters the latch on the falling edge of the latch enable (LE) input. The latch remains transparent to the data inputs while LE is low, and stores the data that is present one setup time before the low–to–high latch enable transition. B2 8 21 A7 • Propagation delay 7.0ns typical • Power supply current 70mA typical TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 7.0ns 70mA 74F1604 A3 9 20 B7 B3 10 19 Q7 Q3 11 18 Q6 Q2 12 17 Q5 Q1 13 16 Q4 GND 14 15 Q SF00553 LOGIC SYMBOL 3 4 5 6 7 8 9 10 27 26 25 24 2322 21 20 ORDERING INFORMATION A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6B6A7 B7 ORDER CODE DESCRIPTION COMMERCIAL RANGE PKG DWG # VCC = 5V ±10%, Tamb = 0°C to +70°C 28–pin plastic DIP N74F1604N SOT117-2 28–pin plastic SOL N74F1604D SOT136-1 1 LE 2 SELCT A/B Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 VCC = Pin 28 GND = Pin 14 INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW 15 13 12 11 16 17 18 19 SF00554 IEC/IEEE SYMBOL 2 1 A0 – A7 Data inputs 1.0/0.033 20µA/20µA B0 – B7 Data inputs 1.0/0.033 20µA/20µA 3 4 SELECT A/B LE Select input 1.0/0.033 20µA/20µA 5 C1 1D 2 1D 2 1 15 13 6 Latch enable input (active low) 1.0/0.033 7 20µA/20µA Data outputs 50/33 12 8 9 Q0 – Q7 G2 1.0mA/20mA 11 10 Note to input and output loading and fan out table One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state. 27 16 26 25 17 24 23 18 22 21 19 20 SF00555 October 4, 1990 2 853 0088 00619 Philips Semiconductors Product specification Latch 74F1604 LOGIC DIAGRAM 2 SELECT A/B 1 LE 3 D E A0 Q 4 B0 D E 15 Q 5 D E A1 Q 6 B1 D E 13 Q 7 D E A2 D E 12 Q 9 D E A3 D E 11 Q 27 D E A4 D E 16 Q 25 D E A5 D E 17 Q 23 D E A6 D E 18 Q 21 D E A7 D E VCC = Pin 28 GND = Pin 14 Q6 Q 20 B7 Q5 Q 22 B6 Q4 Q 24 B5 Q3 Q 26 B4 Q2 Q 10 B3 Q1 Q 8 B2 Q0 19 Q Q7 SF00556 FUNCTION TABLE INPUTS OUTPUTS OUTPUTS OPERATING MODE A0 – A7 B0 –B7 SELECT A/B LE Q0 – Q7 A data A data B data L L B data B data H L A data X X X H NC A data B data l ↑ B data Enable and read register Hold Latch and read register A data B data h ↑ A data Notes to function table H = High–voltage level h = High–voltage level one setup time before the low–to–high latch enable transition L = Low–voltage level l = Low–voltage level one setup time before the low–to–high latch enable transition NC= No change ( If SELECT A/B is toggled and the A latched data is different from B latched data then the output will change accordingly.) X = Don’t care ↑ = Low–to–high latch enable transition October 4, 1990 3 Philips Semiconductors Product specification Latch 74F1604 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current –30 to +5 mA VOUT Voltage applied to output in high output state –0.5 to VCC V IOUT Current applied to output in low output state 40 mA Tamb Operating free air temperature range 0 to +70 °C Tstg Storage temperature range –65 to +150 °C RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS UNIT MIN NOM MAX VCC Supply voltage 4.5 5.0 5.5 VIH High–level input voltage 2.0 VIL Low–level input voltage 0.8 V IIk Input clamp current –18 mA IOH High–level output current –1 mA IOL Low–level output current 20 mA Tamb Operating free air temperature range +70 °C V V 0 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) PARAMETER SYMBOL TEST LIMITS CONDITIONS1 IOH = –1mA VOH High-level output voltage VCC = MIN, VIL = MAX, IOH = –3mA VIH = MIN VOL Low-level output voltage VCC = MIN, VIL = MAX, VIH = MIN IOL = MAX MIN ±10%VCC 2.5 ±5%VCC 2.7 ±10%VCC 2.4 ±5%VCC 2.7 TYP2 UNIT MAX V 3.4 V V 3.3 V ±10%VCC 0.30 0.50 V ±5%VCC 0.30 0.50 V –0.73 -1.2 V 100 µA VIK Input clamp voltage VCC = MIN, II = IIK II Input current at maximum input voltage VCC = MAX, VI = 7.0V IIH High–level input current VCC = MAX, VI = 2.7V 20 µA IIL Low–level input current VCC = MAX, VI = 0.5V –20 µA IOS Short–circuit output current3 -150 mA ICC Supply current (total) 80 mA VCC = MAX ICCH -60 VCC = MAX 60 ICCL 75 100 mA Notes to DC electrical characteristics 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. October 4, 1990 4 Philips Semiconductors Product specification Latch 74F1604 AC ELECTRICAL CHARACTERISTICS LIMITS Tamb = +25°C SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V CL = 50pF, RL = 500Ω VCC = +5.0V ± 10% CL = 50pF, R = 500Ω MIN TYP MAX MIN MAX UNIT tPLH tPHL Propagation delay SELECT A/B to Qn (non–inverting) Waveform 2 3.0 3.5 5.5 6.5 8.5 10.0 2.5 3.0 9.0 11.5 ns tPLH tPHL Propagation delay SELECT A/B to Qn (inverting) Waveform 1 4.0 2.5 7.0 4.5 10.5 7.5 3.5 2.0 12.0 8.0 ns tPLH tPHL Propagation delay LE to Qn Waveform 3 6.5 6.0 9.5 9.0 13.0 12.5 5.5 5.0 15.0 14.0 ns tPLH tPHL Propagation delay An or Bn to Qn Waveform 1, 2 4.0 4.0 6.5 7.0 9.5 10.5 3.5 3.5 10.5 12.5 ns AC SETUP REQUIREMENTS LIMITS Tamb = +25°C SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V CD = 50pF, RL = 500Ω MIN TYP VCC = +5.0V ± 10% CD= 50pF, RL = 500Ω MAX MIN UNIT MAX tsu (H) tsu (L) Setup time, high or low An, Bn to LE Waveform 4 0.0 1.0 0.0 3.5 ns th (H) th (L) Hold time, high or low An, Bn to LE Waveform 4 1.5 3.0 2.0 3.5 ns tw (L) LE Pulse width, low Waveform 4 6.5 7.5 ns AC WAVEFORMS An, Bn, SELCET A/B VM VM tPHL tPLH VM Qn LE VM VM VM tPHL VM tPLH VM Qn VM SF00559 SF00557 Waveform 1. Propagation delay for SELECT A/B to output (A register stored data = low) or An. Bn to output An, Bn, SELCET A/B VM VM tPHL tPLH Waveform 3. Propagation delay for latch enable to output An, Bn VM tsu(H) Qn VM LE VM VM th(H) VM VM tsu(L) VM th(L) VM SF00560 SF00558 Waveform 4. Setup time and hold times and LE pulse width Waveform 2. Propagation delay for SELECT A/B to output (A register stored data = low) or An. Bn to output Note to AC waveforms For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. October 4, 1990 5 Philips Semiconductors Product specification Latch 74F1604 TEST CIRCUIT AND WAVEFORMS VCC NEGATIVE PULSE VIN tw 90% VM D.U.T. RT CL RL AMP (V) VM 10% VOUT PULSE GENERATOR 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V AMP (V) 90% 90% POSITIVE PULSE DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. VM VM 10% Test Circuit for Totem-Pole Outputs 10% tw 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00006 October 4, 1990 6 Philips Semiconductors Product specification Latch 74F1604 DIP28: plastic dual in-line package; 28 leads (600 mil); long body 1990 Oct 04 7 SOT117-2 Philips Semiconductors Product specification Latch 74F1604 SO28: plastic small outline package; 28 leads; body width 7.5mm 1990 Oct 04 8 SOT136-1 Philips Semiconductors Product specification Latch 74F1604 NOTES 1990 Oct 04 9 Philips Semiconductors Product specification Latch 74F1604 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 10 Date of release: 10-98 9397-750-05194