INTEGRATED CIRCUITS 74F2373 Octal transparent latch with 30Ω equivalent output termination (3-State) Product specification Supersedes data of 1995 Jun 20 IC15 Data Handbook 1999 Feb 01 Philips Semiconductors Product specification Octal transparent latch with 30Ω equivalent output termination (3-State) 74F2373 The data on the D inputs is transferred to the latch outputs when the enable (E) input is high. The latch remains transparent to the data input while E is high, and stores the data that is present one setup time before the high-to-low enable transition. FEATURES • 8-bit transparent latch • 30 Ohm output termination for driving DRAM • 3-State outputs glitch free during power-up and power-down • Common 3-State output register • Independent register and 3-State buffer operation The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active low output enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is low, latched or transparent data appears at the output. When OE is high, the outputs are in high impedance “off ” state, which means they will neither drive nor load the bus. DESCRIPTION The 74F2373 is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates. TYPE The 30 Ohm series termination on the outputs reduces over/undershoot, making them ideal for driving DRAM TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 4.5ns 35mA 74F2373 ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE DRAWING NUMBER VCC = 5V ±10%, Tamb = 0°C to +70°C 20-pin plastic DIP N74F2373N SOT146-1 20-pin plastic SOL N74F2373D SOT163-1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Data inputs 1.0/1.0 20µA/0.6mA Enable input (active high) 1.0/1.0 20µA/0.6mA Output enable inputs (active low) 1.0/1.0 20µA/0.6mA 3-State outputs 150/40 3.0mA/3.0mA PINS DESCRIPTION D0 - D7 E OE Q0 - Q7 NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state. PIN CONFIGURATION LOGIC SYMBOL OE 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 3 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 8 13 14 17 18 E OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 11 E VCC = Pin 20 GND = Pin 10 SF00250 1999 Feb 01 7 D0 D1 D2 D3 D4 D5 D6 D7 1 Q2 6 4 2 5 6 9 12 15 16 19 SF00251 853-2140 20747 Philips Semiconductors Product specification Octal transparent latch with 30Ω equivalent output termination (3-State) 74F2373 IEC/IEEE SYMBOL 1 EN1 11 EN2 3 2D 2 1 4 5 7 6 9 8 13 12 14 15 17 16 18 19 SF00252 LOGIC DIAGRAM D1 4 D0 3 D E D2 7 D E Q D3 8 D E Q D4 13 D E Q D5 14 D E Q D6 17 D E Q D7 18 D E Q D E Q Q 11 E OE 1 VCC = Pin 20 GND = Pin 10 2 5 6 9 Q0 Q1 Q2 Q3 12 Q4 15 Q5 16 Q6 19 Q7 SF00256 FUNCTION TABLE INPUTS OUTPUTS OE E Dn INTERNAL REGISTER L H L L L L H H H H L ↓ l L L L ↓ h H H L L X NC NC H L X NC Z H H Dn Dn Z NOTES: H = High-voltage level h = High state must be present one setup time before the high-to-low enable transition L = Low-voltage level l = Low state must be present one setup time before the high-to-low enable transition NC= No change X = Don’t care Z = High impedance “off ” state ↓ = High-to-low enable transition 1999 Feb 01 OPERATING MODE Q0 - Q7 3 Enable and read register Latch and read register Hold Disable outputs Philips Semiconductors Product specification Octal transparent latch with 30Ω equivalent output termination (3-State) 74F2373 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.) SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 VIN Input voltage –0.5 to +7.0 V V IIN Input current –30 to +5 mA VOUT Voltage applied to output in high output state -0.5 to VCC V IOUT Current applied to output in low output state Tamb Operating free air temperature range Tstg Storage temperature range 24 mA 0 to +70 °C –65 to +150 °C RECOMMENDED OPERATING CONDITIONS SYMBOL * LIMITS PARAMETER MIN NOM MAX 5.0 5.5 UNIT VCC Supply voltage 4.5 V VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V IIk Input clamp current –18 mA IOH High-level output current –3* mA IOL Low-level output current 5* mA Tamb Operating free air temperature range +70 °C V 0 12mA with reduced noise margin DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL VOH O TEST CONDITIONS1 PARAMETER High level output voltage High-level MIN VCC = MIN, VIL = MAX, ±10%VCC 2.4 VIH = MIN, IOH = –3mA ±5%VCC 2.7 VCC = MIN, VIL = MAX, ±10%VCC 2.0 VIH = MIN, IOH = –12mA ±5%VCC 2.0 ±10%VCC ±5%VCC ±10%VCC ±5%VCC LIMITS TYP2 MAX UNIT V 3.4 V V V VOL Low-level out output ut voltage VIK II IIH IIL Input clamp voltage Input current at maximum input voltage High-level input current Low-level input current VCC = MIN, VIL = MAX, VIH = MIN, IOL = –5mA VCC = MIN, VIL = MAX, VIH = MIN, IOL = 12mA VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V IOZH Off-state output current, high-level voltage applied VCC = MAX, VO = 2.7V 50 V V V V V µA µA mA µA IOZL Off-state output current, low-level voltage applied VCC = MAX, VO = 0.5V -50 µA -150 mA IOS Short-circuit output current3 VCC = MAX 0.42 0.42 0.67 0.67 -0.73 -60 0.50 0.50 -1.2 100 20 -0.6 ICC Supply current (total) VCC = MAX 35 60 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 1999 Feb 01 4 Philips Semiconductors Product specification Octal transparent latch with 30Ω equivalent output termination (3-State) 74F2373 AC ELECTRICAL CHARACTERISTICS LIMITS Tamb = +25°C SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω VCC = +5.0V CL = 50pF, RL = 500Ω UNIT MIN TYP MAX MIN MAX Waveform 2 3.0 2.0 5.3 3.7 8.0 6.0 3.0 2.0 9.0 7.0 ns Propagation delay E to Qn Waveform 1 5.0 3.0 9.0 4.0 12.0 8.0 5.0 3.0 12.5 8.5 ns tPZH tPZL Output enable time to high or low level Waveform 4 Waveform 5 2.0 2.0 5.0 5.6 12.0 8.0 2.0 2.0 12.5 8.5 ns tPHZ tPLZ Output disable time from high or low level Waveform 4 Waveform 5 2.0 2.0 4.5 3.8 6.5 5.5 2.0 2.0 7.5 6.5 ns tPLH tPHL Propagation delay Dn to Qn tPLH tPHL AC SETUP REQUIREMENTS LIMITS Tamb = +25°C SYMBOL PARAMETER TEST CONDITION MIN tsu (H) tsu (L) Setup time, high or low level Dn to E th (H) th (L) tw (H) Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL= 50pF, RL = 500Ω VCC = +5.0V CL = 50pF, RL = 500Ω TYP MAX MIN UNIT MAX Waveform 3 0 1.0 0 1.0 ns Hold time, high or low level Dn to E Waveform 3 3.0 3.0 3.0 3.0 ns E Pulse width, high Waveform 1 3.5 4.0 ns AC WAVEFORMS For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. tw(H) E Dn VM VM VM tPHL tsu(H) tPLH Qn VM E VM VM tsu(L) th(H) VM th(L) VM VM VM VM SF00261 SF00259 Waveform 3. Data setup time and hold times Waveform 1. Propagation delay for enable to output and enable pulse width Dn OEn VM VM tPHL tPLH Qn, Qn Qn VM VM tPZH tPHZ VOH -0.3V VM 0V VM SF00260 SF00263 Waveform 2. Propagation delay for data to output 1999 Feb 01 VM Waveform 4. 3-State output enable time to high level and output disable time from high level 5 Philips Semiconductors Product specification Octal transparent latch with 30Ω equivalent output termination (3-State) 74F2373 AC WAVEFORMS (Continued) For all waveforms, VM = 1.5V. The shaded areas indicate when the input is permitted to change for predictable output performance. OEn VM VM tPZL tPLZ VM Qn, Qn VOL +0.3V SF00264 Waveform 5. 3-State output enable time to low level and output disable time from low level TEST CIRCUIT AND WAVEFORMS SWITCH POSITION TEST SWITCH tPLZ, tPZL closed All other open PULSE GENERATOR 7.0V VCC tw 90% NEGATIVE PULSE 90% VM VM 10% VIN RL VOUT AMP (V) 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V D.U.T. RT CL RL Test circuit for 3-state outputs AMP (V) POSITIVE PULSE VM VM 10% 10% tw DEFINITIONS: 0V Input pulse definition RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 90% 90% INPUT PULSE REQUIREMENTS family 74F amplitude VM rep. rate 3.0V 1.5V 1MHz tw tTLH 500ns 2.5ns tTHL 2.5ns SF00265 1999 Feb 01 6 Philips Semiconductors Product specification Octal transparent latch with 30Ω equivalent output termination (3-State) DIP20: plastic dual in-line package; 20 leads (300 mil) 1999 Feb 01 7 74F2373 SOT146-1 Philips Semiconductors Product specification Octal transparent latch with 30Ω equivalent output termination (3-State) SO20: plastic small outline package; 20 leads; body width 7.5 mm 1999 Feb 01 8 74F2373 SOT163-1 Philips Semiconductors Product specification Octal transparent latch with 30Ω equivalent output termination (3-State) NOTES 1999 Feb 01 9 74F2373 Philips Semiconductors Product specification Octal transparent latch with 30Ω equivalent output termination (3-State) 74F2373 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 10 Date of release: 10-98 9397-750-05201