TDA1566 I2C-bus controlled dual channel 46 W/2 Ω, single channel 92 W/1 Ω amplifier with load diagnostic features Rev. 02 — 20 August 2007 Product data sheet 1. General description The TDA1566 is a car audio power amplifier with a complementary output stage realized in BCDMOS. The TDA1566 has two Bridge Tied Load (BTL) output stages and comes in a HSOP24 or DBS27P package. The TDA1566 can be controlled with or without I2C-bus. With I2C-bus control gain settings per channel and diagnostic trigger levels can be selected. Failure conditions as well as load identification can be read with I2C-bus. The load identification detects whether the outputs of a BTL channel are connected with a DC or AC load and discriminates between a speaker load, a line driver load and an open (unconnected) load. The TDA1566 can be configured in a single BTL mode and drive a 1 Ω load. For the single BTL mode it is necessary to connect on the Printed-Circuit Board (PCB) the outputs of both BTL channels in parallel. 2. Features n Operates in I2C-bus mode and non-I2C-bus mode n TH version: four I2C-bus addresses controlled by two pins; J version: two I2C-bus addresses controlled by one pin n Two 4 Ω or 2 Ω capable BTL channels or one 1 Ω capable BTL channel n Low offset n Pop free off/standby/mute/operating mode transitions n Speaker fault detection n Selectable gain (26 dB and 16 dB) n In I2C-bus mode: u DC load detection: open, short and speaker or line driver present u AC load (tweeter) detection u Programmable trigger levels for DC and AC load detection u Per channel programmable gain (26 dB and 16 dB, selectable per channel) u Selectable diagnostic levels for clip detection and thermal pre-warning u Selectable information on the DIAG pin for clip information of each channel separately and independent enabling of thermal-, offset- or load fault n Independent short-circuit protection per channel n Loss of ground and open VP safe n All outputs short-circuit proof to VP, GND and across the load n All pins short-circuit proof to ground n Temperature controlled gain reduction at high junction temperatures TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier n Fault condition diagnosis per channel: short to ground, short to supply, shorted lead and speaker fault (wrongly connected) n Low battery voltage detection n TH version: pin compatible with the TDA8566TH1 3. Ordering information Table 1. Ordering information Type number Package Name Description Version TDA1566TH HSOP24 plastic, heatsink small outline package; 24 leads; low stand-off height SOT566-3 TDA1566J DBS27P plastic DIL-bent-SIL (special bent) power package; 27 leads (lead length 6.8 mm) SOT827-1 4. Block diagram ADS2 ADS1 8 SDA SCL 6 5 9 VP1 VP2 14 23 22 13 EN 7 MODE SELECT IN1− IN2+ IN2− 16 10 MUTE 11 26 dB/ 16 dB 18 19 MUTE 26 dB/ 16 dB 21 PROTECTION /DIAGNOSTIC VP 3 DIAG OUT1+ OUT1− PROTECTION /DIAGNOSTIC MUTE 2 CLIP SELECT DIAGNOSTIC /CLIP DETECT I 2 C-BUS 1 IN1+ PROG MUTE 15 24 TDA1566TH 4 12 17 20 SVR SGND PGND1 PGND2 OUT2+ OUT2− 1OHM TAB 001aac999 Fig 1. Block diagram (TDA1566TH) TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 2 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier ADS1 SDA 2 EN IN1+ IN1− IN2+ IN2− 1 MODE SELECT VP1 SCL 26 25 VP2 7 21 20 SELECT DIAGNOSTIC /CLIP DETECT I 2 C-BUS 6 10 3 MUTE 4 26 dB/ 16 dB 13 15 MUTE 26 dB/ 16 dB 18 PROTECTION /DIAGNOSTIC VP 23 MUTE 9, 11, 14, 17, 19 8 TDA1566J 27 24 SVR DIAG OUT1+ OUT1− PROTECTION /DIAGNOSTIC MUTE 22 PROG 5 SGND 12 16 PGND1 PGND2 OUT2+ OUT2− n.c. 1OHM TAB 001aad002 Fig 2. Block diagram (TDA1566J) TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 3 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier 5. Pinning information 5.1 Pinning TAB 24 1 VP2 23 2 IN2+ PROG 22 3 IN2− OUT2− 21 4 SVR PGND2 20 5 SCL OUT2+ 19 DIAG 6 SDA 7 EN PGND1 17 8 ADS2 OUT1+ 16 9 ADS1 OUT1− 18 TDA1566TH 1OHM 15 10 IN1+ VP1 14 11 IN1− 12 SGND CLIP 13 001aad006 Fig 3. Pin configuration for TDA1566TH (top view) TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 4 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier EN 1 ADS1 2 IN1+ 3 IN1− 4 SGND 5 DIAG 6 VP1 7 1OHM 8 n.c. 9 OUT1+ 10 n.c. 11 PGND1 12 OUT1− 13 n.c. 14 TDA1566J OUT2+ 15 PGND2 16 n.c. 17 OUT2− 18 n.c. 19 PROG 20 VP2 21 IN2+ 22 IN2− 23 SVR 24 SCL 25 SDA 26 TAB 27 001aad007 Fig 4. Pin configuration for non mounting base TDA1566J (front) 5.2 Pin description Table 2. Pin description TDA1566TH Symbol Pin Description DIAG 1 diagnostic output IN2+ 2 positive input channel 2 IN2− 3 negative input channel 2 SVR 4 supply voltage ripple decoupling SCL 5 I2C-bus clock input SDA 6 I2C-bus data input/output EN 7 enable input ADS2 8 I2C-bus address select bit 2 ADS1 9 I2C-bus address select bit 1 IN1+ 10 positive input channel 1 IN1− 11 negative input channel 1 SGND 12 signal ground TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 5 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier Table 2. Pin description TDA1566TH …continued Symbol Pin Description CLIP 13 clip detect and temperature pre-warning output VP1 14 supply voltage channel 1 1OHM 15 1 Ω select pin OUT1+ 16 positive output channel 1 PGND1 17 power ground channel 1 OUT1− 18 negative output channel 1 OUT2+ 19 positive output channel 2 PGND2 20 power ground channel 2 OUT2− 21 negative output channel 2 PROG 22 program input/output VP2 23 supply voltage channel 2 TAB 24 connect to PGND Table 3. Pin description TDA1566J Symbol Pin Description EN 1 enable input ADS1 2 I2C-bus address select bit 1 IN1+ 3 positive input channel 1 IN1− 4 negative input channel 1 SGND 5 signal ground DIAG 6 diagnostic output VP1 7 supply voltage channel 1 1OHM 8 1 Ω select pin n.c. 9 not connected OUT1+ 10 positive output channel 1 n.c. 11 not connected PGND1 12 power ground channel 1 OUT1− 13 negative output channel 1 n.c. 14 not connected OUT2+ 15 positive output channel 2 PGND2 16 power ground channel 2 n.c. 17 not connected OUT2− 18 negative output channel 2 n.c. 19 not connected PROG 20 program input/output VP2 21 supply voltage channel 2 IN2+ 22 positive input channel 2 IN2− 23 negative input channel 2 SVR 24 supply voltage ripple decoupling TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 6 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier Table 3. Pin description TDA1566J …continued Symbol Pin Description SCL 25 I2C-bus clock input SDA 26 I2C-bus data input/output TAB 27 connect to PGND 6. Functional description 6.1 General Naming conventions used in this document: • Reference to bits in instruction bytes: IBx[Dy] refers to bit Dy of instruction byte x • Reference to bits in data bytes: DBx[Dy] refers to bit Dy of data byte x 6.1.1 Mode selection The ADS1 pin selects the I2C-bus or non-I2C-bus mode operation as listed in Table 4. See Section 6.1.6 and Section 6.4.3 for the ADS1 pin functionality. Table 4. Mode selection with the ADS1 pin Pin Non-I2C-bus mode I2C-bus mode ADS1 GND open or via 33 kΩ to GND Table 5 lists the control for the I2C-bus mode operation. In I2C-bus mode the EN pin operates at CMOS compatible LOW and HIGH logic levels. With the EN pin LOW the TDA1566 is switched off and the quiescent current is at its lowest value. With the enable pin HIGH the operation mode of the TDA1566 is selected with IB1[D0] and IB1[D1]. The I2C-bus instruction and data bytes are described in Section 6.4.2 and Section 6.4.3. Table 5. I2C-bus mode operation EN pin IB1[D0] IB2[D0] Operation mode HIGH (> 2.6 V) 1 0 operating 1 1 mute 0 don’t care standby don’t care don’t care off LOW (< 1.0 V) In non-I2C-bus mode the TDA1566 has 3 operation modes: off/mute/operation. The operation mode is selected with the EN pin. Figure 5 displays the required voltage levels at the EN pin in I2C-bus and non-I2C-bus mode. For the voltage levels see Section 9 “Characteristics”. TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 7 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier I2C-bus mode off 0V operation mode defined by IB1[D0] and IB2[D0] 1.0 V 2.6 V VP non-I2C-bus mode off 0V mute 1.0 V 2.6 V operating 4.5 V 6.5 V VP 001aad008 Fig 5. Enable pin mode switching in I2C-bus and non-I2C-bus mode 6.1.2 Gain selection The TDA1566 features a 16 dB and a 26 dB gain setting. The 16 dB setting is referred to as line driver mode, the 26 dB setting is referred to as amplifier mode. Table 6 shows how the gain is selected. Table 6. Gain select in I2C-bus and non-I2C-bus mode Gain select 16 dB 26 dB I2C-bus IB3[D6] = 1 IB3[D6] = 0[1] IB3[D5] = 1 IB3[D5] = 0[2] PROG connected with 1.5 kΩ to GND PROG open[3] Non-I2C-bus 6.1.2.1 [1] Channel 1. [2] Channel 2. [3] Both channels. I2C-bus mode The gain is selected with IB3[D6] for channel 1 and IB3[D5] for channel 2. If the gain select is performed when the amplifier is muted, the gain select will be pop free. See Section 6.4.2 for the definition of the instruction bytes. If DC load detection is used, IB1[D1] = 1, auto gain select is activated. Detection of an open load (see Section 6.2.1) will result in a line driver mode setting. If the load detection data is invalid, IB3[D5] and IB3[D6] will define the gain setting. 6.1.2.2 Non-I2C-bus mode The gain for channel 1 and channel 2 is selected with the PROG pin. Leaving the pin unconnected selects 26 dB gain and connecting a resistor of 1500 Ω between the PROG pin and GND selects 16 dB gain. When the amplifier is used in line driver mode loads of 2 Ω and 4 Ω can be driven. With a load larger than 25 Ω a Zobel network of 33 nF in series with 22 Ω should be connected between the amplifier output terminals. The Zobel network should be placed close to the output pins. To prevent instability in 1 Ω mode the amplifier must not be used in line driver mode with a load larger than 25 Ω. TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 8 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier 6.1.3 Balanced and unbalanced input sources The TDA1566 accepts balanced as well as unbalanced input signals. Table 7 and Table 8 show the required hard or software setting and Figure 6 shows the input source connection. Note that the unbalanced input source should be connected to the positive BTL channel input. Note that the J version accepts in non-I2C-bus mode only a balanced input source. Table 7. Balanced and unbalanced input source setting TDA1566TH Source I2C-bus mode Non-I2C-bus Table 8. mode Unbalanced input source IB3[D1] = 0 IB3[D1] = 1 ADS2 pin connected to GND ADS2 pin unconnected Balanced and unbalanced input source setting TDA1566J Source I2C-bus Balanced input source mode Non-I2C-bus mode Balanced input source Unbalanced input source IB3[D1] = 0 IB3[D1] = 1 default not selectable 001aad009 Fig 6. Balanced (left) and unbalanced (right) input source 6.1.4 Single channel 1 Ω operation The input and output pins for single channel 1 Ω operation are listed in Table 9. The 1 Ω operation requires that on the PCB the output pins are shorted as indicated in Table 9. In the 1 Ω operation the input signal is taken from channel 1. To prevent instability in 1 Ω operation the amplifier must not be used in line driver mode with a load larger than 25 Ω. Table 9. Pinning for the single channel 1 Ω mode; TDA1566TH and TDA1566J Symbol Pin (TDA1566TH) Pin (TDA1566J) Description single channel operation Description dual channel operation IN2+ 2 22 disabled: connect IN2+ with 470 nF to SGND positive input channel 2 IN2− 3 23 disabled: connect IN2+ with 470 nF to SGND negative input channel 2 IN1+ 10 3 positive input channel 1 positive input channel 1 IN1− 11 4 negative input channel 1 negative input channel 1 1OHM 15 8 1 Ω select pin connected to VP 1 Ω select pin connected to GND OUT1+ 16 10 positive output channel 1 positive output channel 1 OUT1− 18 13 negative output channel 1 negative output channel 1 OUT2+ 19 15 shorted on board to OUT1− positive output channel 2 OUT2− 21 18 shorted on board to OUT1+ negative output channel 2 TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 9 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier 6.1.5 Mute speed setting In I2C-bus mode the amplifier can be muted slow (20 ms) or fast (0.1 ms). The mute speed is selected with IB2[D2]. See Section 6.4.2 for the definition of the instruction bytes. Table 10 lists the operation mode transitions where slow and fast mute are applied. The operation modes are described in Section 6.1.1, Table 5. Table 10. Mute speed setting Mode transition I2C-bus mode Non-I2C-bus mode Mute to operating slow mute slow mute Operating to mute IB2[D2] = 0: slow mute slow mute IB2[D2] = 1: fast mute Operating to standby slow mute n.a. Operating to off fast mute fast mute 6.1.6 Pins with double functions Table 11. Pins with double functions Pin I2C-bus mode Non-I2C-bus mode PROG load detection reference current programming, see Section 6.2.1 and 6.2.2 gain select, see Section 6.1.2 ADS1 I2C-bus address select bit 1, see Section 6.4.1 non-I2C-bus mode select, see Section 6.1.1 ADS2[1] I2C-bus address select bit 2, see Section 6.4.1 balanced/unbalanced input, see Section 3 EN chip enable, see Section 6.1.1 mode select, see Section 6.1.1 [1] TH version only. 6.2 Load identification (I2C-bus mode only) 6.2.1 DC load detection The default setting IB1[D1] = 0 disables DC load detection. When the DC load detection is enabled with IB1[D1] = 1, an offset is slowly applied at the output of the amplifiers at the beginning of the start-up cycle. The DC load is measured and compared with Rtrip1 and Rtrip2 to distinguish between an amplifier load, line driver load or open load. Rtrip1 and Rtrip2 are set with resistor RPROG (1 %) connected between the PROG pin and GND. amplifier load 0Ω line driver load 25 Ω 100 Ω open load 500 Ω Rtrip1 5 kΩ ∞ Rtrip2 001aad010 Fig 7. DC load detection limits (RPROG = 1500 Ω/1 %) The relation between RPROG, Rtrip1 and Rtrip2 is approximated by (valid for RPROG should be between 1.2 kΩ and 4 kΩ): TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 10 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier Rtrip1 = 0.1 × (RPROG − 720) Ω Rtrip2 = 1.05 × (RPROG − 450) Ω Rtrip1 and Rtrip2 levels presented refer to the advised value of 1500 Ω. Note that a shorted load will be interpreted as an amplifier load. The result of the DC load detection is stored in DB1[D4] and DB1[D5] for channel 1 and in DB2[D4] and DB2[D5] for channel 2, see Table 12. Table 12. Interpretation of DC load detection bits Open load bits Amplifier load bits DC load valid bit DB1[D4] and DB2[D4] DB1[D5] and DB2[D5] DB3[D3] Description 0 0 1 amplifier load 0 1 1 line driver load 1 don’t care 1 open load Don’t care don’t care 0 invalid DC load detection result Note that the DC load bits are only valid if DB3[D3] = 1. The DC load detection valid bit is reset, DB3[D3] = 0, when the DC load detection is started with a not completely discharged SVR capacitor (VSVR > 0.3 V) or when the DC load detection is interrupted by an engine start (VP < 7.5 V typical, see Section 9). 6.2.2 AC load detection The AC load detection is used to detect if AC coupled speakers like tweeters are connected correctly during assembly. The detection starts when IB1[D2] changes from LOW to HIGH. A sine wave of a certain frequency (e.g. 19 kHz) needs to be applied to the inputs of the amplifier. The output voltage over the load impedance will cause an output current in the amplifier. Output currents larger than 1.15 × Iref will set the AC load detection bit and no AC load is detected when the output current is less than 0.85 × Iref, see Figure 8. The reference current Iref is set with an external resistor RPROG (1 %) connected between the PROG pin and GND. The relation between RPROG and Iref is given by: Iref = 390 / RPROG [A] (valid for RPROG between 1.2 kΩ and 4 kΩ). To set the AC load detection bit the peak output current must pass the 1.15 × Iref threshold three times. The three ‘threshold cross’ counter is used to prevent false AC load detection caused by switching the input signal on or off. To reset the slope counter, IB1[D2] needs to be reset. With RPROG = 1500 Ω the current thresholds are set to 200 mA and 320 mA. 0.78 × Iref no AC load detected 200 mA (peak) 1.22 × Iref AC load detected 320 mA (peak) 001aad011 Fig 8. AC load detection limits The levels presented refer to the advised value of 1500 Ω. TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 11 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier For instance at an output voltage of 4 V peak the total impedance must be less than 10 Ω to detect the AC coupled load or more than 13.4 Ω to guarantee no connected AC load is detected. Values between 10 Ω and 13.4 Ω cannot be recognized. The result of the AC load detection is shown in DB1[D7] for channel 1 and DB2[D7] for channel 2. When IB1[D2] = 1 the AC load detection is enabled. The AC load detection can only be performed after the amplifier has completed its start-up cycle and will not conflict with the DC load detection. The default setting of IB1[D2] = 0 disables AC load detection. Note: in the 1 Ω mode Iref is doubled, so Iref = 2 × 390 / RPROG [A]. 6.3 Diagnostic 6.3.1 Diagnostic table The available diagnostic information is shown in Table 13 and Table 14. Refer to Table 17 and Table 18 for the bitmap of the instruction and data bytes. DIAG and CLIP have an open-drain output, are active LOW and must have an external pull-up resistor to an external voltage. DIAG shows fixed information and via the I2C-bus selectable information. This information will be seen on DIAG and CLIP as a logical OR. The temperature pre-warning diagnostic and clip information is available on the CLIP. In case of a failure, DIAG will remain LOW and the microprocessor can read out the failure information via the I2C-bus. The I2C-bus bits are set on a failure and will be reset with the I2C-bus read command. Even when the failure is removed the microprocessor will know what was wrong by reading the I2C-bus. The consequence of this procedure is that during the I2C-bus read old information is read. Most actual information will be gathered with 2 read commands after each other. DIAG will give actual diagnostic information (when selected). When a failure is removed, DIAG will be released instantly, independently of the I2C-bus latches. Table 13. Available diagnostic data TH version Diagnostic I2C-bus mode Non-I2C-bus mode DIAG CLIP DIAG CLIP POR yes no no no Low VP or load dump detection yes no yes no Clip detection selectable yes no yes Temperature pre-warning selectable yes no yes Short selectable no yes no Speaker protection selectable no yes no Offset detection selectable no yes no Maximum temperature protection yes no yes no Load detection no no no no TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 12 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier Note that in the J version no CLIP pin is available. Table 14. Available diagnostic data J version Diagnostic POR I2C-bus mode Non-I2C-bus mode DIAG DIAG yes no Low VP or load dump detection yes yes Clip detection selectable yes Temperature pre-warning selectable yes Short selectable yes Speaker protection selectable yes Offset detection selectable no Maximum temperature protection yes yes Load detection no no Following diagnostic information is only available via I2C-bus: • DC and AC load detection results, see Section 6.2 • DB3[D4] is set when the DC settling of the amplifier has almost completed and the SVR voltage has risen to a value of VP / 2 or above, see Section 6.5.1 6.3.2 Diagnostic level settings Table 15. Clip and temperature pre-warning level setting Setting Clip detection level I2C-bus mode Non-I2C-bus mode IB2[D7] = 0 selects 3 % 3% IB2[D7] = 1 selects 7 % Temperature pre-warning level IB3[D4] = 0 selects 145 °C 145 °C IB3[D4] = 1 selects 122 °C 6.3.3 Temperature pre-warning If in I2C-bus mode the average junction temperature reaches a by I2C-bus selectable level, the pre-warning will be activated resulting in a LOW CLIP pin. In non-I2C mode the thermal pre-warning is set on 145 °C. In the TH version the thermal pre-warning is available on the CLIP pin in I2C-bus mode and non-I2C mode. In the J version the thermal pre-warning is available on the DIAG pin in non-I2C-bus mode. In I2C-bus mode the presence of the thermal pre-warning on the DIAG is selected with IB1[D4], see Section 6.3.1 and Section 6.4.2. If the temperature increases above the pre-warning level, the temperature controlled gain reduction will be activated for both channels resulting in a lower output power. If this does not reduce the average junction temperature, both channels will be switched off at the absolute maximum temperature Toff, typical 175 °C. TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 13 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier 6.3.4 Speaker protection To prevent damage of the speaker when one side of the speaker is connected to ground, see Figure 9, a ‘missing current protection’ is implemented. IO1 IO2 001aad012 Fig 9. Speaker protection condition When in one BTL channel the absolute value of the current through the output terminals differ, so |IO1| ≠ |IO2|, a fault condition is assumed, and the BTL channel will be switched off. The ‘speaker protection active’ diagnosis options for I2C-bus and non-I2C-bus mode are listed in Table 13. 6.3.5 Offset detection The offset detection can be performed with no input signal (for instance when the DSP is in mute after a start-up) or with input signal. In I2C-bus mode the offset bits DB1[D2] and DB2[D2] are set by executing a read command. The offset bits will be reset when the BTL output voltage Vo = |VOUT1+ − VOUT1−| enters the offset threshold window of 1.5 V. The offset bits are read with a 2nd read command. In non-I2C-bus mode (or in I2C-bus mode with offset diagnostic selected on DIAG) DIAG will be pulled LOW if the BTL output voltage is more than 1.5 V. TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 14 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier Vo = VOUT+ − VOUT− offset threshold Vo = VOUT+ − VOUT− offset threshold time time DB1[D2] read DIAG DB1[D2] = 1 0 0 => 1 time Vo = VOUT+ − VOUT− offset threshold Vo = VOUT+ − VOUT− offset threshold time time DB1[D2] read DIAG DB1[D2] = 1 1 1 time 001aad013 I2C-bus mode only TH version only: Non-I2C-bus mode TH/J version: I2C-bus mode with offset fault selected on DIAG Fig 10. Offset detection in I2C-bus mode and in non-I2C-bus mode 6.4 I2C-bus operation 6.4.1 I2C-bus address with hardware address select Table 16. I2C-bus address table TH version ADS1 ADS2 A6 A5 A4 A3 A2 A1 A0 R/W[1] open open 1 1 0 1 0 0 0 1/0 GND 1 1 0 1 0 0 1 1/0 33 kΩ to GND open 1 1 0 1 0 1 0 1/0 GND 1 1 0 1 0 1 1 1/0 [1] 0 = write to TDA1566TH; 1 = read from TDA1566TH. Table 17. I2C-bus address table J version ADS1 A6 A5 A4 A3 A2 A1 A0 R/W[1] open 1 1 0 1 0 0 1 1/0 33 kΩ to GND 1 1 0 1 0 1 1 1/0 [1] 0 = write to TDA1566J; 1 = read from TDA1566J. TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 15 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier 6.4.2 Instruction bytes If R/W bit = 0, the TDA1566 expects 3 instruction bytes; IB1, IB2 and IB3. After a power-on reset, all instruction bits are set to zero. In 1 Ω mode the instruction bits of channel 1 are used. The instruction bits labelled ‘reserved for test’ should be set to zero. Table 18. Instruction bytes Bit Instruction byte IB1 Instruction byte IB2 Instruction byte IB3 D7 0 slow start enable 0 clip detect level on 3% reserved for test 1 slow start disable 1 clip detect level on 7% 0 channel 1 no clip detect on DIAG reserved for test 1 channel 1 clip detect on DIAG 0 channel 2 no clip detect on DIAG 1 channel 2 clip detect on DIAG 0 no temperature prewarning on DIAG 0 speaker protection or short on DIAG 1 temperature prewarning on DIAG 1 D6 D5 D4 D3 D2 D1 D0 reserved for test 0 channel 1 26 dB gain 1 channel 1 16 dB gain 0 channel 2 26 dB gain 1 channel 2 16 dB gain 0 temperature prewarning on 145 °C no speaker protection 1 or short on DIAG temperature prewarning on 122 °C reserved for test reserved for test 0 channel 1 enabled 1 channel 1 disabled 0 AC load detection disabled; detection slope counter reset 0 slow mute (20 ms) 0 channel 2 enabled 1 AC load detection enabled 1 fast mute (0.1 ms) 1 channel 2 disabled 0 DC load detection disabled 0 offset fault on DIAG 0 balanced input 1 DC load detection enabled 1 no set fault on DIAG 1 unbalanced input 0 TDA1566 in standby 0 channel 1 and channel 2 operating reserved for test 1 TDA1566 in mute or operating (see IB2[D0]) 1 channel 1 and channel 2 muted 6.4.3 Data bytes If R/W = 1, the TDA1566 will send 3 data bytes to the microprocessor: DB1, DB2, and DB3. All short diagnostic and offset detect bits are latched. All bits are reset after a read operation except DB1[D7], DB2[D7], DB1[D4], DB2[D4], DB1[D5] and DB2[D5]. DB1[D2] and DB2[D2] are set after a read operation, see Section 6.3.5. DB1[D7] and DB2[D7] are reset when IB1[D2] is LOW. In 1 Ω mode the diagnostic information will be shown in DB1. The content of the bits ‘reserved for test’ should be ignored. TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 16 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier Table 19. Data bytes Bit Data byte DB1 channel 1 Data byte DB2 channel 2 Data byte DB3 both channels D7 0 no AC load detected 0 no AC load detected 0 TDA1566 in mute or operating (IB1[D0] = 1) 1 AC load detected 1 AC load detected 1 power-on reset has occurred or TDA1566 in standby (IB1[D0] = 0) 0 no speaker fault 0 no speaker fault 0 below maximum temperature 1 speaker fault 1 speaker fault 1 maximum temperature protection activated D6 D5 0 1 D4 0 1 amplifier load (D4 = 0) 0 amplifier load (D4 = 0) 0 not valid (D4 = 1) not valid (D4 = 1) line driver load (D4 = 0) 1 D2 D1 D0 1 open load (D4 = 1) open load (D4 = 1) amplifier load (D5 = 0) 0 amplifier load (D5 = 0) 0 line driver load (D5 = 1) line driver load (D5 = 1) not valid (D5 = 0) 1 open load (D5 = 1) D3 line driver load (D4 = 0) not valid (D5 = 0) no temperature warning temperature pre-warning active SVR below VP / 2 1 SVR above VP / 2 open load (D5 = 1) 0 no shorted load 0 no shorted load 0 invalid DC load data 1 shorted load 1 shorted load 1 valid DC load data 0 no output offset reserved for test 0 no output offset 1 output offset detected 1 0 no short to VP 0 no short to VP 1 short to VP 1 short to VP output offset detected 0 no short to ground 0 no short to ground 1 short to ground 1 short to ground reserved for test reserved for test 6.5 Timing waveforms 6.5.1 Start-up and shutdown To prevent switch-on or switch-off pop noise, the capacitor on the SVR pin CSVR is used for smooth start-up and shutdown. During start-up and shutdown the output voltage tracks the SVR voltage. With IB1[D7] = 0 the time constant made with the SVR capacitor can be increased to reduce turn on transients at the load. Consequently the start-up time td(mute_off) increases with approximately 420 ms (VP = 14.4 V, CSVR = 22 µF, Tamb = 25 °C). Note that in non-I2C-bus mode the IB1[D7] = 0 setting will be used. Increasing CSVR results in a longer start-up and shutdown time. Note that a larger SVR capacitor value will also result in a longer DC load detection cycle. TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 17 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier For optimized pop performance it is recommended to keep the amplifier in mute until the SVR voltage has reached its final level. When the amplifier is switched off by pulling the EN pin LOW the amplifier is muted (fast mute) and the capacitor on the SVR pin will be discharged. With an SVR capacitor of 22 µF the off current is reached 2 s after the EN pin is switched to zero. Start-up and shutdown in I2C-bus mode is shown in Figure 11 and explained in Table 20. VP DIAG DB3[D7] 5 DB3[D4] 9 3 7 4 IB1[D0] IB2[D0] = 0 2 6 1 8 EN 10 SVR t dcload t d(mute-fgain) t wake OUTx slow mute fast mute t d(mute_off) 001aad014 Fig 11. Start-up and shutdown timing in I2C-bus mode Table 20. Start-up and shutdown timing in I2C-bus mode Step Action Result 1 TDA1566 is enabled with EN TDA1566 from off to standby DB3[D7] is set and DIAG is pulled LOW to indicate power-on reset 2 TDA1566 is switched from standby to operating with IB1[D0] = 1 DIAG is released DB3[D7] is reset SVR capacitor is charged, OUTx voltage tracks SVR voltage gradual increase of gain; when the SVR voltage increases above a threshold of 2 V + 2VBE the amplifiers operate at full gain TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 18 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier Table 20. Step Start-up and shutdown timing in I2C-bus mode …continued Action Result 3 4 SVR voltage has become larger than VP / 2 resulting in setting DB3[D4] TDA1566 is switched from operating to standby with IB1[D0] = 0 TDA1566 is switched from standby to operating with IB1[D0] = 1 7 8 SVR is discharged, OUTx voltage tracks SVR voltage amplifier is slow muted SVR voltage has dropped below VP / 2 resulting in resetting DB3[D4] 5 6 DIAG is pulled LOW see step 2 see step 3 TDA1566 is disabled with EN DIAG is pulled LOW amplifier is fast muted SVR is discharged, OUTx voltage tracks SVR voltage 9 see step 5 10 OUTx is at ground potential, DIAG is released, TDA1566 is off 6.5.2 Engine start The DC-output voltage of the amplifier follows the voltage on the SVR pin. On the SVR pin a capacitor is connected which is used for start-up and shutdown timing as well as for DC load detection. If the supply voltage drops during engine start below 8.6 V the SVR capacitor will be discharged and the fast mute is activated to prevent audible transients at the output. If in I2C-bus mode the supply voltage drops below 5.5 V (see VP(POR)) the content of the I2C-bus latches cannot be guaranteed and the power-on reset will be activated: DB3[D7] = 1. All latches will be reset, the amplifier is switched off and the DIAG pin will be pulled LOW to indicate that a power-on reset has occurred. The TDA1566 will not start-up but wait for a command to start-up. 7. Limiting values Table 21. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VP supply voltage operating; RL = 4 Ω - 18 V operating; RL = 2 Ω or 1Ω - 16 V non operating −1 +50 V load dump protection; during 50 ms; tr ≥ 2.5 ms - 50 V maximum 10 minutes - −2 V - 13 A VP(r) reverse supply voltage IOSM non-repetitive peak output current TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 19 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier Table 21. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit IORM repetitive peak output current - 8 A IBGM peak back gate current loss off GND or open VP application failure; supply decoupling capacitor of maximum 3 × 2200 µF/16 V and a series resistance of 70 mΩ - 50 A V1OHM voltage on pin 1OHM operating, non operating [1] 0 24 V VEN voltage on pin EN operating, non operating [1] 0 24 V VIN1- voltage on pin IN1− operating, non operating [2] 0 13 V VIN1+ voltage on pin IN1+ operating, non operating [2] 0 13 V VIN2- voltage on pin IN2− operating, non operating [2] 0 13 V VIN2+ voltage on pin IN2+ operating, non operating [2] 0 13 V VDIAG voltage on pin DIAG operating, non operating [2] 0 13 V VCLIP voltage on pin CLIP operating, non operating [2] 0 13 V VPROG voltage on pin PROG operating, non operating [2] 0 13 V VSVR voltage on pin SVR operating, non operating [2] 0 13 V VSCL voltage on pin SCL operating, non operating [2] 0 6.5 V VSDA voltage on pin SDA operating, non operating [2] 0 6.5 V VADS1 voltage on pin ADS1 operating, non operating [2] 0 6.5 V VADS2 voltage on pin ADS2 operating, non operating [2] 0 6.5 V Tj junction temperature - 150 °C Tstg storage temperature −55 +150 °C Tamb ambient temperature −40 +85 °C V(prot) protection voltage AC and DC short-circuit voltage of output pins and across the load - VP V Ptot total power dissipation Tcase = 70 °C - 80 W TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 20 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier Table 21. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Vesd electrostatic discharge voltage HBM C = 100 pF; Rs = 1500 Ω Min Max Unit - 2000 V - 200 V MM C = 200 pF; Rs = 10 Ω; L = 0.75 µH [1] The voltage on this pin is clamped by an ESD protection. If this pin is connected to VP a series resistance of 10 kΩ should be added. [2] The voltage on this pin is clamped by an ESD protection. 8. Thermal characteristics Table 22. Thermal characteristics Symbol Parameter Rth(j-c) thermal resistance from junction to case Rth(j-a) Conditions Typ Unit TDA1566TH 1.0 K/W TDA1566J 1.0 K/W thermal resistance from junction to ambient TDA1566TH in free air 35 K/W TDA1566J in free air 35 K/W 9. Characteristics Table 23. Characteristics Refer to test circuit (see Figure 22); VP = 14.4 V; RL = 4 Ω; −40 °C < Tamb < +85 °C and −40 °C < Tj < +150 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VP(low)(mute) 14.4 18 V VP(low)(mute) 14.4 16 V - 180 220 mA - 10 15 mA - 2 10 µA Supply voltage behavior VP(oper) operating supply voltage RL = 4 Ω RL = 2 Ω or 1 Ω quiescent current no load Istb standby current I2C-bus Ioff off-state current VEN ≤ 0.4 V; Tj < 85 °C VO output voltage VP(low)(mute) low supply voltage mute Iq VP(POR) mode only 6.7 7.2 7.6 V falling supply voltage 6.5 7.2 7.7 V rising supply voltage 7.0 7.6 8.2 V 4.1 5.0 5.8 V power-on reset supply voltage TDA1566_2 Product data sheet [1] © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 21 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier Table 23. Characteristics …continued Refer to test circuit (see Figure 22); VP = 14.4 V; RL = 4 Ω; −40 °C < Tamb < +85 °C and −40 °C < Tj < +150 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VO(offset) output offset voltage amplifier mode; on −50 0 +50 mV line driver mode; on −25 0 +25 mV amplifier and line driver mode; mute −25 0 +25 mV off condition; I2C-bus and non-I2C-bus mode - - 1.0 V standby mode; I2C-bus mode 2.6 - VP V 2.6 - 4.5 V Mode select pin EN (see Figure 5) VEN voltage on pin EN mute condition; mode IEN current on pin EN non-I2C-bus operating condition; non-I2C-bus mode [2] 6.5 - VP V VEN = 8.5 V [3] - 10 70 µA - 300 500 µs Start-up, shutdown and mute timing (see Figure 11) twake wake-up time time after wake-up via EN pin before first I2C-bus transmission is recognized td(mute_off) mute off delay time I2C-bus mode with slow start enabled and non-I2C-bus mode; DC load detection disabled CSVR = 22 µF [4] - 380 - ms CSVR = 10 µF [4] - 170 - ms CSVR = 22 µF [4] - 510 - ms CSVR = 10 µF [4] - 250 - ms CSVR = 22 µF [4] - 230 - ms CSVR = 10 µF [4] - 110 - ms CSVR = 22 µF [4] - 370 - ms CSVR = 10 µF [4] - 180 - ms CSVR = 22 µF [4] - 160 - ms CSVR = 10 µF [4] - 70 - ms [5] - 90 - ms [5] - 40 - ms I2C-bus mode only; DC load detection enabled; slow start enabled I2C-bus mode only; DC load detection disabled; slow start disabled I2C-bus mode only; DC load detection enabled; slow start disabled tdet(DCload) td(mute-fgain) DC load detection time I2C-bus mode only; DC load detection enabled mute to full gain delay CSVR = 22 µF time CSVR = 10 µF TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 22 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier Table 23. Characteristics …continued Refer to test circuit (see Figure 22); VP = 14.4 V; RL = 4 Ω; −40 °C < Tamb < +85 °C and −40 °C < Tj < +150 °C; unless otherwise specified. Symbol td(mute-on) Parameter Conditions Min Typ Max Unit mute to on delay time I2C-bus - 20 40 ms non-I2C-bus mode: VEN from 3.3 V to 8 V - 20 40 ms I2C-bus mode: - 20 40 ms non-I2C-bus mode: VEN from 8 V to 3.3 V - 20 40 ms on to mute in I2C-bus mode; - 0.1 1 ms on to standby in I2C-bus mode; IB2[D0] = 0; IB1[D0] = 1 to 0 - 20 40 ms on to off in I2C-bus and non-I2C-bus mode: VEN from 8 V to 0.5 V - 0.1 1 ms CSVR = 22 µF - 1000 - ms CSVR = 10 µF - 440 - ms CSVR = 22 µF - 1100 - ms CSVR = 10 µF - 530 - ms CSVR = 22 µF - 810 - ms CSVR = 10 µF - 370 - ms CSVR = 22 µF - 940 - ms CSVR = 10 µF - 450 - ms mode: IB2[D0] = 1 to 0 td(slow_mute) slow mute delay time IB2[D0] = 0 to 1; IB2[D2] = 0 td(fast_mute) fast mute delay time IB2[D2] = 1; IB2[D0] = 0 to 1 t(on-SVR) time from amplifier switch-on to SVR above VP / 2 via I2C-bus (IB1[D0]) to DB3[D4] = 1 (SVR above VP / 2); I2C-bus mode with slow start enabled; DC load detection disabled I2C-bus mode only; DC load detection enabled; slow start enabled. I2C-bus mode only; DC load detection disabled; slow start disabled I2C-bus mode only; DC load detection enabled; slow start disabled I2C-bus interface and 1 Ω selection[6] VIL(SCL) LOW-level input voltage on pin SCL - - 1.5 V VIL(SDA) LOW-level input voltage on pin SDA - - 1.5 V VIH(SCL) HIGH-level input voltage on pin SCL 2.3 - 5.5 V TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 23 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier Table 23. Characteristics …continued Refer to test circuit (see Figure 22); VP = 14.4 V; RL = 4 Ω; −40 °C < Tamb < +85 °C and −40 °C < Tj < +150 °C; unless otherwise specified. Symbol Parameter VIH(SDA) HIGH-level input voltage on pin SDA VOL(SDA) LOW-level output voltage on pin SDA fclk clock frequency V1OHM I1OHM ISCL ISDA IADS1 IADS2 voltage on pin 1OHM current on pin 1OHM current on pin SCL current on pin SDA current on pin ADS1 current on pin ADS2 Conditions Iload = 5 mA mono channel mode [7] Min Typ Max Unit 2.3 - 5.5 V - - 0.4 V - 400 - kHz 2.5 - VP V dual channel mode 0 - 1.5 V V1OHM = 1.5 V - 130 200 µA V1OHM = 5.5 V - - 5 µA VSCL = 1.5 V - - 5 µA VSCL = 5.5 V - - 5 µA VSDA = 1.5 V - - 5 µA VSDA = 5.5 V - - 5 µA ADS1 pin connected to GND - 300 400 µA ADS1 pin connected via 33 kΩ to GND - 70 100 µA ADS2 pin connected to GND - 300 400 µA ADS2 pin connected via 33 kΩ to GND - 70 100 µA Diagnostic VOL(DIAG) LOW-level output voltage on pin DIAG fault condition; IDIAG = 1 mA - - 0.3 V VOL(CLIP) LOW-level output voltage on pin CLIP TH version only; clip or temperature pre-warning active; ICLIP = 1 mA - - 0.3 V ILIH(CLIP) HIGH-level input diagnostic, clip or temperature leakage current on pin pre-warning not activated CLIP - - 2 µA ILIH(DIAG) HIGH-level input diagnostic, clip or temperature leakage current on pin pre-warning not activated DIAG - - 2 µA Vth(offset) threshold voltage for offset detection 1.0 1.5 2.0 V THDCLIP7 7 % clip detection level (THD) I2C-bus mode: IB2[D7] = 1 [8] - 7 - % THDCLIP3 3 % clip detection level (THD) I2C-bus mode: IB2[D7] = 0 and non-I2C-bus mode [8] - 3 - % Tj(AV)(warn1) average junction temperature for pre-warning 1 I2C-bus mode: IB3[D4] = 0 and non-I2C-bus mode - 145 - °C Tj(AV)(warn2) average junction temperature for pre-warning 2 I2C-bus mode: IB3[D4] = 1 - 122 - °C TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 24 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier Table 23. Characteristics …continued Refer to test circuit (see Figure 22); VP = 14.4 V; RL = 4 Ω; −40 °C < Tamb < +85 °C and −40 °C < Tj < +150 °C; unless otherwise specified. Symbol Parameter Tj(AV)(G(−0.5dB)) ∆Tj(warn1-mute) Conditions Min Typ Max Unit average junction Vi = 0.05 V temperature for 0.5 dB gain reduction - 155 - °C difference in junction temperature between pre-warning 1 and mute - 10 - °C ∆Tj(G(−0.5-40dB)) difference in junction temperature between 0.5 dB and 40 dB gain reduction - 20 - °C Tj(AV)(off) average junction temperature for off - 175 185 °C Zth(load) load detection threshold impedance amplifier DC load detection; I2C-bus mode only: RPROG = 1500 Ω/1 % - - 25 Ω line driver DC load detection; I2C-bus mode only: RPROG = 1500 Ω/1 % 120 - 500 Ω 5 - - kΩ AC load bit is set; I2C-bus mode only: RPROG = 1500 Ω/1 %; Tj > 0 °C 320 - - mA AC load bit is not set; I2C-bus mode only: RPROG = 1500 Ω/1 %; Tj > 0 °C - - 200 mA open load DC load detection; I2C-bus mode only: RPROG = 1500 Ω/1 % IoM peak output current TDA1566_2 Product data sheet [9] © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 25 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier Table 23. Characteristics …continued Refer to test circuit (see Figure 22); VP = 14.4 V; RL = 4 Ω; −40 °C < Tamb < +85 °C and −40 °C < Tj < +150 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit output power RL = 4 Ω; VP = 14.4 V; THD = 0.5 % - 23 - W RL = 4 Ω; VP = 14.4 V; THD = 3 % - 24 - W RL = 4 Ω; VP = 14.4 V; THD = 10 % 24 29 - W RL = 4 Ω; VP = 14.4 V maximum power; Vi = 2 V (RMS) square wave 40 45 - W RL = 4 Ω; VP = 15.2 V maximum power; Vi = 2 V (RMS) square wave 45 50 - W RL = 2 Ω; VP = 14.4 V; THD = 0.5 % - 38 - W RL = 2 Ω; VP = 14.4 V; THD = 3 % - 41 - W RL = 2 Ω; VP = 14.4 V; THD = 10 % 39 50 - W RL = 2 Ω; VP = 14.4 V maximum power; Vi = 2 V (RMS) square wave 67 75 - W RL = 1 Ω; VP = 14.4 V; THD = 0.5 % - 74 - W RL = 1 Ω; VP = 14.4 V; THD = 3 % - 81 - W RL = 1 Ω; VP = 14.4 V; THD = 10 % 78 92 - W RL = 1 Ω; VP = 14.4 V maximum power; Vi = 2 V (RMS) square wave 130 150 - W Po = 1 W to 12 W; f = 1 kHz; RL = 4 Ω - 0.005 0.1 % Po = 1 W to 12 W; f = 1 kHz; RL = 2 Ω - 0.01 0.2 % Po = 1 W to 12 W; f = 1 kHz; RL = 1 Ω - 0.02 Po = 1 W to 12 W; f = 10 kHz; measured with 30 kHz filter; RL = 4 Ω - 0.1 0.3 % Po = 1 W to 12 W; f = 10 kHz; measured with 30 kHz filter; RL = 2 Ω - 0.2 0.6 % line driver mode; Vo =1 V (RMS) and 5 V (RMS); f = 20 Hz to 20 kHz; RL = 400 Ω - 0.02 0.1 % Amplifier Po THD total harmonic distortion TDA1566_2 Product data sheet % © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 26 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier Table 23. Characteristics …continued Refer to test circuit (see Figure 22); VP = 14.4 V; RL = 4 Ω; −40 °C < Tamb < +85 °C and −40 °C < Tj < +150 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit αcs channel separation f = 1 kHz to 10 kHz; Rs = 2 kΩ 42 55 - dB SVRR supply voltage rejection ratio f = 100 Hz to 10 kHz; Rs = 2 kΩ; Vripple = 2 V (p-p) 45 70 - dB CMRR common-mode rejection ratio amplifier mode; Vcm = 0.3 V (p-p); f = 1 kHz to 3 kHz; Rs = 2 kΩ 60 70 - dB Vcm(max)(rms) maximum common-mode voltage (RMS value) f = 1 kHz; Vi = 0.5 V (RMS); amplifier mode - - 1 V f = 1 kHz; Vi = 1.6 V (RMS); line driver mode - - 0.6 V RMS noise output voltage line driver mode; filter 20 Hz to 22 kHz; Rs = 2 kΩ - 20 50 µV amplifier mode; filter 20 Hz to 22 kHz; Rs = 2 kΩ - 50 70 µV mute mode; filter 20 Hz to 22 kHz; Rs = 2 kΩ - 20 50 µV Vn(o)(RMS) Gv(amp) voltage gain amplifier mode (VOUT1+ − VOUT1−) / (VIN1+ − VIN1−) 25 26 27 dB Gv(ld) voltage gain line driver (VOUT1+ − VOUT1−) / mode (VIN1+ − VIN1−) 15 16 17 dB Zi(sym) symmetrical input impedance C = 470 nF 44 60 - kΩ αmute mute attenuation f = 1 kHz; Vi = 1 V (RMS) - 80 - dB power bandwidth −1 dB; C = 2.2 µF - 20 to 20000 - Hz Bp [1] [10] [11] Operation above 16 V with a 2 Ω or 1 Ω mode with reactive load can trigger the amplifier protection. The amplifier switches off and will restart after 8 ms resulting in an ‘audio hole’. [2] If the EN pin is connected with VP a series resistance of 10 kΩ is necessary for load dump robustness. [3] If the EN pin is left unconnected the amplifier will be switched off. [4] The mute release is initiated when the SVR voltage increases above 3.5 V typical. Mute release is defined as the moment when the output signal has reached 10 % of the expected amplitude. [5] Mute release is defined as the moment when the output signal has reached 10 % of the expected amplitude (Gv × Vi). Full gain is defined as the moment when the output signal has reached 90 % of the expected amplitude (Gv × Vi). [6] Standard I2C-bus spec: maximum LOW level = 0.3 × VDD, minimum HIGH level = 0.7 × VDD. To comply with 5 V and 3.3 V logic the maximum LOW level is defined with VDD = 5 V and the minimum HIGH level with VDD = 3.3 V. [7] If the 1 Ω pin is connected with VP a series resistance of 10 kΩ is necessary for load dump robustness. [8] Clip detect is not operational for VP < 10 V. [9] If an open load is detected the amplifier is switched in line driver mode. [10] Rs is the total differential source resistance. −3 dB cut-off frequency is given as 1 1 ------------------------------ = ------------------------------------------------------------------ = 19 Hz assuming worst case low input resistance and 20 % spread in Ci. 2π × R i × C i 2π × 22 kΩ × 470 nF × 0.8 [11] Power bandwidth can be limited by the −3 dB cut-off frequency, see Table note 10. TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 27 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier 9.1 Performance diagrams All graphs Tamb = 25 °C. 001aad019 102 THD (%) 001aad020 10 THD (%) 10 1 1 10−1 10−1 (1) 10−2 10−2 10−3 10−1 (1) (2) (2) (3) 1 102 10 10−3 10 102 103 104 Po (W) 105 f (Hz) RL = 4 Ω; 80 kHz measurement filter. RL = 4 Ω; 80 kHz measurement filter. (1) f = 10 kHz. (1) Po = 1 W. (2) f = 1 kHz. (2) Po = 10 W. (3) f = 100 Hz. Fig 12. THD as a function of output power Fig 13. THD as a function of frequency 001aad021 10 001aad022 0 SVRR (dB) THD (%) 1 −20 10−1 −40 10−2 −60 10−3 −80 10−4 10−1 1 102 10 operating −100 10 102 103 Vo(rms) (V) 105 f (Hz) RL = 100 Ω; 80 kHz measurement filter; f = 1 kHz. Fig 14. THD as a function of output voltage in line driver mode Rs = 1 kΩ; CSVR = 10 µF. Fig 15. SVRR as a function of frequency (operating) TDA1566_2 Product data sheet 104 © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 28 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier 001aad023 0 SVRR (dB) −20 001aad024 −50 αcs (dB) mute (1), (2) −60 (3) −40 −70 −60 −80 −80 −90 (3) (1) −100 10 102 103 104 105 (2) −100 10 102 103 104 105 f (Hz) f (Hz) Rs = 1 kΩ; CSVR = 10 µF. (1) Rs = 0 Ω. (2) Rs = 1 kΩ. (3) Rs = 10 kΩ. Fig 16. SVRR as a function of frequency (mute) Fig 17. Channel separation as a function of frequency TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 29 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier 9.2 PCB layout S G + S C n 5 D L d V A external I2C supply top 10 µF inputs TDA3664 + gnd + 1 in IN2 + 470 nF Sgnd 470 nF − IN1 R legacy/I2C 1.5 kΩ 1% 1 µF − prog monitor +Vp + 2200 µF 2− Rs 2+ Zobel 22 + µF 1− Zobel 1+ 33 kΩ R temperature/clip LED output ADS1 ADS2 Vp 10 kΩ 1.5 kΩ 3.6 V enable Jp I2C D0 D2 legacy input unbalanced D6 address select GND sense device off device operating D4 legacy input balanced mode select GND 26 dB LED 470 nF SVR + external supply diagnostic 470 nF − I2C/gain in legacy 16 dB/I2C load detection Vp supply device mute legacy mode control TDA1566TH stereo NXP Semiconductors SRK ver. 1e 001aad688 Fig 18. PCB layout TDA1566TH, components top TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 30 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier top 1 24 12 13 001aad696 Fig 19. PCB layout TDA1566TH, components bottom TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 31 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier ADS1 SDA S2 SCL X2 S7 GND +5VA 1 GND EXT-I2C OUT2+ R2 + C6 + C9 J1 C10 OUT2− 1 OUT1+ VP OUT1− J8 1 APPL-BOARD-TDA1566J-DB527 7322-448-07651 C11 IN1+ J9 1 IN1+DC 1 C12 IN1−DC IN2+ C13 IN2+DC IN2− C14 IN2−DC IN1− X1 SGND C7 + C15 VP S4 S6 V1 S1 R9 R1 S5 J7 1 GND EN SVR DIAG/CLIP GND PROG 1E 001aad689 Fig 20. PCB layout TDA1566J, components top TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 32 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier A1 R6 C8 C5 R8 R7 R4 001aad708 Fig 21. PCB layout TDA1566J, components bottom TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 33 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier 10. Test information +5 V 2200 µF (4) 220 nF (1) VP ADS2 ADS1 SDA SCL VP1 VP2 8 9 6 5 14 23 10 kΩ 22 PROG (2) 10 kΩ 13 CLIP EN 7 STAND-BY /MUTE (3) SELECT DIAGNOSTIC /CLIP DETECT I 2 C-BUS 1 DIAG 0.5Rs 0.5Vin 0.5Vin 470 nF 470 nF C 0.5Rs 470 nF 0.5Vin 0.5Rs 16 OUT1+ MUTE 26 dB/ 16 dB C 0.5Rs 0.5Vin IN1+ 10 IN1− 11 IN2+ 2 19 OUT2+ MUTE 26 dB/ 16 dB 21 OUT2− RL PROTECTION /DIAGNOSTIC VP IN2− 3 RL PROTECTION /DIAGNOSTIC MUTE C 470 nF 18 OUT1− MUTE C Vcm TDA1566TH 4 12 17 20 24 15 SVR SGND PGND1 PGND2 TAB 1OHM 22 µF 001aad015 (1) The 220 nF capacitor should be placed close to the VP and PGND pins of the IC. (2) In non-I2C-bus mode the PROG pin should be left unconnected for 26 dB gain selection or connected via a resistor of 1500 Ω to GND for 16 dB gain selection. (3) CLIP is not available in the DBS27P version. (4) In non-I2C-bus mode (ADS1 pin connected to GND) and balanced input source (ADS2 pin connected to GND) selected. ADS2 is not available in DBS27P version. Fig 22. Non-I2C-bus mode (26 dB gain) TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 34 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier 2200 µF 220 nF (1) connected to microcontroller (4) VP +5 V ADS2 ADS1 SDA SCL VP1 VP2 8 9 6 5 14 23 10 kΩ 22 PROG (2) RPROG 1500 Ω (1 %) 13 CLIP connected to microcontroller EN 7 STAND-BY /MUTE (3) SELECT DIAGNOSTIC /CLIP DETECT I 2 C-BUS 1 DIAG 0.5Rs 0.5Vin 0.5Vin 470 nF 470 nF C 0.5Rs 470 nF 0.5Vin 0.5Rs 16 OUT1+ MUTE 26 dB/ 16 dB C 0.5Rs 0.5Vin IN1+ 10 IN1− 11 PROTECTION /DIAGNOSTIC MUTE IN2+ 2 19 OUT2+ MUTE 26 dB/ 16 dB C 470 nF RL 21 OUT2− PROTECTION /DIAGNOSTIC VP IN2− 3 RL 18 OUT1− MUTE C Vcm TDA1566TH 4 12 17 20 24 15 SVR SGND PGND1 PGND2 TAB 1OHM 22 µF 001aad016 (1) The 220 nF capacitor should be placed close to the VP and PGND pins of the IC. (2) RPROG defines the trip levels for the AC and DC load detection. (3) CLIP is not available in DBS27P version. (4) I2C-bus mode is selected with ADS1 open. ADS2 is not available in DBS27P version. Fig 23. I2C-bus mode TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 35 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier +5 V 2200 µF (4) 220 nF (1) VP ADS2 ADS1 SDA SCL VP1 VP2 8 9 6 5 14 23 10 kΩ 22 PROG (2) 10 kΩ 13 CLIP EN 7 STAND-BY /MUTE (3) SELECT DIAGNOSTIC /CLIP DETECT I 2 C-BUS 1 DIAG 0.5Rs 0.5Vin 470 nF IN1+ 10 16 OUT1+ MUTE 26 dB/ 16 dB C 0.5Vin 470 nF 0.5Rs C 470 nF IN1− 11 MUTE IN2+ 2 19 OUT2+ MUTE 26 dB/ 16 dB 21 OUT2− PROTECTION /DIAGNOSTIC VP IN2− 3 RL 1Ω PROTECTION /DIAGNOSTIC C 470 nF 18 OUT1− MUTE C Vcm TDA1566TH 4 12 17 20 24 15 SVR SGND PGND1 PGND2 TAB 1OHM 22 µF 10 kΩ 001aad017 connected to VP (1) The 220 nF capacitor should be placed close to the VP and PGND pins of the IC. (2) In non-I2C-bus mode the PROG pin should be left unconnected for 26 dB gain selection or connected via a resistor of 1500 Ω to GND for 16 dB gain selection. (3) CLIP is not available in the DBS27P version. (4) In non-I2C-bus mode (ADS1 pin connected to GND) and balanced input source (ADS2 pin connected to GND) selected. ADS2 is not available in DBS27P version. Fig 24. Non-I2C-bus mode (1 Ω mode and 26 dB gain) TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 36 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier 2200 µF 220 nF (1) connected to microcontroller (4) VP +5 V ADS2 ADS1 SDA SCL VP1 VP2 8 9 6 5 14 23 10 kΩ 22 PROG (2) RPROG 1500 Ω (1 %) 13 CLIP connected to microcontroller EN 7 STAND-BY /MUTE (3) SELECT DIAGNOSTIC /CLIP DETECT I 2 C-BUS 1 DIAG 0.5Rs 0.5Vin 0.5Vin 0.5Rs 470 nF IN1+ 10 16 OUT1+ MUTE 26 dB/ 16 dB C 470 nF IN1− 11 18 OUT1− RL 1Ω PROTECTION /DIAGNOSTIC MUTE C 470 nF IN2+ 2 19 OUT2+ MUTE 26 dB/ 16 dB C 470 nF 21 OUT2− PROTECTION /DIAGNOSTIC VP IN2− 3 MUTE C Vcm TDA1566TH 4 12 17 20 24 15 SVR SGND PGND1 PGND2 TAB 1OHM 22 µF 10 kΩ 001aad018 connected to VP (1) The 220 nF capacitor should be placed close to the VP and PGND pins of the IC. (2) RPROG defines the trip levels for the AC and DC load detection. (3) CLIP is not available in the DBS27P version. (4) I2C-bus mode is selected with ADS1 open. ADS2 is not available in DBS27P version. Fig 25. I2C-bus mode (1 Ω mode) TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 37 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier 11. Package outline HSOP24: plastic, heatsink small outline package; 24 leads; low stand-off height SOT566-3 E D A x X c E2 y HE v M A D1 D2 12 1 pin 1 index Q A A2 E1 (A3) A4 θ Lp detail X 24 13 Z w M bp e 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A A2 max. 3.5 3.5 3.2 A3 0.35 A4(1) D1 D2 E(2) E1 E2 e HE Lp Q +0.08 0.53 0.32 16.0 13.0 −0.04 0.40 0.23 15.8 12.6 1.1 0.9 11.1 10.9 6.2 5.8 2.9 2.5 1 14.5 13.9 1.1 0.8 1.7 1.5 bp c D(2) v w x y 0.25 0.25 0.03 0.07 Z θ 2.7 2.2 8° 0° Notes 1. Limits per individual lead. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 03-02-18 03-07-23 SOT566-3 Fig 26. Package outline SOT566-3 (HSOP24) TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 38 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier DBS27P: plastic DIL-bent-SIL (special bent) power package; 27 leads (lead length 6.8 mm) SOT827-1 non-concave Dh x D Eh view B: mounting base side A2 d B j E A L4 L3 L 1 L2 27 e1 Z w M bp e c Q v M e2 m 0 10 20 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A2 mm 19 4.65 0.60 4.35 0.45 bp c 0.5 0.3 D(1) d 29.2 25.8 28.8 25.4 Dh E(1) e e1 e2 Eh j L L2 12 15.9 15.5 2 1 4 8 3.4 3.1 6.8 3.9 3.1 L3 L4 1.15 22.9 0.85 22.1 m Q v w 4 2.1 1.8 0.6 x 0.25 0.03 Z(1) 1.8 1.2 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT827-1 --- --- --- EUROPEAN PROJECTION ISSUE DATE 03-07-29 Fig 27. Package outline SOT827-1 (DBS27P) TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 39 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier 12. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling integrated circuits. 13. Soldering 13.1 Introduction There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 13.2 Through-hole mount packages 13.2.1 Soldering by dipping or by solder wave Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 13.2.2 Manual soldering Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 °C and 400 °C, contact may be up to 5 seconds. 13.3 Surface mount packages 13.3.1 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 28) than a PbSn process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 40 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 24 and 25 Table 24. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) ≥ 350 < 350 < 2.5 235 220 ≥ 2.5 220 220 Table 25. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 28. temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 28. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 41 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier 13.3.2 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 13.3.3 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 °C and 320 °C. 13.4 Package related soldering information Table 26. Suitability of IC packages for wave, reflow and dipping soldering methods Mounting Through-hole mount Through-hole-surface mount Package[1] Soldering method Wave Reflow[2] Dipping CPGA, HCPGA suitable − − DBS, DIP, HDIP, RDBS, SDIP, SIL suitable[3] − suitable PMFP[4] not suitable not suitable − TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 42 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier Table 26. Suitability of IC packages for wave, reflow and dipping soldering methods …continued Mounting Package[1] Soldering method Wave Surface mount HTSSON..T[5], not suitable BGA, LBGA, LFBGA, SQFP, SSOP..T[5], TFBGA, VFBGA, XSON Reflow[2] Dipping suitable − DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable[6] suitable − PLCC[7], SO, SOJ suitable suitable − not recommended[7][8] suitable − SSOP, TSSOP, VSO, VSSOP not recommended[9] suitable − CWQCCN..L[10], not suitable not suitable − LQFP, QFP, TQFP WQCCN..L[10] [1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your NXP Semiconductors sales office. [2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). [3] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. [4] Hot bar soldering or manual soldering is suitable for PMFP packages. [5] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. [6] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [7] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. [8] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [9] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [10] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 43 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier 14. Revision history Table 27. Revision history Document ID Release date Data sheet status Change notice Supersedes TDA1566_2 20070820 Product data sheet - TDA1566_1 Modifications: TDA1566_1 (9397 750 15043) • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Table 23 “Characteristics” changed values for CMRR, Po and THD 20060405 Product data sheet TDA1566_2 Product data sheet - - © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 44 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 16. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] TDA1566_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 20 August 2007 45 of 46 TDA1566 NXP Semiconductors I2C-bus controlled dual channel/single channel amplifier 17. Contents 1 2 3 4 5 5.1 5.2 6 6.1 6.1.1 6.1.2 6.1.2.1 6.1.2.2 6.1.3 6.1.4 6.1.5 6.1.6 6.2 6.2.1 6.2.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.4 6.4.1 6.4.2 6.4.3 6.5 6.5.1 6.5.2 7 8 9 9.1 9.2 10 11 12 13 13.1 13.2 13.2.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 7 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . 7 Gain selection . . . . . . . . . . . . . . . . . . . . . . . . . . 8 I2C-bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Non-I2C-bus mode . . . . . . . . . . . . . . . . . . . . . . 8 Balanced and unbalanced input sources . . . . . 9 Single channel 1 W operation. . . . . . . . . . . . . . 9 Mute speed setting . . . . . . . . . . . . . . . . . . . . . 10 Pins with double functions . . . . . . . . . . . . . . . 10 Load identification (I2C-bus mode only) . . . . . 10 DC load detection . . . . . . . . . . . . . . . . . . . . . . 10 AC load detection . . . . . . . . . . . . . . . . . . . . . . 11 Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Diagnostic table . . . . . . . . . . . . . . . . . . . . . . . 12 Diagnostic level settings . . . . . . . . . . . . . . . . . 13 Temperature pre-warning . . . . . . . . . . . . . . . . 13 Speaker protection . . . . . . . . . . . . . . . . . . . . . 14 Offset detection. . . . . . . . . . . . . . . . . . . . . . . . 14 I2C-bus operation . . . . . . . . . . . . . . . . . . . . . . 15 I2C-bus address with hardware address select 15 Instruction bytes . . . . . . . . . . . . . . . . . . . . . . . 16 Data bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Timing waveforms. . . . . . . . . . . . . . . . . . . . . . 17 Start-up and shutdown . . . . . . . . . . . . . . . . . . 17 Engine start . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 19 Thermal characteristics. . . . . . . . . . . . . . . . . . 21 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 21 Performance diagrams . . . . . . . . . . . . . . . . . . 28 PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Test information . . . . . . . . . . . . . . . . . . . . . . . . 34 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 38 Handling information. . . . . . . . . . . . . . . . . . . . 40 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Through-hole mount packages . . . . . . . . . . . . 40 Soldering by dipping or by solder wave . . . . . 40 13.2.2 13.3 13.3.1 13.3.2 13.3.3 13.4 14 15 15.1 15.2 15.3 15.4 16 17 Manual soldering . . . . . . . . . . . . . . . . . . . . . . Surface mount packages . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Manual soldering . . . . . . . . . . . . . . . . . . . . . . Package related soldering information . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 40 40 42 42 42 44 45 45 45 45 45 45 46 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 20 August 2007 Document identifier: TDA1566_2