PHILIPS TDF8599TH

TDF8599
I2C-bus controlled dual channel 43 W/2 Ω single channel
85 W/1 Ω class-D power amplifier with load diagnostics
Rev. 01 — 13 November 2008
Product data sheet
1. General description
The TDF8599 is a dual Bridge-Tied Load (BTL) car audio amplifier comprising an
NDMOST-NDMOST output stage based on SOI BCDMOS technology. Low dissipation
enables the TDF8599 high-efficiency, class-D amplifier to be used with a smaller heat sink
than those normally used with standard class-AB amplifiers.
The TDF8599 can operate in either non-I2C-bus mode or I2C-bus mode. When in I2C-bus
mode, DC load detection results and fault conditions can be easily read back from the
device. Up to five I2C-bus addresses can be selected when an external resistor is
connected to pin ADS.
When pin ADS is short circuited to ground, the TDF8599 operates in non-I2C-bus mode.
Switching between Operating mode and Mute mode in non-I2C-bus mode is only possible
using pins EN and SEL_MUTE.
2. Features
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
High-efficiency
Low quiescent current
Operating voltage from 8 V to 18 V
Two 4 Ω/2 Ω capable BTL channels or one 1 Ω capable BTL channel
Differential inputs
Supports I2C-bus mode with five I2C-bus addresses or non-I2C-bus mode operation
Clip detect
Independent short circuit protection for each channel
Advanced short circuit protection for load, GND and supply
Load dump protection
Thermal foldback and thermal protection
DC offset protection
Selectable AD or BD modulation
Parallel channel mode for high current drive capability
Advanced clocking:
u Switchable oscillator clock source: internal (master) or external (slave)
u Spread spectrum mode
u Phase staggering
u Frequency hopping
n No ‘pop noise’ caused by DC output offset voltage
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
n I2C-bus mode:
u DC load detection
u AC load detection
u Thermal pre-warning diagnostic level setting
u Identification of activated protections or warnings
u Selectable diagnostic information available using pin DIAG
n Qualified in accordance with AEC-Q100
3. Applications
n Car audio applications
4. Quick reference data
Table 1.
Quick reference data
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
General; Vp = 14.4 V
VP
supply voltage
8
14.4
18
V
Istb
standby current
voltage on pin EN < 0.8 V
-
-
10
µA
Iq(tot)
total quiescent current
Operating mode; no load, snubbers and
filter connected
-
90
120
mA
18
20
-
W
THD = 10 %; RL = 4 Ω
24
26
-
W
square wave (EIAJ); RL = 4 Ω
-
40
-
W
THD = 1 %; RL = 2 Ω
29
32
-
W
THD = 10 %; RL = 2 Ω
39
43
-
W
square wave (EIAJ); RL = 2 Ω
-
70
-
W
-
85
-
W
Dual BTL channel; Vp = 14.4 V
output power
Po
Stereo mode;
THD = 1 %; RL = 4 Ω
[1]
Parallel mode
THD = 10 %; RL = 1 Ω
[1]
[1]
Output power is measured indirectly based on RDSon measurement.
5. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
Version
TDF8599TH
HSOP36
plastic, heatsink small outline package; 36 leads; low stand-off height
SOT851-2
TDF8599TD
HSOP36
plastic, heatsink small outline package; 36 leads; low stand-off height
SOT938-1
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
2 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
6. Block diagram
VDDA
10
AGND
SVRR
VP1
VP2
31
24
34
STABI1
9
32
8
VP1
33
PWM
CTRL
1
OUT1N
DRIVER
LOW
PGND1
29
VP1
IN1N
BOOT1N
DRIVER
HIGH
TDF8599
IN1P
VSTAB1
2
BOOT1P
DRIVER
HIGH
28
PWM
CTRL
OUT1P
DRIVER
LOW
ACGND
PGND1
5
+
23
BOOT2N
VP2
DRIVER
HIGH
22
PWM
CTRL
IN2P
3
PGND2
26
VP2
IN2N
OUT2N
DRIVER
LOW
4
BOOT2P
DRIVER
HIGH
27
PWM
CTRL
OUT2P
DRIVER
LOW
OSCSET
OSCIO
SSM
MOD
VDDD
EN
SEL_MUTE
SCL
SDA
ADS
18
PGND2
19
17
OSCILLATOR
12
35
5 V STABI
16
15
MODE
SELECT
+
I2C-BUS
DIAGNOSTICS
PROTECTIONS
OVP, OCP, OTP
UVP, TF, WP,DCP
11
GNDD/HW
14
DIAG
13
20
CLIP DCP
30
25
PGND1
PGND2
001aai766
Block diagram
TDF8599_1
Product data sheet
VSTAB2
6
7
36
Fig 1.
21
STABI2
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
3 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
7. Pinning information
7.1 Pinning
GNDD/HW 36
1
IN1P
VDDD 35
2
IN1N
VSTAB1 34
3
IN2P
OUT1N 33
4
IN2N
BOOT1N 32
5
ACGND
VP1 31
6
EN
PGND1 30
7
SEL_MUTE
BOOT1P 29
8
SVRR
OUT1P 28
9
AGND
OUT2P 27
TDF8599TH
BOOT2P 26
10 VDDA
11 ADS
PGND2 25
12 MOD
VP2 24
13 CLIP
BOOT2N 23
14 DIAG
OUT2N 22
15 SDA
VSTAB2 21
16 SCL
DCP 20
17 SSM
18 OSCSET
OSCIO 19
001aai767
Fig 2.
Heatsink up (top view) pin configuration TDF8599TH
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
4 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
IN1P
1
36 GNDD/HW
IN1N
2
35 VDDD
IN2P
3
34 VSTAB1
IN2N
4
33 OUT1N
ACGND
5
32 BOOT1N
EN
6
31 VP1
SEL_MUTE
7
30 PGND1
SVRR
8
29 BOOT1P
AGND
9
28 OUT1P
TDF8599TD
VDDA 10
27 OUT2P
ADS 11
26 BOOT2P
MOD 12
25 PGND2
CLIP 13
24 VP2
DIAG 14
23 BOOT2N
SDA 15
22 OUT2N
SCL 16
21 VSTAB2
SSM 17
20 DCP
OSCSET 18
19 OSCIO
001aai768
Fig 3.
Heatsink down (top view) pin configuration TDF8599TD
7.2 Pin description
Table 3.
Pin description
Symbol
Pin
Type[1]
Description
IN1P
1
I
channel 1 positive audio input
IN1N
2
I
channel 1 negative audio input
IN2P
3
I
channel 2 positive audio input
IN2N
4
I
channel 2 negative audio input
ACGND
5
I
decoupling for input reference voltage
EN
6
I
enable input:
non-I2C-bus mode: switch between off and Mute mode
I2C-bus mode: off and Standby mode
SEL_MUTE
7
I
select mute or on (unmute)
SVRR
8
I
decoupling for internal half supply reference voltage
AGND
9
G
analog supply ground
VDDA
10
P
analog supply voltage
ADS
11
I
non-I2C-bus mode: connected to ground
I2C-bus mode: selection and address selection pin
MOD
12
I
modulation mode, phase shift and parallel mode select
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
5 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
Table 3.
Pin description …continued
Symbol
Pin
Type[1]
Description
CLIP
13
O
clip output; open-drain
DIAG
14
O
diagnostic output; open-drain
SDA
15
I/O
I2C-bus data input and output
SCL
16
I
I2C-bus clock input
SSM
17
master setting: Spread spectrum mode frequency
slave setting: phase lock operation
OSCSET
18
master/slave setting oscillator
master only setting: set internal oscillator frequency
OSCIO
19
I/O
external oscillator slave setting: input
internal oscillator master setting: output
DCP
20
I
DC protection input for the filtered output voltages
VSTAB2
21
OUT2N
22
BOOT2N
23
VP2
24
P
channel 2 power supply voltage
PGND2
25
G
channel 2 power ground
BOOT2P
26
OUT2P
27
O
channel 2 positive PWM output
OUT1P
28
O
channel 1 positive PWM output
BOOT1P
29
PGND1
30
G
channel 1 power ground
VP1
31
P
channel 1 power supply voltage
BOOT1N
32
OUT1N
33
decoupling internal stabilizer 2 for DMOST drivers
O
channel 2 negative PWM output
boot 2 negative bootstrap capacitor
boot 2 positive bootstrap capacitor
boot 1 positive bootstrap capacitor
boot 1 negative bootstrap capacitor
O
channel 1 negative PWM output
VSTAB1
34
decoupling internal stabilizer 1 for DMOST drivers
VDDD
35
decoupling of the internal 5 V logic supply
GNDD/HW
36
G
ground digital supply voltage
handle wafer connection
[1]
I = input, O = output, I/O = input/output, G = ground and P = power supply.
8. Functional description
8.1 General
The TDF8599 is a dual full bridge (BTL) audio power amplifier utilizing class-D technology.
The audio input signal is converted into a Pulse-Width Modulated (PWM) signal using the
analog input and PWM control stages. A PWM signal is applied to driver circuits for both
high-side and low-side enabling the DMOS power output transistors to be driven. An
external 2nd order low-pass filter converts the PWM signal into an analog audio signal
across the loudspeakers.
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
6 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
The TDF8599 includes integrated common circuits for all channels such as the oscillator,
all reference sources, mode functionality and a digital timing manager. In addition, the
built-in protection includes thermal foldback, temperature, overcurrent and overvoltage
(load dump).
The TDF8599 operates in either I2C-bus mode or non-I2C-bus mode. In I2C-bus mode,
DC load detection, frequency hopping and extended configurability are provided together
with enhanced diagnostic information.
8.2 Mode selection
The mode pins EN and SEL_MUTE enable mute state, I2C-bus mode and Operating
mode switching.
Pin SEL_MUTE is used to mute and demute the device and must be connected to an
external capacitor. This capacitor generates a time constant which is used to ensure
smooth fade-in and fade-out of the input signal.
When pin EN is LOW, the TDF8599 is off and the supply current is at its lowest value
(typically 2 µA). When off, the TDF8599 is completely deactivated and will not react to
I2C-bus commands. The TDF8599 is enabled when pin EN is HIGH.
A resistor connected between pin ADS and ground determines if the TDF8599 is in
I2C-bus mode or in non-I2C-bus mode (see Section 9). I2C-bus mode is selected by
leaving the connection between pin ADS and pin GND open. In I2C-bus mode with pin EN
HIGH, the TDF8599 is in Standby mode and will wait for further commands.
Non-I2C-bus mode is selected by connecting pin ADS to pin GND. In non-I2C-bus mode,
the default TDF8599 state is Mute mode. The amplifiers switch idle (50 % duty cycle) and
the audio signal is suppressed at the output. In addition, the capacitor (CSVRR) is charged
to half the supply voltage. To enter Operating mode, pin SEL_MUTE must be released
(see Figure 4) and capacitor (CON) charged by an internal pull-up.
S2
3.3 V
S2
EN
EN
3.3 V
TDF8599
SEL_MUTE
TDF8599
SEL_MUTE
CON
CON
S1
001aai769
a. non-I2C-bus mode
Fig 4.
001aai770
b. I2C-bus mode
Mode selection
I2C-bus mode and non-I2C-bus mode control are described in Table 4 and Table 5.
Switches S1 and S2 are illustrated in Figure 4.
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
7 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
Table 4.
I2C-bus mode operation
Pin EN
Bit IB1[D0]
Bit IB2[D0]
Mode
S2 closed
1
0
Operating mode
1
1
Mute mode
0
X[1]
Standby mode
X[1]
X[1]
off
S2 open
[1]
X = do not care
Table 5.
Non-I2C-bus mode operation
Pin EN
Bit IB2[D0]
Mode
S2 closed
S1 open
Operating mode
S2 closed
Mute mode
do not care
off
S2 open
8.3 Pulse-width modulation frequency
The output signal from the amplifier is a PWM signal with a switching frequency of fosc.
This frequency is set by connecting a resistor (Rosc) between pins OSCSET and AGND.
The optimal clock frequency setting is between 300 kHz and 400 kHz. Connecting a
resistor with a value of 39 kΩ, for example, sets the clock frequency to 320 kHz. The
external capacitor (Cosc) has no influence on the oscillator frequency. It does however,
reduce jitter and sensitivity to disturbance. Using a 2nd order LC demodulation filter in the
application generates an analog audio signal across the loudspeaker.
8.3.1 Master and slave mode selection
In a master and slave configuration, multiple TDF8599 devices are daisy-chained together
in one audio application with a single device providing the clock frequency signal for the
other devices. In this situation, it is recommended that the oscillators of all devices are
synchronized for optimum EMI behavior as follows:
All OSCIO pins are connected together and one TDF8599 in the application is configured
as the clock-master. All other TDF8599 devices are configured as clock-slaves (see
Figure 6).
• The clock-master pin OSCIO is configured as the oscillator output. When a resistor
(Rosc) is connected between pins OSCSET and AGND, the TDF8599 is in Master
mode.
• The clock-slave pins OSCIO are configured as the oscillator inputs. When pin
OSCSET is directly connected to pin AGND (see Table 6), the TDF8599 is in Slave
mode.
Table 6.
Mode
Mode setting OSCIO
Settings
Pin OSCSET
Pin OSCIO
Master
Rosc > 26 kΩ
output
Slave
Rosc = 0 kΩ; shorted to AGND
input
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
8 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
The value of the resistor Rosc sets the carrier frequency based on the following formula:
9
12.45 × 10
f osc = ---------------------------- [ Hz ]
R osc
(1)
001aai771
50
Rosc
(kΩ)
40
30
20
10
0
300
Fig 5.
350
400
450
500
fosc (kHz)
Oscillator frequency as function of Rosc
OSCSET
TDF8599
OSCSET
Rosc
Cosc
TDF8599
OSCIO
Master
OSCIO
fosc
R
Slave 1
OSCSET
TDF8599
OSCIO
Slave 2
001aai772
Fig 6.
Master and slave configuration
In Master mode, Spread spectrum mode and frequency hopping can be enabled. In Slave
mode, phase staggering and phase lock operation can be selected. An external clock can
be used as the master-clock on pin OSCIO of the slave devices. When using an external
clock it must remain active during the shutdown sequence to ensure that all devices are
switched off and able to enter the off state as described in Section 8.2.
8.3.2 Spread spectrum mode (Master mode)
Spread spectrum mode is a technique of modulating the oscillator frequency with a slow
varying signal to broaden the switching spectrum, thereby reducing the spectral density of
the EMI. Connecting a capacitor (CSSM) to pin SSM enables Spread spectrum mode (see
Figure 7). When pin SSM is connected to pin AGND, Spread spectrum mode is disabled.
The capacitor on pin SSM (CSSM) sets the spreading frequency when Spread spectrum
mode is active. The current (ISSM) flowing in and out of pin SSM is typically 5 µA. This
gives a triangular voltage on pin SSM that sweeps around the voltage set by pin OSCSET
± 5 %. The voltage on pin SSM is used to modulate the oscillator frequency.
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
9 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
The spread spectrum frequency can be calculated using:
I SSM
f SSM = ------------------------------------------------------ [ Hz ]
2 × C SSM × V 1 × 10 %
(2)
where the voltage on pin OSCSET = V1 and is calculated as 100 µA × Rosc (V) with
ISSM = 5 µA.
100 µA
100 µA
OSCSET
Rosc
OSCSET
Rosc
Cosc
Cosc
5 µA
ISSM
SSM
SSM
CSSM
001aai773
001aai774
a. Off
Fig 7.
b. On
Spread spectrum mode
The frequency swings between 0.95 × fosc and 1.05 × fosc, see Figure 8.
OSCIO
max(V)
SSM
min(V)
t (ms)
001aai775
Fig 8.
Spread spectrum operation in Master mode
8.3.3 Frequency hopping (Master mode)
Frequency hopping is a technique used to change the oscillator frequency for AM tuner
compatibility. In Master mode, the resistor connected between pin OSCSET and pin
AGND sets the oscillator frequency. In I2C-bus mode, this frequency can be varied by
10 % to 0.9 × fosc or 1.1 × fosc using bit IB1[D3:D4]. See Figure 8.
8.3.4 Phase lock operation (Slave mode)
In Slave mode, phase lock operation can be used to reduce the jitter effects of the external
oscillator signal connected to pin OSCIO. Phase lock operation is also needed to enable
phase staggering, see Section 8.4.2. Phase lock operation is enabled when the oscillator
is in Slave mode by connecting two capacitors (CPLL_S and CPLL_p) and a resistor (RPLL)
between pin SSM and pin AGND (see Figure 9). Connecting pin SSM to pin AGND
disables phase lock operation and causes the slave to use the external oscillator signal
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
10 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
directly. Values for CPLL_s, CPLL_p and RPLL depend on the desired loop bandwidth
(BWPLL) of the PLL. RPLL is given by: RPLL = 8.4 × BWPLL Ω. The corresponding values for
CPLL_s and CPLL_p are given by:
0.032
C PLL_p = ------------------------------------ [ F ]
R PLL × BW PLL
(3)
Remark: CPLL_P is only needed when π/4 phase shift is selected. See Section 8.4.2 for
more detailed information.
0.8
C PLL_s = ------------------------------------ [ F ]
R PLL × BW PLL
(4)
When pin OSCIO is connected to a clock-master with Spread spectrum mode enabled,
the PLL loop bandwidth BWPLL should be 100 × fSSM.
100 µA
OSCSET
100 µA
OSCSET
PLL
SSM
CPLL_s
SSM
PLL
RPLL
001aai776
001aai777
a. Off
Fig 9.
CPLL_P(1)
b. On
Phase lock operation
See Table 7 for all oscillator modes.
Table 7.
Oscillator modes
OSCSET pin
OSCIO pin
SSM pin
Oscillator modes
Rosc > 26 kΩ
output
Cssm
master, spread spectrum
Rosc > 26 kΩ
output
shorted to AGND
master, no spread spectrum
Rosc = 0 Ω
input
CPLL + RPLL
slave, PLL enabled
Rosc = 0 Ω
input
shorted to AGND
slave, PLL disabled
8.4 Operation mode selection
Pin MOD is used to select specific operation modes. The resistor (RMOD) connected
between pins MOD and AGND determines the operation mode. The mode of operation
depends on whether non-I2C-bus mode or I2C-bus mode is active. This is in turn
determined by the resistor value connected between pins ADS and AGND.
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
11 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
In non-I2C-bus mode pin MOD is used to select:
1. AD or BD modulation type (see Section 8.4.1).
2. 1⁄2 π phase shift when oscillator is used in Slave mode (see Section 8.4.2).
3. Parallel mode operation (see Section 8.4.3).
In I2C-bus mode, pin MOD can only select Parallel mode. In addition, the modulation type
and phase shift are programmed using I2C-bus commands.
Table 8.
RMOD (kΩ)
Operation mode selection with the MOD pin
I2C-bus mode
Non-I2C-bus mode
0 (short to GND) Stereo mode
AD modulation: no phase shift in Slave mode
4.7
BD modulation: no phase shift in Slave mode
13
AD modulation: 1⁄2 π phase shift in Slave mode
33
BD modulation: 1⁄2 π phase shift in Slave mode
100
Parallel mode
AD modulation: no phase shift in Slave mode
∞ (open)
BD modulation: no phase shift in Slave mode
The information on pin MOD is latched when one of the TDF8599 outputs starts switching
to avoid incorrect information on pin MOD caused by disturbances of switching amplifier
outputs.
8.4.1 Modulation mode
In non-I2C-bus mode, pin MOD is used to select either AD or BD modulation mode. In
I2C-bus mode, the modulation mode is selected using an I2C-bus command.
• AD modulation mode: the bridge halves switch in opposite phase.
• BD modulation mode: the bridge halves switch in phase but the input signal for the
modulators is inverted.
Figure 10, Figure 11 and Figure 12 show simplified representations of AD and BD
modulation.
+VP
INxP
+VP
OUTP OUTN
INxN
AD
BD
001aai778
Fig 10. AD/BD modulation switching circuit
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
12 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
INxP
OUTxP
001aai779
a. Bridge half 1.
INxN
OUTxN
001aai780
b. Bridge half 2 switched in the opposite phase to bridge half 1.
Fig 11. AD modulation
INxP
OUTxP
OUTxP, OUTxN
001aai781
a. Phase switching cycle.
INxN
OUTxN
001aai782
b. Inverted signal to the modulator.
Fig 12. BD modulation
8.4.2 Phase staggering (Slave mode)
In Slave mode with phase lock operation enabled, a phase shift with respect to the
incoming clock signal can be selected to distribute the switching moments over time. In
non-I2C-bus mode, 1⁄2 π phase shift can be programmed using pin MOD. In I2C-bus mode,
five different phase shifts (1⁄4 π, 1⁄3 π, 1⁄2 π, 2⁄3 π, 3⁄4 π) can be selected using the I2C-bus
bits (IB3[D1:D3]). See Figure 9 for selection of the phase shift in non-I2C-bus mode with
pin MOD. An additional capacitor must be connected to pin SSM when 1⁄4 π phase shift is
used (see Figure 9). An example of using 1⁄2 π phase shift for BD modulation is shown in
Figure 13.
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
13 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
OUT1P
phase
0
OUT1N
master
OUT2P
π
OUT2N
OUT1P
1/2 π
OUT1N
slave
OUT2P
3/2 π
OUT2N
001aai783
Fig 13. Master and slave operation with 1⁄2 π phase shift.
8.4.3 Parallel mode
In Parallel mode; the two output stages operate in parallel to enlarge the drive capability.
The inputs and outputs for Parallel mode must be connected on the Printed-Circuit Board
(PCB) as shown in Figure 14. The parallel connection can be made after the output filter,
as shown in Figure 14 or directly to the device output pins.
+
−
IN1P
OUT1N
IN1N
OUT1P
−
IN2N
TDF8599
IN2P
OUT2P
MOD
OUT2N
+
RMOD
001aai784
Fig 14. Mono and Parallel modes
In Parallel mode, the channel 1 I2C-bus bits can be programmed using the I2C-bus.
However, clip detection must be deactivated by disabling clip detection for both channel 1
and channel 2.
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
14 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
8.5 Protection
The TDF8599 includes a range of built-in protection functions. How the TDF8599 handles
the various possible fault conditions differs for each protection and is described in the
following sections:
Table 9.
Overview of protection types
Protection type
Reference
Thermal foldback
Overtemperature
Overcurrent
Window
DC Offset
Undervoltage
Overvoltage
Section 8.5.1
Section 8.5.2
Section 8.5.3
Section 8.5.4
Section 8.5.5
Section 8.5.6
Section 8.5.6
8.5.1 Thermal foldback
Thermal Foldback Protection (TFP) is activated when the junction temperature exceeds
the threshold level (145 °C). TFP decreases amplifier gain such that the combination of
dissipation and Rth(j-a) create a junction temperature around the threshold level. The
device will not completely switch off but remains operational at the lower output power
levels. If the junction temperature continues to increase, a second built-in temperature
protection threshold level shuts down the amplifier completely.
8.5.2 Overtemperature protection
If the junction temperature Tj > 160 °C, the OverTemperature Protection (OTP) is activated
and the power stage immediately shuts down.
8.5.3 Overcurrent protection
OverCurrent Protection (OCP) is activated when the output current exceeds the maximum
output current of 8 A. OCP regulates the output voltage such that the maximum output
current is limited to 8 A. The amplifier outputs keep switching and the amplifier is NOT
shutdown completely. This is called current limiting.
OCP also detects when the loudspeaker terminals are short circuited or one of the
amplifier’s demodulated outputs is short circuited to one of the supply lines. In either case,
the shorted channel(s) are switched off.
The amplifier can distinguish between loudspeaker impedance drops and a low-ohmic
short across the load or one of the supply lines. This impedance threshold depends on the
supply voltage used. When a short is made across the load causing the impedance to
drop below the threshold level, the shorted channel(s) are switched off. They try to restart
every 50 ms. If the short circuit condition is still present after 50 ms, the cycle repeats. The
average dissipation will be low because of this forced reduced duty cycle.
When a channel is switched off due to a short circuit on one of the supply lines, Window
Protection (WP) is activated. WP ensures the amplifier does not start-up after 50 ms until
the supply line short circuit is removed.
TDF8599_1
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TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
8.5.4 Window protection
Window Protection (WP) checks the PWM output voltage before switching from Standby
mode to Mute mode (outputs switching) and is activated as follows:
• During the start-up sequence:
– When the TDF8599 is switched from standby to mute (td(stb-mute)). When a short
circuit on one of the output terminals (i.e. between VP and GND) is detected, the
start-up procedure is interrupted and the TDF8599 waits for open circuit outputs.
No large currents flow in the event of a short circuit to the supply lines because the
check is performed before the power stages are enabled.
• During operation:
–
A short to one of the supply lines activates OCP causing the amplifier channel to
shutdown. After 50 ms the amplifier channel restarts and WP is activated.
However, the corresponding amplifier channel will not start-up until the supply line
short circuit has been removed.
8.5.5 DC Protection
DC Protection (DCP) is activated when the DC content in the demodulated output voltage
exceeds a set threshold (typically 2 V). DCP is active in both Mute mode and Operating
mode. False triggering of the DCP by low frequencies in the audio signal is prevented
using the external capacitor (CF) to generate a cut-off frequency as shown in Figure 15.
OUT1P
OUT1N
OUT2P
OUT2N
V to I
Vref
V to I
50 kΩ
IB1[D6]
IB2[D6]
DCP
CF
DIAG
IB1[D7]
DB1[D7]
S
Q
S4
IB2[D7]
S3
switch off channels
001aai785
Fig 15. DC offset protection and diagnostic output
TDF8599_1
Product data sheet
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Rev. 01 — 13 November 2008
16 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
In I2C-bus mode, DC offsets generate a voltage shift around the bias voltage. When the
voltage shift exceeds threshold values, the offset alarm bit DB1[D2] is set and if bit
IB1[D7] is set, diagnostic information is also given. Any detected offset shuts down both
channels when bit IB2[D7] is not set. To restart the TDF8599 in I2C-bus mode, pin EN
must be toggled or DCP disabled by connecting pin DCP to pin GND.
In non-I2C-bus mode, when an offset is detected, DCP always gives diagnostic
information on pin DIAG and shuts down both channels. Connecting pin DCP to pin GND
disables DCP.
8.5.6 Supply voltages
UnderVoltage Protection (UVP) is activated when the supply voltage drops below the UVP
threshold (typically 7.5 V). UVP triggers the UVP circuit causing the system to first mute
and then stop switching. When the supply voltage rises above the threshold level, the
system restarts.
OverVoltage Protection (OVP) is activated when the supply voltage exceeds the OVP
threshold (typically 27 V). The OVP (or load dump) circuit is activated and the power
stages are shutdown. An overview of all protection circuits and the amplifier states is
given in Table 10.
8.5.7 Overview of protection circuits and amplifier states
Table 10.
Overview of TDF8599 protection circuits and amplifier states
Protection circuit name
Amplifier state
Complete
shutdown
Channel
shutdown
Restart[1]
TFP
N[2]
N[2]
Y[3]
OTP
Y
N
Y[3]
OCP
N
Y
Y[4]
WP
N
Y
Y
DCP
Y
N
N[5]
UVP
Y
N
Y[6]
OVP
Y
N
Y
[1]
When fault is removed.
[2]
Amplifier gain depends on the junction temperature and size of the heat sink.
[3]
TFP influences restart timing depending on heat sink size.
[4]
Shorted load causes a restart of the channel every 50 ms.
[5]
Latched protection is reset by toggling the pin EN or by disabling DCP in I2C-bus mode.
[6]
In I2C-bus mode deep supply voltage drops will cause a Power-On Reset (POR). The restart requires an
I2C-bus command.
TDF8599_1
Product data sheet
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Rev. 01 — 13 November 2008
17 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
8.6 Diagnostic output
8.6.1 Diagnostic table
The diagnostic information for I2C-bus mode and non-I2C-bus mode is shown in Table 11.
The instruction bitmap and data bytes are described in Table 14 and Table 15.
Pins DIAG and CLIP have an open-drain output which must have an external pull-up
resistor connected to an external voltage. Pins CLIP and DIAG can show both fixed and
I2C-bus selectable information.
Pin DIAG goes LOW when a short circuit to one of the amplifier outputs occurs. The
microprocessor reads the failure information using the I2C-bus. The I2C-bus bits are set
for a short circuit. These bits can be reset with the I2C-bus read command.
Even after the short has been removed, the microprocessor knows what was wrong after
reading the I2C-bus. In principle, during a single I2C-bus read command, the old
information is read. To read the current information, two read commands must be sent,
one-after-another.
When selected, pin DIAG gives the current diagnostic information. Pin DIAG is released
instantly when the failure is removed, independent of the I2C-bus latches.
Table 11.
Available data at DIAG and CLIP pin
Diagnostic
Power-on reset
I2C-bus mode
Non-I2C-bus mode
DIAG
CLIP
DIAG
CLIP
yes
no
yes
no
UVP or OVP
yes
no
yes
no
Clip detection
no
selectable
no
yes
Temperature pre-warning
no
selectable
no
yes
OCP
yes
no
yes
no
DCP
selectable
no
yes
no
OTP
yes
no
yes
no
When OCP is triggered, the open-drain DIAG output is activated. The diagnostic output
signal during different short circuit conditions is illustrated in Figure 16.
shorted load
short to GND or VP line
AMPLIFIER
RESTART
NO
RESTART
pull up V
AGND = 0 V
≈50 ms ≈50 ms ≈50 ms
001aai786
Fig 16. Diagnostic output for short circuit conditions
TDF8599_1
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TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
8.6.2 Load identification (I2C-bus mode only)
8.6.2.1
DC load detection
DC load detection is only available in I2C-bus mode and is controlled using bit IB2[D2].
The default setting is logic 0 for bit IB2[D2] which disables DC load detection. DC load
detection is enabled when bit IB2[D2] = 1. Load detection takes place before the class-D
amplifier output stage starts switching in Mute mode (see Figure 17) and the start-up time
from Standby mode to Mute mode is increased by tdet(DCload)
VP
DRIVER
HIGH
B
OUTN
PWM
CONTROL
DRIVER
LOW
PGND1
RL
VP
DRIVER
HIGH
OUTP
PWM
CONTROL
DRIVER
LOW
PGND2
001aai787
Fig 17. DC load detection circuit
out (V)
out−
out+
t (s)
Tdet(DCload)
Td(mute-off)
001aai788
Fig 18. DC load detection procedure
The capacitor connected to pin SEL_MUTE (see Figure 4) is used to create an inaudible
current test pulse, drawn from the positive amplifier output. The diagnostic ‘speaker load’
(or ‘open load’), based on the voltage difference between pins OUTxP and OUTxN is
shown in Figure 19.
SPEAKER LOAD
0Ω
OPEN LOAD
25 Ω
350 Ω
001aai789
Fig 19. DC load detection limits
TDF8599_1
Product data sheet
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Rev. 01 — 13 November 2008
19 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
Remark: DC load detection identifies a short circuited speaker as a valid speaker load.
OCP detection, using byte DB1[D3] for channel 1 and byte DB2[D3] for channel 2,
performs diagnostics on shorted loads. However, the diagnostics are performed after the
DC load detection cycle has finished and once the amplifier is in Operating mode.
The result of the DC load detection is stored in DB1[D4] and DB2[D4].
Table 12.
Interpretation of DC load detection bits
DC load bits DB1[D4] and DB2[D4]
OCP bits DB1[D3] and DB2[D3]
Meaning
0
0
speaker load
0
1
shorted load
1
0
open load
Remark: After DC load detection has been performed, the DC load valid bit DB1[D6] must
be set. The DC load data bits are only valid when bit DB1[D6] = 1. When DC load
detection is interrupted by a sudden large change in supply voltage (triggered by UVP or
OVP) or if the amplifier hangs up, the DC load valid bit is reset to DB1[D6] = 0. The DC
load enable bit DB2[D2] must be reset after the DC load protection cycle to release any
amplifier hang-up. Once the DC load detection cycle has finished, DC load detection can
be restarted by toggling the DC load detection enable bit IB2[D2]. However, this can only
be used if both amplifier channels have not been enabled with bit IB1[D1] or bit IB2[D1].
See Section 8.6.2.2 “Recommended start-up sequence with DC load detection enabled”
for detailed information.
8.6.2.2
Recommended start-up sequence with DC load detection enabled
The flow diagram (Figure 20) illustrates the TDF8599’s ability to perform a DC load
detection without starting the amplifiers. After a DC load detection cycle finishes without
setting the DC load valid bit DB1[D6], DC load detection is repeated (when bit IB2[D2] is
toggled).
To limit the maximum number of DC load detection cycle loops, a counter and limit have
been added. The loop exits after the predefined number of cycles (COUNTMAX), if the
DC load detection cycle finishes with an invalid detection.
Depending on the application needs the invalid DC load detection cycle can be handled
as follows:
• the amplifier can be started without DC load detection
• the DC load detection loop can be executed again
A valid DC load detection cycle does not affect the normal amplifier start-up timing.
TDF8599_1
Product data sheet
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Rev. 01 — 13 November 2008
20 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
I2C-bus TX
startup
enable DC load
disable channel 1
disable channel 2
IB1[D0] = 1
IB2[D2] = 1
IB1[D1] = 1
IB2[D1] = 1
COUNT = 0
WAIT DC load
DB1[D4] = 1
DB2[D4] = 1
DB1[D6] = 1
IB1[D0] = 1
IB2[D2] = 1
IB1[D1] = 1
IB2[D1] = 1
I2C-bus TX
startup
enable DC load
disable channel 1
disable channel 2
I2C-bus RX
ch1 openload
ch2 openload
DC load valid
COUNT ≤ COUNTMAX
COUNT = COUNT + 1
YES
ERROR HANDLING
start amplifier
anyway
I2C-bus TX
IB1[D0] = 1
IB2[D2] = 0
IB1[D1] = 1
IB2[D1] = 1
DB1[D6] = 1
DC load valid
restart
DC load
NO
startup
disable DC load
disable channel 1
disable channel 2
NO
YES
IB1[D0] = 1
IB2[D2] = 0
IB1[D1] = 0
IB2[D1] = 0
I2C-bus TX
startup
disable DC load
enable channel 1
enable channel 2
001aaj061
Fig 20. Recommended start-up sequence with DC load detection enabled
8.6.2.3
AC load detection
AC load detection is only available in I2C-bus mode and is controlled using bit IB3[D4].
The default setting for bit IB3[D4] = 0 which disables AC load detection. When AC load
detection is enabled (bit IB3[D4] = 1), the amplifier load current is measured and
compared with a reference level. Pin CLIP is activated when this threshold is reached.
Using this information, AC load detection can be performed using a predetermined input
signal frequency and level. The frequency and signal level should be chosen so that the
load current exceeds the programmed current threshold when the AC coupled load
(tweeter) is present.
8.6.2.4
CLIP detection
CLIP detection gives instantaneous information for clip levels ≥ 1 %. Pin CLIP is used as
the output for the clip detection circuitry on both channel 1 and channel 2. Setting either
bit IB1[D5] or bit IB2[D5] defines which channel reports clip information on the CLIP pin.
TDF8599_1
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TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
In Parallel mode, disabling clip detection on both channels requires both bits to be set to
bit IB1[D5] = 1 and bit IB2[D5] = 1.
8.6.3 Start-up and shutdown sequence
To prevent the switch on or switch off ‘pop noise’, a capacitor (CSVR) connected to pin SVR
is used to smooth start-up and shutdown. During start-up and shutdown, the output
voltage tracks the voltage on pin SVR. Increasing CSVR results in a longer start-up and
shutdown time. Enhanced pop performance is achieved by muting the amplifier until the
SVR voltage reaches its final value and the outputs start switching. The capacitor on the
pin SEL_MUTE (CON) determines the unmute and mute timing. The voltage on pin
SEL_MUTE determines the amplifier gain. Increasing CON increases the unmute and
mute times. In addition, a larger CON value increases the DC load detection cycle.
When the amplifier is switched off with an I2C-bus command or by pulling pin EN low, the
amplifier is first muted and then capacitor (CSVR) is discharged.
In Slave mode, the device enters the off state immediately after capacitor (CSVR) is
discharged. In Master mode, the clock is kept active by an additional delay (td(2)) of
approximately 50 ms to allow slave devices to enter off state.
When an external clock is connected to pin OSCIO (in Slave mode), the clock remains
active during the shutdown sequence (td(1)) to ensure that the slaved TDF8599 devices
are able to enter the off state.
VDDA
DIAG
td(1)
EN
ACGND
td(3)
IB1[D0] and
IB2[D0]=0
mute on delay
td(2)
SEL_MUTE
SVR
twake
td(stb-mute)
tdet(DCload)
OUT
001aai790
(1) Shutdown hold delay
(2) Master mode shutdown delay
(3) Shutdown delay
Fig 21. Start-up and shutdown timing in I2C-bus mode with DC load detection
TDF8599_1
Product data sheet
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Rev. 01 — 13 November 2008
22 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
VDDA
DIAG
td(2)
td(1)
EN
ACGND
mute on delay
td(3)
SEL_MUTE
SVR
td(stb-mute)
OUT
001aai791
(1) Shutdown hold delay
(2) Shutdown delay
(3) Master mode shutdown delay
Fig 22. Start-up and shutdown timing in non-I2C-bus mode
9. I2C-bus specification
TDF8599 address with hardware address select.
Table 13.
TDF8599 address using an external resistor
ADS[1]
A6
A5
A4
A3
A2
A1
A0
R/W
Open
0
1
0
1
1
0
0
0 = Write to TDF8599
100 kΩ to ground
0
1
0
1
0
1
1
1 = Read from TDF8599
33 kΩ to ground
0
1
0
1
0
1
0
13 kΩ to ground
0
1
0
1
0
0
1
4.7 kΩ to ground
0
1
0
1
0
0
0
Ground
Non-I2C-bus mode select
[1]
Required external resistor accuracy is 1 %.
The information on pin ADS is latched when the amplifier starts switching.
TDF8599_1
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Rev. 01 — 13 November 2008
23 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
SCL
SCL
SDA
SDA
Mµp
START
Mµp
STOP
SLAVE
(1)
SLAVE
(1)
(2)
001aai793
001aai792
(1) When SDL is HIGH, SDA changes to form the start or
stop condition.
(1) SDA is allowed to change.
(2) All data bits must be valid on the positive edges of the
SCL.
Fig 23. I2C-bus start and stop conditions
SCL
1
SDA
MSB
Mµp START
2
MSB−1
Fig 24. Data bits sent from Master microprocessor
(Mµp)
7
8
LSB+1
9
ACK
ADDRESS
1
MSB
2
MSB−1
WRITE
SLAVE
7
LSB+1
8
LSB
9
ACK
WRITE DATA
STOP
ACK(1)
ACK
001aai794
(1) To stop the transfer after the last acknowledge a stop condition must be generated.
Fig 25. I2C-bus write
SCL
1
SDA
MSB
Mµp START
SLAVE
2
MSB−1
ADDRESS
7
8
LSB+1
9
ACK
1
MSB
2
7
MSB−1
LSB+1
8
9
LSB
ACK(1)
READ
ACKNOWLEDGE
STOP
READ DATA
001aai795
(1) To stop the transfer, the last byte must not be acknowledged (SDA is HIGH) and a stop condition must be generated.
Fig 26. I2C-bus read
TDF8599_1
Product data sheet
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Rev. 01 — 13 November 2008
24 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
9.1 Instruction bytes
If R/W bit = 0, the TDF8599 expects three instruction bytes: IB1, IB2 and IB3. After a
power-on reset, all instruction bits are set to zero.
Table 14.
Instruction byte descriptions
Bit
Value
Instruction byte IB1
Instruction byte IB2
D7
0
offset detection on DIAG
offset protection on
1
no offset detection on DIAG
offset protection off
0
channel 1 offset monitoring on
channel 2 offset monitoring on
1
channel 1 offset monitoring off
channel 2 offset monitoring off
0
channel 1 clip detect on CLIP
channel 2 clip detect on CLIP
1
channel 1 no clip detect on CLIP
channel 2 no clip detect on CLIP
0
disable frequency hopping
thermal pre-warning on CLIP
disable AC load detection
D6
D5
D4
D3
D2
D1
D0
hopping[1]
Instruction byte IB3
1
enable frequency
no thermal pre warning on CLIP
enable AC load detection
0
oscillator frequency as set with
Rosc − 10 %
temperature pre-warning on
140 °C
[2]
1
oscillator frequency as set with
Rosc + 10 %
temperature pre-warning on
120 °C
0
DC-load detection disabled
1
DC-load detection enabled
0
channel 1 enabled
channel 2 enabled
1
channel 1 disabled
channel 2 disabled
0
TDF8599 in standby
1
[1]
Description
TDF8599 in mute or
operating[3]
[2]
[2]
all channels operating
AD modulation
all channels muted
BD modulation
See Section 8.3.3 on page 10 for information on IB1[D3].
[2]
See Table 15 “Frequency bit settings” for information.
[3]
See Table 4, Table 5 and Table 16 for information on IB2[D0].
Table 15.
Frequency bit settings
D3
D2
D1
Phase
0
0
0
0
0
0
1
1⁄
4
π
0
1
0
1⁄
3
π
1
1⁄
2
π
0
2⁄
3
π
1
3⁄
4
π
0
1
1
1
0
0
TDF8599_1
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TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
9.2 Data bytes
If R/W = 1, the TDF8599 sends two data bytes to the microprocessor (DB1 and DB2). All
short diagnostic and offset protection bits are latched. In addition, all bits are reset after a
read operation except the DC load detection bits (DBx[D4], DB1[D6]). The default setting
for all bits is logic 0.
In Parallel mode, the diagnostic information is stored in byte DB1.
Table 16.
Description of data bytes
Bit
Value
DB1 channel 1
DB2 channel 2
D7
0
at least 1 instruction bit set to logic 1
below maximum temperature
1
all instruction bits are set to logic 0
maximum temperature protection
activated
D6
D5
D4
D3
D2
D1
D0
0
invalid DC load data
no temperature warning
1
valid DC load data
temperature pre-warning active
0
no overvoltage
no undervoltage
1
overvoltage protection active
undervoltage protection active
0
speaker load channel 1
speaker load channel 2
1
open load channel 1
open load channel
0
no shorted load
no shorted load
1
shorted load channel 1
shorted load channel 2
0
no offset
reserved
1
offset detected
reserved
0
no short to Vp channel 1
no short to Vp channel 2
1
short to Vp channel 1
short to Vp channel 2
0
no short to ground channel 1
no short to ground channel 2
1
short to ground channel 1
short to ground channel 2
Data byte DB1[D7] indicates whether the instruction bits have been set to logic 0. In
principle, DB1[D7] is set after a POR or when all the instruction bits are programmed to
logic 0. Pin DIAG is activated when bit IB1[D7] = 1.
TDF8599_1
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TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
10. Limiting values
Table 17. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
VP
supply voltage
Operating mode
off state
[1]
load dump; duration
50 ms, tr >2.5 ms
Min
Max
Unit
-
18
V
−1
50
V
-
50
V
IORM
repetitive peak output
current
maximum output current
limiting
[2]
8
-
A
IOM
peak output current
maximum; non-repetitive
[2]
-
12
A
Vi
input voltage
pins SCL, SDA, ADS,
MOD, SSM, OSCIO, EN
and SEL_MUTE
0
5.5
V
Vo
output voltage
pins DIAG and CLIP
0
10
V
Tj
junction temperature
-
150
°C
Tstg
storage temperature
−55
+150
°C
Tamb
ambient temperature
−40
+85
°C
VESD
electrostatic discharge
voltage
-
2000
V
-
500
V
-
750
V
0
Vp
V
-
15
W
[3]
HBM
C = 100 pF;
Rs = 1500 Ω
CDM
[4]
non-corner pins
corner pins
V(prot)
protection voltage
AC and DC short circuit
voltage of output pins
across load and to
supply and ground
Pmax
maximum power dissipation
Tcase = 70 °C
[5]
[1]
Floating condition assumed for outputs.
[2]
Current limiting concept.
[3]
Human Body Model (HBM).
[4]
Charged-Device Model (CDM).
[5]
The output pins are defined as the output pins of the filter connected between the TDF8599 output pins and
the load.
11. Thermal characteristics
Table 18.
Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
Rth(j-a)
thermal resistance from junction
to ambient
in free air
35
K/W
Rth(j-c)
thermal resistance from junction
to case
1
K/W
TDF8599_1
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27 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
12. Static characteristics
Table 19. Static characteristics
Vp = 14.4 V; fosc = 320 kHz; −40 °C < Tamb < +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supply
VP
supply voltage
8
14.4 18
V
IP
supply current
off state; Tj ≤ 85 °C; VP = 14.4 V
-
2
10
µA
Istb
standby current
voltage on pin EN < 0.8 V
-
-
10
µA
Iq(tot)
total quiescent current
Operating mode; no load,
snubbers and filter connected
-
90
120
mA
Tj = 25 °C
-
130
-
mΩ
Tj = 100 °C
-
170
-
mΩ
Series resistance output switches
RDSon
drain-source on-state resistance
power switch;
I2C-bus interface: pins SCL and SDA
VIL
LOW-level input voltage
0
-
1.5
V
VIH
HIGH-level input voltage
2.3
-
5.5
V
VOL
LOW-level output voltage
0
-
0.4
V
pin SDA; Iload = 5 mA
Address, phase shift and modulation mode select: pins ADS and MOD
Vi
Ii
input voltage
input current
pins not connected
[1]
1.5
2
2.7
V
pins shorted to GND
[1]
80
120
160
µA
0
-
0.8
V
2
-
5
V
pin EN; Mute mode or Operating
mode; non-I2C-bus mode
2
-
5
V
pin SEL_MUTE; Mute mode;
voltage on pin EN > 2 V
0
-
0.8
V
pin SEL_MUTE; Operating mode;
voltage on pin EN > 2 V
3
-
5
V
pin EN; 2.5 V
-
-
5
µA
pin SEL_MUTE; Operating mode;
0.8 V
-
-
50
µA
-
0.2
-
%
1
2
3
V
Enable and SEL_MUTE input: pins EN and SEL_MUTE
Vi
input voltage
pin EN; off state
pin EN; Standby mode;
mode
Ii
input current
I2C-bus
Diagnostic output
THDclip
total harmonic distortion clip
detection level
Vth(offset)
threshold voltage for offset
detection
VOL
LOW-level output voltage
DIAG or CLIP pins activated;
Io = 1 mA
-
-
0.3
V
IL
leakage current
DIAG and CLIP pins; diagnostic
not activated
-
-
50
µA
-
2.45 -
[2]
Audio inputs; pins IN1N, IN1P, IN2N and IN2P
Vi
input voltage
TDF8599_1
Product data sheet
V
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
28 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
Table 19. Static characteristics …continued
Vp = 14.4 V; fosc = 320 kHz; −40 °C < Tamb < +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
input ACGND pin
2
2.45 3
V
half supply reference SVRR pin
6.9
7.2
7.5
V
-
-
25
mV
-
-
70
mV
8
10
12
V
SVRR voltage and ACGND input bias voltage in Mute and Operating modes
Vref
reference voltage
Amplifier outputs; pins OUT1N, OUT1P, OUT2N and OUTP2
VO(offset)
output offset voltage
BTL; Mute mode
BTL; Operating mode
[3][5]
Stabilizer output; pins VSTAB1 and VSTAB2
Vo
output voltage
stabilizer output in Mute mode and
Operating mode
Voltage protections
V(prot)
protection voltage
undervoltage; amplifier is muted
6.8
7.2
8
V
overvoltage; load dump protection
is activated
26.2 27
-
V
VP that a POR occurs at
3
3.7
4.4
V
current limit
8
-
-
A
Current protection
IO(ocp)
overcurrent protection output
current
Temperature protection
Tprot
protection temperature
155
-
160
°C
Tact(th_fold)
thermal foldback activation
temperature
gain = −1 dB
140
-
150
°C
Tj(AV)(warn1)
average junction temperature for
pre-warning 1
IB2[D3] = 0; non-I2C-bus mode
-
140
150
°C
Tj(AV)(warn2)
average junction temperature for
pre-warning 2
IB2[D3] = 1
-
120
130
°C
DC load detection levels: I2C-bus mode only[6]
Zth(load)
load detection threshold
impedance
for normal speaker; DB1[D4] = 0;
DB2[D4] = 0
-
-
25
Ω
Zth(open)
open load detection threshold
impedance
DB1[D4] = 1; DB2[D4] = 1
350
-
-
Ω
700
900
1100
mA
AC load detection levels: I2C-bus mode only
Ith(o)det(load)AC
AC load detection output
threshold current
Start-up/shut-down/mute timing
twake
wake-up time
on pin EN before first I2C-bus
transmission is recognized
[4]
-
-
500
µs
tdet(DCload)
DC load detection time
CON = 470 nF
[4]
-
250
-
ms
td(stb-mute)
delay time from standby to mute
measured from amplifier enabling
to start of mute release (no DC
load detection); CSVR = 47 µF
CON = 470 nF
-
140
-
ms
td(mute-fgain)
mute to full gain delay time
CON = 470 nF
-
15
-
ms
TDF8599_1
Product data sheet
[5]
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
29 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
Table 19. Static characteristics …continued
Vp = 14.4 V; fosc = 320 kHz; −40 °C < Tamb < +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
td
delay time
shutdown delay time from EN pin
low to SVRR low; SVRR < 0.1 V;
CSVR = 47 µF
145
260
425
ms
shutdown delay time from pin EN
low to ACGND low; voltage on pin
ACGND < 0.1 V; Master mode
-
400
-
ms
delay in Master mode to allow
slaved devices to shutdown
fosc = 320 kHz
-
50
-
ms
Speaker load impedance
load resistance
RL
stereo mode
1.6
4
-
Ω
parallel mode
0.8
-
-
Ω
[1]
Required resistor accuracy for pins ADS and MOD is 1 %; see Section 9 on page 23.
[2]
Maximum leakage current from DCP pin to ground = 3 µA.
[3]
DC output offset voltage is applied to the output during the transition between Mute mode and Operating mode in a gradual way.
[4]
I2C-bus mode only.
[5]
The transition time between Mute mode and Operating mode is determined by the time constant on the SEL_MUTE pin.
[6]
The DC load valid bit DB1[D6] must be used; Section 8.6.2.1 on page 19. The DC load enable bit IB2[D2] must be reset after each load
detection cycle to prevent amplifier hang-up incidents.
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
30 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
12.1 Switching characteristics
Table 20. Switching characteristics
VP = 14.4 V; −40 °C < Tamb < +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
external clock frequency;
Rosc = 39 kΩ
-
320
-
kHz
internal fixed frequency and Spread
spectrum mode frequency
300
-
500
kHz
Internal oscillator
fosc
oscillator frequency
Master/slave setting (OSCIO pin)
Rosc
oscillator resistance
resistor value on pin OSCSET;
master setting
26
39
49
kΩ
VOL
LOW-level output voltage
output
-
-
0.8
V
VOH
HIGH-level output voltage
output
4
-
-
V
VIL
LOW-level input voltage
input
-
-
0.8
V
VIH
HIGH-level input voltage
input
4
-
-
V
ftrack
tracking frequency
PLL enabled
300
-
500
kHz
Nslave
number of slaves
driven by one master
-
-
12
Spread spectrum mode setting
∆fosc
oscillator frequency variation
between maximum and minimum
values; Spread spectrum mode
activated
-
10
-
%
fsw
switching frequency
Spread spectrum mode activated;
CSSM = 1 µF
-
7
-
Hz
change positive; IB1[D4] = 1;
IB1[D3] = 0
-
fosc + 10 % -
kHz
change negative; IB1[D4] = 1;
IB1[D3] = 1
-
fosc − 10 % -
kHz
Frequency hopping
fosc(int)
internal oscillator frequency
Timing
tr
rise time
PWM output; Io = 0
-
10
-
ns
tf
fall time
PWM output; Io = 0
-
80
-
ns
tw(min)
minimum pulse width
Io = 0
-
80
-
ns
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
31 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
13. Dynamic characteristics
Table 21. Dynamic characteristics
Vp = 14.4 V; RL = 4 Ω; fi = 1 kHz; fosc = 320 kHz; RsL < 0.04 Ω[1]; −40 °C < Tamb < +85 °C; Stereo mode; unless otherwise
specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Po
output power
Stereo mode;
18
20
-
W
THD = 10 %; RL = 4 Ω
24
26
-
W
square wave (EIAJ); RL = 4 Ω
-
40
-
W
THD = 1 %; RL = 4 Ω
[2]
THD = 1 %; RL = 2 Ω
29
32
-
W
THD = 10 %; RL = 2 Ω
39
43
-
W
square wave (EIAJ); RL = 2 Ω
-
70
-
W
[2]
-
85
-
W
fi = 1 kHz; Po = 1 W
[3]
-
0.02
0.1
%
fi = 10 kHz; Po = 1 W
[3]
-
0.02
0.1
%
25
26
27
dB
-
70
-
dB
Parallel mode
THD = 10 %; RL = 1 Ω
THD
total harmonic distortion
Gv(cl)
closed-loop voltage gain
αcs
channel separation
fi = 1 kHz; Po = 1 W
SVRR
supply voltage rejection ratio
Operating mode
fripple = 100 Hz
[4]
-
70
-
dB
fripple = 1 kHz
[4]
-
70
-
dB
[4]
-
70
-
dB
[4]
-
90
-
dB
60
100
150
kΩ
Mute mode
fripple = 1 kHz
off state and Standby mode
fripple = 1 kHz
|Zi(dif)|
differential input impedance
Vn(o)
output noise voltage
Operating mode
BD mode
[5]
-
60
77
µV
AD mode
[5]
-
100
140
µV
BD mode
[6]
-
25
32
µV
AD mode
[6]
-
85
110
µV
-
0
1
dB
Mute mode
αbal(ch)
channel balance
αmute
mute attenuation
66
-
-
dB
CMRR
common mode rejection ratio
Vi(CM) = 1 V RMS
65
80
-
dB
ηpo
output power efficiency
Po = 20 W
-
90
-
%
[7]
[1]
RS(L) is the sum of the inductor series resistance from the low-pass LC filter in the application together with all resistance from PCB
traces or wiring between the output pin of the TDF8599 and the inductor to the measurement point. LC filter dimensioning is L = 10 µH,
C = 1 µF is used and for 2 Ω load L = 5 µH, C = 2.2 µF for 4 Ω load.
[2]
Output power is measured indirectly based on RDSon measurement.
[3]
Total harmonic distortion is measured at the bandwidth of 22 Hz to 20 kHz, AES brick wall. The maximum limit is guaranteed but may
not be 100 % tested.
[4]
Vripple = Vripple(max) = 1 V RMS; Rs = 0 Ω.
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
32 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
[5]
B = 22 Hz to 20 kHz, AES brick wall, Rs = 0 Ω.
[6]
B = 22 Hz to 20 kHz, AES brick wall, independent of Rs.
[7]
Vi = Vi(max) = 0.5 V RMS.
14. Application information
14.1 Output power estimation (Stereo mode)
The output power, just before clipping, can be estimated using the following equations:
2
RL
f osc
 × 1 – t
  ----------------------------------------------------
×
V
×
--------W ( min )
p
  R L + 2 × ( R DSon + R S ) 
2 
P o = ---------------------------------------------------------------------------------------------------------------------------------------2 × RL
(5)
Where,
•
•
•
•
•
•
•
Po = 0.5 %
VP = supply voltage (V)
RL = load impedance (Ω)
RDSon = on-resistance power switch (Ω)
RS = series resistance output inductor (Ω)
tW(min) = minimum pulse width(s) depending on output current
fosc = oscillator frequency in Hz (typically 320 kHz)
The output power at 10 % THD can be estimated by: P 0 ( 2 ) = 1.25 × P o ( 1 ) Where
Po(1) = 0.5 % and Po(2) = 10 %.
Figure 27 and Figure 28 show the estimated output power at THD = 0.5 % and
THD = 10 % as a function of supply voltage for different load impedances at stereo mode.
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
33 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
001aai796
80
Po
(W)
001aai797
80
Po
(W)
60
60
40
(1)
40
(1)
(2)
(2)
20
20
(3)
(3)
0
0
8
10
12
14
16
18
8
10
VP (V)
THD = 0.5 %.
14
16
18
VP (V)
THD = 10 %.
(1) RDSon = 0.12 Ω (at Tj = 25 °C), RS = 0.025 Ω,
tW(min) = 130 ns and IO(ocp) = 8 A (minimum).
(1) RDSon = 0.12 Ω (at Tj = 25 °C), RS = 0.025 Ω,
tW(min) = 130 ns and IO(ocp) = 8 A (minimum).
(2) RL = 1 Ω.
(2) RL = 1 Ω.
(3) RL = 2 Ω.
(3) RL = 2 Ω.
(4) RL = 4 Ω.
(4) RL = 4 Ω.
Fig 27. Po as a function of Vp in stereo mode with
THD = 0.5 %
Fig 28. Po as a function of Vp in stereo mode with
THD = 10 %
TDF8599_1
Product data sheet
12
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
34 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
14.2 Output power estimation (Parallel mode)
Figure 29 and Figure 30 show the estimated output power at THD = 0.5 % and
THD = 10 % as a function of the supply voltage for different load impedances in parallel
mode.
001aai798
160
Po
(W)
001aai799
160
Po
(W)
120
(1)
120
(1)
80
80
(2)
(2)
40
(3)
40
(3)
0
0
8
10
12
14
16
18
8
10
VP (V)
THD = 0.5 %.
12
14
16
18
VP (V)
THD = 10 %.
(1) RDSon = 0.06 Ω (at Tj = 25 °C), RS = 0.0125 Ω,
tW(min) = 130 ns and IO(ocp) = 16 A (minimum).
(1) RDSon = 0.06 Ω (at Tj = 25 °C), RS = 0.0125 Ω,
tW(min) = 130 ns and IO(ocp) = 16 A (minimum).
(2) RL = 1 Ω.
(2) RL = 1 Ω.
(3) RL = 2 Ω.
(3) RL = 2 Ω.
(4) RL = 4 Ω.
(4) RL = 4 Ω.
Fig 29. Po as a function of Vp in parallel mode with
THD = 0.5 %
Fig 30. Po as a function of Vp parallel mode with
THD = 10 %
14.3 Output current limiting
The peak output current is internally limited to 8 A maximum. During normal operation, the
output current should not exceed this threshold level otherwise the output signal will be
distorted. The peak output current can be estimated using the following equation:
Vp
I o ≤ ------------------------------------------------------ ≤ 8 A
R L + 2 × ( R RSon + R S )
•
•
•
•
•
(6)
Io = output current (A)
VP = supply voltage (V)
RL = load impedance (Ω)
RDSon = on-resistance power switch (Ω)
RS = series resistance output inductor (Ω)
Example: A 1 Ω speaker can be used with a supply voltage of 11 V before current limiting
is triggered.
Current limiting (clipping) avoids audio holes but can cause distortion similar to voltage
clipping. In Parallel mode, the output current is internally limited above 16 A.
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
35 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
14.4 Speaker configuration and impedance
A flat-frequency response (due to a 2nd order Butterworth filter) is obtained by changing
the low-pass filter components (LLC, CLC) based on the speaker configuration and
impedance. Table 22 shows the required values.
Table 22.
Filter components values
Load impedance (Ω)
LLC (µH)
CLC (µF)
1
2.5
4.4
2
5
2.2
4
10
1
Remark: When using a 1 Ω load impedance in Parallel mode, the outputs are shorted
after the low-pass filter switches two 2 Ω filters in parallel.
14.5 Heat sink requirements
In some applications, it may be necessary to connect an external heat sink to the
TDF8599. Thermal foldback activates at Tj = 145 °C. The expression below shows the
relationship between the maximum power dissipation before activation of thermal foldback
and the total thermal resistance from junction to ambient;
T j ( max ) – T amb
R th ( j – a ) = ----------------------------------P max
(7)
Pmax is determined by the efficiency (η) of the TDF8599. The efficiency measured as a
function of output power is given in Figure 39. The power dissipation can be derived as a
function of output power (see Figure 32).
Example 1:
•
•
•
•
•
•
Vp = 14.4 V
Po = 2 × 25 W into 4 Ω (THD = 10 % continuous)
Tj(max) = 140 °C
Tamb = 25 °C
Pmax = 5.8 W (from Figure 39)
The required Rth(j-a) = 115 °C/5.8 W = 19 K/W
The total thermal resistance Rth(j-a) consists of:
• Rth(j-c) + Rth(c-h) + Rth(h-a)
Where:
• Thermal resistance from junction to case (Rth(j-c)) = 1.1 K/W
• Thermal resistance from case to heat sink (Rth(c-h)) = 0.5 − 1 K/W (depending on
mounting)
• Thermal resistance from heat sink to ambient (Rth(h-a)) would then be
19 − (1.1 + 1) = 17 K/W.
If an audio signal has a crest factor of 10 (the ratio between peak power and average
power = 10 dB) then Tj will be much lower.
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
36 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
Example 2:
•
•
•
•
•
•
Vp = 14.4 V
Po = 2 × (25 W/10) = 2 × 2.5 W into 4 Ω (audio with crest factor of 10)
Tamb = 25 °C
Pmax = 2.5 W (from Figure 39)
Rth(j-a) = 19 K/W
Tj(max) = 25 °C + 2.5 W × 19 K/W = 72 °C
14.6 Curves measured in reference design
001aai800
102
%
001aai801
102
%
10
10
1
1
10−1
(1)
10−1
(1)
(2)
10−2
10−2
(3)
10−3
10−1
(2)
(3)
1
102
10
10−3
10−1
1
W
(1) VP = 14.4 V; RL = 2 Ω at 6 kHz.
(1) VP = 14.4 V; RL = 4 Ω at 6 kHz.
(2) VP = 14.4 V; RL = 2 Ω at 1 kHz.
(2) VP = 14.4 V; RL = 4 Ω at 1 kHz.
(3) VP = 14.4 V, RL = 2 Ω at 100 Hz.
(3) VP = 14.4 V, RL = 4 Ω at 100 Hz.
Fig 31. THD + N as a function of output power
Fig 32. THD + N as a function of output power
TDF8599_1
Product data sheet
102
10
W
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
37 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
001aai802
1
001aai803
1
%
%
10−1
10−1
(1)
(1)
10−2
10−2
(2)
10−3
10
102
103
104
105
(2)
10−3
10
102
103
104
Hz
(1) VP = 14.4 V; RL = 2 Ω at 10 W.
(1) VP = 14.4 V; RL = 4 Ω at 10 W.
(2) VP = 14.4 V; RL = 2 Ω at 1 W.
(2) VP = 14.4 V; RL = 4 Ω at 1 W.
Fig 33. THD + N as a function of frequency with a 2 Ω
load
001aai804
−60
105
Hz
dB
Fig 34. THD + N as a function of frequency with a 4 Ω
load
001aai805
−60
dB
−70
−70
−80
−80
(1)
(1)
(2)
−90
(2)
−90
−100
10
102
103
104
105
−100
10
102
103
104
Hz
PO = 1 W; VP = 14.4 V; RL = 2 Ω.
PO = 1 W; VP = 14.4 V; RL = 4 Ω.
(1) Channel 1 to channel 2.
(1) Channel 1 to channel 2.
(2) Channel 2 to channel 1.
(2) Channel 2 to channel 1.
Fig 35. Channel separation as a function of frequency
with a 2 Ω load
Fig 36. Channel separation as a function of frequency
with a 4 Ω load
TDF8599_1
Product data sheet
105
Hz
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
38 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
001aai806
−75
A
(dBr)
CMRR
(dB)
001aai807
1.0
0.8
0.6
0.4
−80
0.2
(2)
0
(1)
−0.2
−85
(1)
(2)
−0.4
−0.6
−0.8
−90
10−2
10−1
1
102
10
−1.0
10
102
103
104
105
kHz
Hz
Vi = 1 V; Ri = 0 Ω.
Vi =100 mV RMS; Ri = 0 Ω.
(1) VP = 14.4 V; RL = 2 Ω.
(1) VP = 14.4 V; RL = 2 Ω.
(2) VP = 14.4 V; RL = 4 Ω.
(2) VP = 14.4 V; RL = 4 Ω.
Fig 37. CMRR as a function of frequency
Fig 38. Gain as a function of frequency
001aai808
100
(2)
n
(%)
PD
(W)
(1)
80
001aai809
20
16
60
12
(1)
40
8
20
4
(2)
0
0
0
10
20
30
40
50
60
Po (W)
0
20
40
(1) VP = 14.4 V; RL = 2 Ω at 1 kHz.
(1) VP = 14.4 V; RL = 2 Ω at 1 kHz.
(2) VP = 14.4 V; RL = 4 Ω at 1 kHz.
(2) VP = 14.4 V; RL = 4 Ω at 1 kHz.
Fig 39. Efficiency as a function of Po
Fig 40. Power dissipation as a function of total output
power
TDF8599_1
Product data sheet
60
Po (W)
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
39 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
14.7 Typical application schematics
bead
100 µF
35 V
bead
bead
VP
100 µF
35 V
VP1
VP2
VPA
PGND1
1000 µF
35 V
GND
PGND2
GNDD/HW
100 nF
VDDD
220 nF
LLC
OUT1N
OUT1N
100 nF
15 nF
10 Ω
CLC
22 Ω
470 pF
CLC
470 pF
10 Ω
100 nF
OUT1P
LLC
OUT2P
OUT2P
100 nF
15 nF
10 Ω
CLC
22 Ω
470 pF
470 pF
VP2
22 Ω
CLC
VP2
VP2
BOOT2N
15 nF
LLC
220 nF
(3)
2
34
3
33
4
32
5
31
6
IN1P CIN1P
470 nF
IN1N CIN1N
470 nF
CIN2P
470 nF
IN2N CIN2N
470 nF
IN2P
ACGND
EN
7
IN1P
IN1N
IN2P
IN2N
CACGND
100 nF
enable(1)
8
28
9
TDF8599
27
10
26
11
25
12
24
13
SEL_MUTE
OUT2N
VSTAB2
DCP
OSCIO
23
14
22
15
21
16
20
17
19
18
mute/on(1)
470 nF
SVRR
47 µF
AGND
VDDA
100 nF
bead
VPA
non-I2C-bus
mode
ADS
MOD
4.7 kΩ
CLIP
10 kΩ
DIAG
10 kΩ
100 nF
10 Ω
100 nF
OUT2N
470 pF
BOOT2P
PGND2 PGND2
PGND2
470 pF
35
PGND1
30
PGND1
BOOT1P
29
15 nF
LLC
OUT1P
VP1
1
100 nF
PGND1
470 pF
BOOT1N
VP1
470 pF
VP1
22 Ω
VSTAB1
36
BD modulation
setting
VPA
VPA
SDA
SCL
SSM
OSCSET
1 µF(2)
100 nF
39 kΩ
MASTER
MODE
001aai810
Dual BTL mode (stereo) in non-I2C-bus mode with DC offset protection disabled Spread spectrum
mode enabled BD modulation.
(1) See Figure 4 on page 7 for a diagram of the connection for pins EN and SEL_MUTE.
(2) See Section 8.3.2 on page 9 for detailed information.
(3) See Section 8.5.5 on page 16 for detailed information on disabling DC offset protection.
Fig 41. Example application diagram for dual BTL in non-I2C-bus mode
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
40 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
bead
100 µF
35 V
bead
bead
VP
100 µF
35 V
VP1
VP2
VPA
PGND1
1000 µF
35 V
GND
PGND2
GNDD/HW
100 nF
VDDD
220 nF
LLC
OUT1N
OUT1N
100 nF
15 nF
10 Ω
CLC
22 Ω
470 pF
CLC
470 pF
10 Ω
100 nF
OUT1P
LLC
OUT2P
OUT2P
100 nF
15 nF
10 Ω
CLC
22 Ω
470 pF
470 pF
VP2
22 Ω
CLC
VP2
VP2
BOOT2N
15 nF
LLC
220 nF
OUT2N
VSTAB2
DCP
(3)
2
34
3
33
4
32
5
31
6
7
8
28
9
TDF8599
27
10
26
11
25
12
24
13
IN1P CIN1P
470 nF
IN1N CIN1N
470 nF
IN2P CIN2P
470 nF
IN2N CIN2N
470 nF
ACGND
EN
4.7 µF
OSCIO
23
14
22
15
21
16
20
17
19
18
IN1P
IN1N
IN2P
IN2N
CACGND
100 nF
enable(1)
SEL_MUTE(1)
470 nF
SVRR
47 µF
AGND
VDDA
ADS
MOD
100 nF
10 Ω
100 nF
OUT2N
470 pF
BOOT2P
PGND2 PGND2
PGND2
470 pF
35
PGND1
30
PGND1
BOOT1P
29
15 nF
LLC
OUT1P
VP1
1
100 nF
PGND1
470 pF
BOOT1N
VP1
470 pF
VP1
22 Ω
VSTAB1
36
100 nF
bead
Rads
≤33 kΩ
CLIP
10 kΩ
DIAG
10 kΩ
VPA
I2C-bus
address select
stereo mode
setting
VPA
VPA
SDA
connect
with µP
SCL
SSM
OSCSET
(2)
100 nF
39 kΩ
MASTER
MODE
001aai811
Dual BTL mode (stereo) in non-I2C-bus mode with DC offset protection enabled Spread spectrum
mode disabled.
(1) See Figure 4 on page 7 for a diagram of the connection for pins EN and SEL_MUTE.
(2) See Section 8.3.2 on page 9 for detailed information.
(3) See Section 8.5.5 on page 16 for detailed information on disabling DC offset protection.
Fig 42. Example application diagram for dual BTL in I2C-bus mode
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
41 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
bead
100 µF
35 V
bead
bead
VP
100 µF
35 V
VP1
VP2
VPA
PGND1
1000 µF
35 V
GND
PGND2
GNDD/HW
100 nF
VDDD
220 nF
LLC
OUT1N
15 nF
10 Ω
470 pF
470 pF
CLC
10 Ω
22 Ω
VP1
OUT1P
LLC
22 Ω
100 nF
OUT2P
BOOT2P
CLC
470 pF
OUTP
15 nF
10 Ω
470 pF
VP2
PGND2 PGND2
470 pF
VP2
VP2
BOOT2N
10 Ω
15 nF
LLC
220 nF
OUT2N
VSTAB2
DCP
(3)
2
34
3
33
4
32
5
31
6
7
8
28
9
TDF8599
27
10
26
11
25
12
24
13
IN1P
IN1N
4.7 µF
OSCIO
23
14
22
15
21
16
20
17
19
18
CINP
CINN
470 nF
INP
470 nF
INN
IN2P
IN2N
ACGND
EN
CACGND
100 nF
enable(1)
SEL_MUTE(1)
470 nF
SVRR
47 µF
AGND
VDDA
100 nF
ADS
bead
Rads
MOD
≥100 kΩ
100 nF
PGND2
470 pF
35
PGND1
30
PGND1
BOOT1P
29
15 nF
LLC
1
100 nF
PGND1
470 pF
100 nF
BOOT1N
VP1
470 pF
VP1
OUTN
VSTAB1
36
CLIP
10 kΩ
DIAG
10 kΩ
VPA
I2C-bus
address select
parallel mode
setting
VPA
VPA
SDA
connect
with µP
SCL
SSM
OSCSET
100 nF
39 kΩ
fixed
frequency(2)
MASTER
MODE
001aai812
Single BTL mode (parallel) in I2C-bus mode with DC offset protection enabled Spread spectrum
mode disabled.
(1) See Figure 4 on page 7 for a diagram of the connection for pins EN and SEL_MUTE.
(2) See Section 8.3.2 on page 9 for detailed information.
(3) See Section 8.5.5 on page 16 for detailed information on disabling DC offset protection.
Fig 43. Example application diagram for a single BTL in I2C-bus mode
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
42 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
bead
100 µF
35 V
bead
100 µF
35 V
bead
VP
GND
VP1
VP2
GNDD/HW
VPA
PGND1
1000 µF
35 V
100 nF
PGND2
VDDD
220 nF
LLC
OUT1N
OUT1N
100 nF
CLC
15 nF
10 Ω
22 Ω
470 pF
CLC
100 nF
470 pF
10 Ω
PGND1
PGND1
BOOT1P
15 nF
LLC
OUT1P
VP1
OUT1P
LLC
OUT2P
OUT2P
100 nF
CLC
15 nF
10 Ω
22 Ω
470 pF
470 pF
VP2
CLC
100 nF
470 pF
VP2
VP2
10 Ω
15 nF
OUT2N
220 nF
VSTAB2
DCP
DC offset
protection enabled
35
2
34
3
33
4
32
5
31
6
30
7
29
8
28
9
TDF8599
27
10
26
11
25
12
IN1P CIN1P
470 nF
IN1N CIN1N
470 nF
IN2P CIN2P
470 nF
IN2N CIN2N
470 nF
4.7 µF
OSCIO
(3)
24
13
23
14
22
15
21
16
20
17
19
18
GNDD/HW
VDDD
220 nF
LLC
470 pF
15 nF
470 pF
470 pF
10 Ω
VP1
OUT1P
LLC
100 nF
OUT2P
BOOT2P
CLC
470 pF
OUT3P
15 nF
10 Ω
470 pF
VP2
PGND2 PGND2
enable
SEL_MUTE(1)
470 nF
SVRR
47 µF
AGND
100 nF
VDDA
ADS
bead
Rads
MOD
≤33 kΩ
CLIP
10 kΩ
DIAG
10 kΩ
VPA
I2C-bus
address select
stereo mode
setting
VPA
VPA
SDA
SCL
1 µF
SSM
OSCSET
spread
spectrum
mode(2)
100 nF
MASTER
MODE
470 pF
VP2
VP2
BOOT2N
10 Ω
15 nF
LLC
220 nF
OUT2N
VSTAB2
DCP
DC offset
protection enabled
(3)
34
3
33
4
32
5
31
6
7
8
9
28
TDF8599
27
10
26
11
25
12
IN1P
Cin
470 nF
IN1N
Cin
470 nF
4.7 µF
OSCIO
24
13
23
14
22
15
21
16
20
17
19
18
IN3P
IN3N
IN2P
IN2N
CACGND
ACGND
100 nF
EN(1)
SEL_MUTE(1)
470 nF
SVRR
47 µF
AGND
100 nF
VDDA
ADS
bead
Rads
MOD
≥100 kΩ
100 nF
PGND2
470 pF
2
35
PGND1
30
PGND1
BOOT1P
29
15 nF
LLC
1
36
100 nF
PGND1
CLC
BOOT1N
VP1
470 pF
VP1
22 Ω
VSTAB1
OUT1N
10 Ω
22 Ω
IN2P
IN2N
39 kΩ
100 nF
100 nF
IN1N
100 nF
EN(1)
20 kΩ
OUT3N
IN1P
CACGND
ACGND
100 nF
BOOT2N
LLC
OUT2N
BOOT2P
PGND2 PGND2
PGND2
470 pF
22 Ω
1
100 nF
PGND1
470 pF
BOOT1N
VP1
470 pF
VP1
22 Ω
VSTAB1
36
CLIP
10 kΩ
DIAG
10 kΩ
VPA
I2C-bus
address select
parallel mode
setting
VPA
VPA
SDA
connect
with µP
SCL
5.1 kΩ
SSM
OSCSET
270 nF
10 nF
SLAVE MODE
phase lock
operation
(2)
001aai813
I2C-bus mode: Single BTL in Master mode with two BTLs in Slave mode; DC offset protection
enabled.
(1) See Figure 4 on page 7 for a diagram of the connection for pins EN and SEL_MUTE.
(2) See Section 8.3.2 on page 9 for detailed information.
(3) See Section 8.5.5 on page 16 for detailed information on disabling DC offset protection.
Fig 44. Master-slave example application diagram; one BTL master and two BTL slaves
in I2C-bus mode
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
43 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
15. Package outline
HSOP36: plastic, heatsink small outline package; 36 leads; low stand-off height
SOT851-2
D
E
A
x
c
y
X
E2
v
HE
M
A
D1
D2
1
18
pin 1 index
Q
A
A2
E1
(A 3)
A4
θ
Lp
detail X
36
19
z
w
bp
e
M
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT max. A2
mm
3.5
A3
A4(1)
+0.08
3.5
0.35
−0.04
3.2
D1
D2
E (2)
E1
E2
e
HE
Lp
Q
0.38 0.32 16.0 13.0
0.25 0.23 15.8 12.6
1.1
0.9
11.1
10.9
6.2
5.8
2.9
2.5
0.65
14.5
13.9
1.1
0.8
1.7
1.5
bp
c
D (2)
v
w
x
y
0.25 0.12 0.03 0.07
Z
θ
2.55
2.20
8°
0°
Notes
1. Limits per individual lead.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
04-05-04
SOT851-2
Fig 45. Package outline SOT851-2 (HSOP36)
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
44 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
HSOP36: plastic, heatsink small outline package; 36 leads; low stand-off height
SOT938-1
A
E
E2
D
X
c
y
v
HE
A
M
D1
D2
36
19
Q
E1
A2
A
pin index
A1
(A3)
A4
θ
Lp
detail X
1
18
Z
w
bp
e
M
0
5
10 mm
scale
y
Z
θ
0.1
2.55
2.20
8°
0°
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
A2
A3
A4(1)
bp
c
D (2)
D1
D2
E (2)
E1
E2
e
HE
Lp
Q
v
w
mm
3.6
0.3
0.1
3.3
3.0
0.35
0.1
0
0.38
0.25
0.32
0.23
16.0
15.8
13.0
12.6
1.1
0.9
11.1
10.9
6.2
5.8
2.9
2.5
0.65
14.5
13.9
1.1
0.8
1.5
1.4
0.25
0.12
Notes
1. Limits per individual lead.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
06-01-20
06-04-07
SOT938-1
Fig 46. Package outline SOT938-1 (HSOP36)
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
45 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
16. Handling information
In accordance with SNW-FQ-611-D. The number of the quality specification can be found
in the Quality Reference Handbook. The handbook can be ordered using the code
9398 510 63011.
17. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
46 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
17.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 47) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 23 and 24
Table 23.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 24.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 47.
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
47 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 47. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
18. Abbreviations
Table 25.
Abbreviations
Abbreviation
Description
BCDMOS
Bipolar Complementary and double Diffused Metal-Oxide Semiconductor
BTL
Bridge-Tied Load
DCP
DC offset Protection
EMI
ElectroMagnetic Interference
I2C
Inter-Integrated Circuit
LSB
Least Significant Bit
MSB
Most Significant Bit
NDMOST
N-type double Diffused Metal-Oxide Semiconductor Transistor
OCP
OverCurrent Protection
OTP
OverTemperature Protection
OVP
OverVoltage Protection
POR
Power-On Reset
PWM
Pulse-Width Modulation
SOI
Silicon On Insulator
TFP
Thermal Foldback Protection
UVP
UnderVoltage Protection
WP
Window Protection
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
48 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
19. Revision history
Table 26.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
TDF8599_1
20081113
Product data sheet
-
-
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
49 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
20. Legal information
20.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
20.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
21. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
50 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
22. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Quick reference data . . . . . . . . . . . . . . . . . . . . .2
Ordering information . . . . . . . . . . . . . . . . . . . . .2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
I2C-bus mode operation . . . . . . . . . . . . . . . . . . .8
Non-I2C-bus mode operation . . . . . . . . . . . . . . .8
Mode setting OSCIO . . . . . . . . . . . . . . . . . . . . .8
Oscillator modes . . . . . . . . . . . . . . . . . . . . . . .11
Operation mode selection with the MOD pin . .12
Overview of protection types . . . . . . . . . . . . . .15
Overview of TDF8599 protection circuits and
amplifier states . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 11. Available data at DIAG and CLIP pin . . . . . . . .18
Table 12. Interpretation of DC load detection bits . . . . . .20
Table 13. TDF8599 address using an external resistor . .23
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Instruction byte descriptions . . . . . . . . . . . . . . 25
Frequency bit settings . . . . . . . . . . . . . . . . . . . 25
Description of data bytes . . . . . . . . . . . . . . . . . 26
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 27
Thermal characteristics . . . . . . . . . . . . . . . . . . 27
Static characteristics . . . . . . . . . . . . . . . . . . . . 28
Switching characteristics . . . . . . . . . . . . . . . . . 31
Dynamic characteristics . . . . . . . . . . . . . . . . . 32
Filter components values . . . . . . . . . . . . . . . . 36
SnPb eutectic process (from J-STD-020C) . . . 47
Lead-free process (from J-STD-020C) . . . . . . 47
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 49
23. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Fig 13.
Fig 14.
Fig 15.
Fig 16.
Fig 17.
Fig 18.
Fig 19.
Fig 20.
Fig 21.
Fig 22.
Fig 23.
Fig 24.
Fig 25.
Fig 26.
Fig 27.
Fig 28.
Fig 29.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Heatsink up (top view) pin configuration
TDF8599TH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Heatsink down (top view) pin configuration
TDF8599TD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Oscillator frequency as function of Rosc . . . . . . . . .9
Master and slave configuration . . . . . . . . . . . . . . .9
Spread spectrum mode . . . . . . . . . . . . . . . . . . . .10
Spread spectrum operation in Master mode . . . .10
Phase lock operation . . . . . . . . . . . . . . . . . . . . . .11
AD/BD modulation switching circuit . . . . . . . . . . .12
AD modulation . . . . . . . . . . . . . . . . . . . . . . . . . . .13
BD modulation . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Master and slave operation with 1⁄2 p phase shift.14
Mono and Parallel modes . . . . . . . . . . . . . . . . . .14
DC offset protection and diagnostic output . . . . .16
Diagnostic output for short circuit conditions . . . .18
DC load detection circuit . . . . . . . . . . . . . . . . . . .19
DC load detection procedure . . . . . . . . . . . . . . . .19
DC load detection limits . . . . . . . . . . . . . . . . . . . .19
Recommended start-up sequence with DC load
detection enabled. . . . . . . . . . . . . . . . . . . . . . . . .21
Start-up and shutdown timing in I2C-bus mode
with DC load detection . . . . . . . . . . . . . . . . . . . . .22
Start-up and shutdown timing in non-I2C-bus
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
I2C-bus start and stop conditions. . . . . . . . . . . . .24
Data bits sent from Master microprocessor
(Mmp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
I2C-bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
I2C-bus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Po as a function of Vp in stereo mode with
THD = 0.5 % . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Po as a function of Vp in stereo mode with
THD = 10 % . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Po as a function of Vp in parallel mode with
THD = 0.5 % . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Fig 30. Po as a function of Vp parallel mode with
THD = 10 %. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Fig 31. THD + N as a function of output power . . . . . . . . 37
Fig 32. THD + N as a function of output power . . . . . . . . 37
Fig 33. THD + N as a function of frequency with
a 2 W load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Fig 34. THD + N as a function of frequency with
a 4 W load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Fig 35. Channel separation as a function of
frequency with a 2 W load . . . . . . . . . . . . . . . . . . 38
Fig 36. Channel separation as a function of
frequency with a 4 W load . . . . . . . . . . . . . . . . . . 38
Fig 37. CMRR as a function of frequency . . . . . . . . . . . . 39
Fig 38. Gain as a function of frequency. . . . . . . . . . . . . . 39
Fig 39. Efficiency as a function of Po . . . . . . . . . . . . . . . . 39
Fig 40. Power dissipation as a function of total
output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Fig 41. Example application diagram for dual BTL in
non-I2C-bus mode . . . . . . . . . . . . . . . . . . . . . . . . 40
Fig 42. Example application diagram for dual BTL
in I2C-bus mode. . . . . . . . . . . . . . . . . . . . . . . . . . 41
Fig 43. Example application diagram for a single BTL
in I2C-bus mode. . . . . . . . . . . . . . . . . . . . . . . . . . 42
Fig 44. Master-slave example application diagram;
one BTL master and two BTL slaves in I2C-bus
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Fig 45. Package outline SOT851-2 (HSOP36) . . . . . . . . 44
Fig 46. Package outline SOT938-1 (HSOP36) . . . . . . . . 45
Fig 47. Temperature profiles for large and small
components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
TDF8599_1
Product data sheet
© NXP B.V. 2008. All rights reserved.
Rev. 01 — 13 November 2008
51 of 52
TDF8599
NXP Semiconductors
Class-D power amplifier with load diagnostics
24. Contents
1
2
3
4
5
6
7
7.1
7.2
8
8.1
8.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.4
8.4.1
8.4.2
8.4.3
8.5
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
8.6
8.6.1
8.6.2
8.6.2.1
8.6.2.2
8.6.2.3
8.6.2.4
8.6.3
9
9.1
9.2
10
11
12
12.1
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 6
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pulse-width modulation frequency . . . . . . . . . . 8
Master and slave mode selection . . . . . . . . . . . 8
Spread spectrum mode (Master mode) . . . . . . 9
Frequency hopping (Master mode). . . . . . . . . 10
Phase lock operation (Slave mode) . . . . . . . . 10
Operation mode selection. . . . . . . . . . . . . . . . 11
Modulation mode . . . . . . . . . . . . . . . . . . . . . . 12
Phase staggering (Slave mode) . . . . . . . . . . . 13
Parallel mode . . . . . . . . . . . . . . . . . . . . . . . . . 14
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Thermal foldback . . . . . . . . . . . . . . . . . . . . . . 15
Overtemperature protection . . . . . . . . . . . . . . 15
Overcurrent protection . . . . . . . . . . . . . . . . . . 15
Window protection . . . . . . . . . . . . . . . . . . . . . 16
DC Protection . . . . . . . . . . . . . . . . . . . . . . . . . 16
Supply voltages . . . . . . . . . . . . . . . . . . . . . . . 17
Overview of protection circuits and amplifier
states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Diagnostic output . . . . . . . . . . . . . . . . . . . . . . 18
Diagnostic table . . . . . . . . . . . . . . . . . . . . . . . 18
Load identification (I2C-bus mode only) . . . . . 19
DC load detection . . . . . . . . . . . . . . . . . . . . . . 19
Recommended start-up sequence with DC
load detection enabled . . . . . . . . . . . . . . . . . . 20
AC load detection . . . . . . . . . . . . . . . . . . . . . . 21
CLIP detection . . . . . . . . . . . . . . . . . . . . . . . . 21
Start-up and shutdown sequence. . . . . . . . . . 22
I2C-bus specification . . . . . . . . . . . . . . . . . . . . 23
Instruction bytes . . . . . . . . . . . . . . . . . . . . . . . 25
Data bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 27
Thermal characteristics. . . . . . . . . . . . . . . . . . 27
Static characteristics. . . . . . . . . . . . . . . . . . . . 28
Switching characteristics . . . . . . . . . . . . . . . . 31
13
14
14.1
14.2
14.3
14.4
14.5
14.6
14.7
15
16
17
17.1
17.2
17.3
17.4
18
19
20
20.1
20.2
20.3
20.4
21
22
23
24
Dynamic characteristics . . . . . . . . . . . . . . . . .
Application information . . . . . . . . . . . . . . . . .
Output power estimation (Stereo mode) . . . .
Output power estimation (Parallel mode) . . . .
Output current limiting . . . . . . . . . . . . . . . . . .
Speaker configuration and impedance. . . . . .
Heat sink requirements . . . . . . . . . . . . . . . . .
Curves measured in reference design . . . . . .
Typical application schematics . . . . . . . . . . . .
Package outline . . . . . . . . . . . . . . . . . . . . . . . .
Handling information . . . . . . . . . . . . . . . . . . .
Soldering of SMD packages . . . . . . . . . . . . . .
Introduction to soldering. . . . . . . . . . . . . . . . .
Wave and reflow soldering . . . . . . . . . . . . . . .
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
33
33
35
35
36
36
37
40
44
46
46
46
46
46
47
48
49
50
50
50
50
50
50
51
51
52
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 13 November 2008
Document identifier: TDF8599_1