INTEGRATED CIRCUITS DATA SHEET 74HC2G02; 74HCT2G02 Dual 2-input NOR gate Product specification Supersedes data of 2003 Feb 03 2003 May 14 Philips Semiconductors Product specification Dual 2-input NOR gate 74HC2G02; 74HCT2G02 FEATURES DESCRIPTION • Wide supply voltage range from 2.0 to 6.0 V The 74HC2G/HCT2G02 is a high-speed Si-gate CMOS device. • Symmetrical output impedance • High noise immunity The 74HC2G/HCT2G02 provides the 2-input NOR function. • Low power dissipation • Balanced propagation delays • Very small 8 pins package • Output capability is standard • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. • Specified from −40 to +85 °C and −40 to +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 6.0 ns. TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC2G02 CL = 15 pF; VCC = 5 V tPHL/tPLH propagation delay nA, nB to nY CI input capacitance 1.5 1.5 pF CPD power dissipation capacitance per gate notes 1 and 2 10 10 pF Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; ∑ (CL × VCC2 × fo) = sum of outputs. 2. For 74HC2G02 the condition is VI = GND to VCC. For 74HCT2G02 the condition is VI = GND to VCC − 1.5 V. 2003 May 14 2 9 HCT2G02 12 ns Philips Semiconductors Product specification Dual 2-input NOR gate 74HC2G02; 74HCT2G02 FUNCTION TABLE See note 1. INPUT OUTPUT nA nB nY L L H L H L H L L H H L Note 1. H = HIGH voltage level; L = LOW voltage level. ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE MARKING 74HC2G02DP −40 to +125 °C 8 TSSOP8 plastic SOT505-2 H02 74HCT2G02DP −40 to +125 °C 8 TSSOP8 plastic SOT505-2 T02 74HC2G02DC −40 to +125 °C 8 VSSOP8 plastic SOT765-1 H02 74HCT2G02DC −40 to +125 °C 8 VSSOP8 plastic SOT765-1 T02 PINNING PIN SYMBOL DESCRIPTION 1 1A data input 2 1B data input 3 2Y data output 4 GND ground (0 V) 5 2A data input 6 2B data input 7 1Y data output 8 VCC supply voltage 2003 May 14 3 Philips Semiconductors Product specification Dual 2-input NOR gate 74HC2G02; 74HCT2G02 handbook, halfpage 1A 1 8 VCC 1B 2 7 1Y 6 2B 5 2A handbook, halfpage 02 2Y 3 GND 4 1 1A 2 1B 5 2A 6 2B 1Y 7 2Y 3 MNA716 MNA715 Fig.1 Pin configuration. handbook, halfpage 1 ≥1 Fig.2 Logic symbol. 7 2 5 handbook, halfpage B Y ≥1 3 A 6 MNA105 MNA717 Fig.3 IEC logic symbol. 2003 May 14 Fig.4 Logic diagram (one driver). 4 Philips Semiconductors Product specification Dual 2-input NOR gate 74HC2G02; 74HCT2G02 RECOMMENDED OPERATING CONDITIONS 74HC2G02 SYMBOL PARAMETER 74HCT2G02 CONDITIONS UNIT MIN. TYP. MAX. MIN. TYP. MAX. VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 − VCC 0 − VCC V VO output voltage 0 − VCC 0 − VCC V Tamb operating ambient temperature +25 +125 −40 +25 +125 °C tr, tf input rise and fall times see DC and AC −40 characteristics per device VCC = 2.0 V − − 1000 − − − ns VCC = 4.5 V − 6.0 500 − 6.0 500 ns VCC = 6.0 V − − 400 − − − ns LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER VCC supply voltage IIK input diode current CONDITIONS VI < −0.5 V or VI > VCC + 0.5 V; note 1 MIN. MAX. UNIT −0.5 +7.0 V − ±20 mA IOK output diode current VO < −0.5 V or VO > VCC + 0.5 V; note 1 − ±20 mA IO output source or sink current −0.5 V < VO < VCC + 0.5 V; note 1 − 25 mA ICC, IGND VCC or GND current note 1 − 50 mA Tstg storage temperature −65 +150 °C PD power dissipation Tamb = −40 to +125 °C; note 2 − 300 mW Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. Above 110 °C the value of PD derates linearly with 8 mW/K. 2003 May 14 5 Philips Semiconductors Product specification Dual 2-input NOR gate 74HC2G02; 74HCT2G02 DC CHARACTERISTICS Type 74HC2G02 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP. MAX. UNIT VCC (V) Tamb = −40 to +85 °C; note 1 VIH VIL VOH VOL 2.0 1.5 1.2 − V 4.5 3.15 2.4 − V 6.0 4.2 3.2 − V 2.0 − 0.8 0.5 V 4.5 − 2.1 1.35 V 6.0 − 2.8 1.8 V IO = −20 µA 2.0 1.9 2.0 − V IO = −20 µA 4.5 4.4 4.5 − V IO = −20 µA 6.0 5.9 6.0 − V IO = −4.0 mA 4.5 4.13 4.32 − V IO = −5.2 mA 6.0 5.63 5.81 − V IO = 20 µA 2.0 − 0 0.1 V IO = 20 µA 4.5 − 0 0.1 V IO = 20 µA 6.0 − 0 0.1 V IO = 4.0 mA 4.5 − 0.15 0.33 V HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL IO = 5.2 mA 6.0 − 0.16 0.33 V ILI input leakage current VI = VCC or GND 6.0 − − ±1.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 6.0 − − 10 µA 2003 May 14 6 Philips Semiconductors Product specification Dual 2-input NOR gate 74HC2G02; 74HCT2G02 TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP. MAX. UNIT VCC (V) Tamb = −40 to +125 °C VIH VIL VOH VOL HIGH-level input voltage LOW-level output voltage 1.5 − − V 4.5 3.15 − − V 6.0 4.2 − − V 2.0 − − 0.5 V 4.5 − − 1.35 V 6.0 − − 1.8 V IO = −20 µA 2.0 1.9 − − V IO = −20 µA 4.5 4.4 − − V IO = −20 µA 6.0 5.9 − − V IO = −4.0 mA 4.5 3.7 − − V IO = −5.2 mA 6.0 5.2 − − V IO = 20 µA 2.0 − − 0.1 V IO = 20 µA 4.5 − − 0.1 V IO = 20 µA 6.0 − − 0.1 V IO = 4.0 mA 4.5 − − 0.4 V IO = 5.2 mA 6.0 − − 0.4 V LOW-level input voltage HIGH-level output voltage 2.0 VI = VIH or VIL VI = VIH or VIL ILI input leakage current VI = VCC or GND 6.0 − − ±1.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 6.0 − − 20 µA Note 1. All typical values are measured at Tamb = 25 °C. 2003 May 14 7 Philips Semiconductors Product specification Dual 2-input NOR gate 74HC2G02; 74HCT2G02 Type 74HCT2G02 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER MIN. OTHER TYP. MAX. UNIT VCC (V) Tamb = −40 to +85 °C; note 1 VIH HIGH-level input voltage 4.5 to 5.5 2.0 1.6 − V VIL LOW-level input voltage 4.5 to 5.5 − 1.2 0.8 V VOH HIGH-level output voltage VOL LOW-level output voltage VI = VIH or VIL IO = −20 µA 4.5 4.4 4.5 − V IO = −4.0 µA 4.5 4.13 4.32 − V IO = 20 µA 4.5 − 0 0.1 V IO = 4.0 µA 4.5 − 0.15 0.33 V VI = VIH or VIL ILI input leakage current VI = VCC or GND 5.5 − − ±1.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 10 µA ∆ICC additional supply current per input VI = VCC − 2.1 V; IO = 0 4.5 to 5.5 − − 375 µA Tamb = −40 to +125 °C VIH HIGH-level input voltage 4.5 to 5.5 2.0 − − V VIL LOW-level input voltage 4.5 to 5.5 − − 0.8 V VOH HIGH-level output voltage VOL LOW-level output voltage VI = VIH or VIL IO = −20 µA 4.5 4.4 − − V IO = −4.0 µA 4.5 3.7 − − V IO = 20 µA 4.5 − − 0.1 V IO = 4.0 µA 4.5 − − 0.4 V VI = VIH or VIL ILI input leakage current VI = VCC or GND 5.5 − − ±1.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 20 µA ∆ICC additional supply current per input VI = VCC − 2.1 V; IO = 0 4.5 to 5.5 − − 410 µA Note 1. All typical values are measured at Tamb = 25 °C. 2003 May 14 8 Philips Semiconductors Product specification Dual 2-input NOR gate 74HC2G02; 74HCT2G02 AC CHARACTERISTICS Type 74HC2G02 GND = 0 V; tr = tf ≤ 6.0 ns; CL = 50 pF. TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT VCC (V) Tamb = −40 to +85 °C; note 1 tPHL/tPLH tTHL/tTLH propagation delay nA, nB to nY output transition time see Figs 5 and 6 2.0 − 26 95 ns 4.5 − 9 19 ns 6.0 − 8 16 ns see Figs 5 and 6 2.0 − 19 95 ns 4.5 − 7 19 ns 6.0 − 5 16 ns see Figs 5 and 6 2.0 − − 110 ns 4.5 − − 22 ns 6.0 − − 20 ns see Figs 5 and 6 2.0 − − 125 ns 4.5 − − 25 ns 6.0 − − 20 ns Tamb = −40 to +125 °C tPHL/tPLH tTHL/tTLH propagation delay nA, nB to nY output transition time Note 1. All typical values are measured at Tamb = 25 °C. Type 74HCT2G02 GND = 0 V; tr = tf ≤ 6.0 ns; CL = 50 pF. TEST CONDITIONS SYMBOL PARAMETER MIN. WAVEFORMS TYP. MAX. UNIT VCC (V) Tamb = −40 to +85 °C; note 1 tPHL/tPLH propagation delay nA, nB to nY see Figs 5 and 6 4.5 − 12 24 ns tTHL/tTLH output transition time see Figs 5 and 6 4.5 − 6 19 ns Tamb = −40 to +125 °C tPHL/tPLH propagation delay nA, nB to nY see Figs 5 and 6 4.5 − − 29 ns tTHL/tTLH output transition time see Figs 5 and 6 4.5 − − 22 ns Note 1. All typical values are measured at Tamb = 25 °C. 2003 May 14 9 Philips Semiconductors Product specification Dual 2-input NOR gate 74HC2G02; 74HCT2G02 AC WAVEFORMS VI handbook, halfpage VM nA, nB input VM GND t PHL t PLH VOH 90% VM VM nY output 10% VOL t THL t TLH MNA718 For 74HC2G02: VM = 50%; VI = GND to VCC. For 74HCT2G02: VM = 1.3 V; VI = GND to 3.0 V. Fig.5 The input (nA, nB) to output (nY) propagation delays and transition times. S1 handbook, full pagewidth VCC PULSE GENERATOR RL = VI 1 kΩ VO D.U.T. CL = 50 pF RT MNA742 TEST S1 tPLH/tPHL open tPLZ/tPZL VCC tPHZ/tPZH GND Definitions for test circuit: CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.6 Load circuitry for switching times. 2003 May 14 10 VCC open GND Philips Semiconductors Product specification Dual 2-input NOR gate 74HC2G02; 74HCT2G02 PACKAGE OUTLINES TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 (A3) A1 pin 1 index θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 2003 May 14 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 --- 11 Philips Semiconductors Product specification Dual 2-input NOR gate 74HC2G02; 74HCT2G02 VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D E SOT765-1 A X c y HE v M A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 4 e L detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1 0.15 0.00 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.40 0.15 0.21 0.19 0.2 0.13 0.1 0.4 0.1 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 2003 May 14 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 MO-187 12 Philips Semiconductors Product specification Dual 2-input NOR gate 74HC2G02; 74HCT2G02 To overcome these problems the double-wave soldering method was specifically developed. SOLDERING Introduction to soldering surface mount packages If wave soldering is used the following conditions must be observed for optimal results: This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 270 °C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively. • below 220 °C (SnPb process) or below 245 °C (Pb-free process) A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. – for all the BGA packages – for packages with a thickness ≥ 2.5 mm Manual soldering – for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called thick/large packages. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. • below 235 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. 2003 May 14 13 Philips Semiconductors Product specification Dual 2-input NOR gate 74HC2G02; 74HCT2G02 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE(1) WAVE BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable(3) DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS not PLCC(4), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP REFLOW(2) suitable suitable suitable not recommended(4)(5) suitable not recommended(6) suitable Notes 1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2003 May 14 14 Philips Semiconductors Product specification Dual 2-input NOR gate 74HC2G02; 74HCT2G02 DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2003 May 14 15 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA75 © Koninklijke Philips Electronics N.V. 2003 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 613508/03/pp16 Date of release: 2003 May 14 Document order number: 9397 750 11097