INTEGRATED CIRCUITS DATA SHEET 74HC1G00; 74HCT1G00 2-input NAND gate Product specification Supersedes data of 2001 Mar 02 2002 May 15 Philips Semiconductors Product specification 2-input NAND gate 74HC1G00; 74HCT1G00 FEATURES DESCRIPTION • Wide supply voltage range from 2.0 to 6.0 V The 74HC1G/HCT1G00 is a high speed Si-gate CMOS device. • Symmetrical output impedance • High noise immunity The 74HC1G/HCT1G00 provides the 2-input NAND function. The standard output currents are 1⁄2 compared to the 74HC/HCT00. • Low power dissipation • Balanced propagation delays • Very small 5 pins package • Output capability: standard. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 6.0 ns. TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC1G tPHL/tPLH propagation delay A, B to Y CI input capacitance CPD power dissipation capacitance CL = 15 pF; VCC = 5 V notes 1 and 2 HCT1G 7 10 ns 1.5 1.5 pF 19 21 pF Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; ∑ (CL × VCC2 × fo) = sum of outputs. 2. For HC1G the condition is VI = GND to VCC. For HCT1G the condition is VI = GND to VCC − 1.5 V. FUNCTION TABLE See note 1. INPUTS OUTPUT A B Y L L H L H H H L H H H L Note 1. H = HIGH voltage level; L = LOW voltage level. 2002 May 15 2 Philips Semiconductors Product specification 2-input NAND gate 74HC1G00; 74HCT1G00 ORDERING INFORMATION PACKAGES OUTSIDE NORTH AMERICA 74HC1G00GW TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE MARKING −40 to +125 °C 5 SC-88A plastic SOT353 HA 74HCT1G00GW −40 to +125 °C 5 SC-88A plastic SOT353 TA 74HC1G00GV −40 to +125 °C 5 SC-74A plastic SOT753 H00 74HCT1G00GV −40 to +125 °C 5 SC-74A plastic SOT753 T00 PINNING PIN SYMBOL DESCRIPTION 1 B data input B 2 A data input A 3 GND ground (0 V) 4 Y data output Y 5 VCC supply voltage handbook, halfpage B 1 A 2 GND 5 VCC handbook, halfpage 00 3 4 Y 1 B 2 A Y 4 MNA097 MNA096 Fig.1 Pin configuration. handbook, halfpage 1 Fig.2 Logic symbol. handbook, halfpage & B 4 Y 2 A MNA098 MNA099 Fig.3 IEC logic symbol. 2002 May 15 Fig.4 Logic diagram. 3 Philips Semiconductors Product specification 2-input NAND gate 74HC1G00; 74HCT1G00 RECOMMENDED OPERATING CONDITIONS 74HC1G SYMBOL PARAMETER 74HCT1G CONDITIONS UNIT MIN. TYP. MAX. MIN. TYP. MAX. VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 − VCC 0 − VCC V VO output voltage 0 − VCC 0 − VCC V Tamb operating ambient temperature see DC and AC characteristics per device −40 +25 +125 −40 +25 +125 °C tr,tf input rise and fall times VCC = 2.0 V − − 1000 − − − ns VCC = 4.5 V − − 500 − − 500 ns VCC = 6.0 V − − 400 − − − ns LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V); see note 1 and 2. SYMBOL PARAMETER VCC supply voltage IIK input diode current CONDITIONS MIN. MAX. UNIT −0.5 +7.0 V VI < −0.5 V or VI > VCC + 0.5 V − ±20 mA IOK output diode current VO < −0.5 V or VO > VCC + 0.5 V − ±20 mA IO output source or sink current −0.5 V < VO < VCC + 0.5 V − ±12.5 mA ICC VCC or GND current − ±25 mA Tstg storage temperature PD power dissipation per package for temperature range from −40 to +125 °C; note 3 −65 +150 °C − 200 mW Notes 1. Stresses beyond those listed may cause permanent damage to the device. These are stress rating only and functional operation of the device at these or any other conditions beyond those under ‘recommended operating conditions’ is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 3. Above 55 °C the value of PD derates linearly with 2.5 mW/K. 2002 May 15 4 Philips Semiconductors Product specification 2-input NAND gate 74HC1G00; 74HCT1G00 DC CHARACTERISTICS Family 74HC1G At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL VIL VOH VOL −40 to +85 PARAMETER OTHER VIH Tamb (°C) TYP.(1) MAX. MIN. UNIT MAX. 1.5 1.2 − 1.5 − V 4.5 3.15 2.4 − 3.15 − V 6.0 4.2 3.2 − 4.2 − V 2.0 − 0.8 0.5 − 0.5 V 4.5 − 2.1 1.35 − 1.35 V 6.0 − 2.8 1.8 − 1.8 V VI = VIH or VIL; IO = −20 µA 2.0 1.9 2.0 − 1.9 − V VI = VIH or VIL; IO = −20 µA 4.5 4.4 4.5 − 4.4 − V VI = VIH or VIL; IO = −20 µA 6.0 5.9 6.0 − 5.9 − V VI = VIH or VIL; IO = −2.0 mA 4.5 4.13 4.32 − 3.7 − V VI = VIH or VIL; IO = −2.6 mA 6.0 5.63 5.81 − 5.2 − V VI = VIH or VIL; IO = 20 µA 2.0 − 0 0.1 − 0.1 V VI = VIH or VIL; IO = 20 µA 4.5 − 0 0.1 − 0.1 V VI = VIH or VIL; IO = 20 µA 6.0 − 0 0.1 − 0.1 V VI = VIH or VIL; IO = 2.0 mA 4.5 − 0.15 0.33 − 0.4 V VI = VIH or VIL; IO = 2.6 mA 6.0 − 0.16 0.33 − 0.4 V LOW-level input voltage LOW-level output voltage MIN. −40 to +125 2.0 HIGH-level input voltage HIGH-level output voltage VCC (V) ILI input leakage current VI = VCC or GND 6.0 − − 1.0 − 1.0 µA ICC quiescent supply current VI = VCC or GND; 6.0 IO = 0 − − 10 − 20 µA Note 1. All typical values are measured at Tamb = 25 °C. 2002 May 15 5 Philips Semiconductors Product specification 2-input NAND gate 74HC1G00; 74HCT1G00 Family 74HCT1G At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL Tamb (°C) −40 to +85 PARAMETER OTHER VCC (V) MIN. TYP.(1) −40 to +125 MAX. MIN. UNIT MAX. VIH HIGH-level input voltage 4.5 to 5.5 2.0 1.6 − 2.0 − V VIL LOW-level input voltage 4.5 to 5.5 − 1.2 0.8 − 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; IO = −20 µA 4.5 4.4 4.5 − 4.4 − V VI = VIH or VIL; IO = −2.0 mA 4.5 4.13 4.32 − 3.7 − V VI = VIH or VIL; IO = 20 µA 4.5 − 0 0.1 − 0.1 V VI = VIH or VIL; IO = 2.0 mA 4.5 − 0.15 0.33 − 0.4 V VOL LOW-level output voltage ILI input leakage current VI = VCC or GND 5.5 − − 1.0 − 1.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 10 − 20 µA ∆ICC additional supply current per input VI = VCC − 2.1 V; IO = 0 4.5 to 5.5 − − 500 − 850 µA Note 1. All typical values are measured at Tamb = 25 °C. 2002 May 15 6 Philips Semiconductors Product specification 2-input NAND gate 74HC1G00; 74HCT1G00 AC CHARACTERISTICS Type 74HC1G00 GND = 0 V; tr = tf ≤ 6.0 ns; CL = 50 pF. TEST CONDITIONS SYMBOL −40 to +85 PARAMETER WAVEFORMS tPHL/tPLH Tamb (°C) propagation delay A and B to Y see Figs 5 and 6 VCC (V) 2.0 MIN. − −40 to +125 TYP.(1) MAX. 25 115 MIN. − UNIT MAX. 135 ns 4.5 − 9 23 − 27 ns 6.0 − 8 20 − 23 ns Note 1. All typical values are measured at Tamb = 25 °C. Type 74HCT1G00 GND = 0 V; tr = tf ≤ 6.0 ns; CL = 50 pF. Tamb (°C) TEST CONDITIONS SYMBOL WAVEFORMS tPHL/tPLH propagation delay A and B to Y see Figs 5 and 6 VCC (V) 4.5 Note 1. All typical values are measured at Tamb = 25 °C. 2002 May 15 −40 to +85 PARAMETER 7 MIN. − −40 to +125 TYP.(1) MAX. 12 24 MIN. − UNIT MAX. 27 ns Philips Semiconductors Product specification 2-input NAND gate 74HC1G00; 74HCT1G00 AC WAVEFORMS handbook, halfpage A, B input tPHL Y output VCC handbook, halfpage VM PULSE GENERATOR tPLH VI VO D.U.T. RT CL MNA101 VM MNA100 Definitions for test circuit: CL = Load capacitance including jig and probe capacitance (see “AC characteristics”). RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. For HC1G: VM = 50%; VI = GND to VCC. For HCT1G: VM = 1.3 V; VI = GND to 3.0 V. Fig.5 The input (A and B) to output (Y) propagation delays. 2002 May 15 Fig.6 Load circuitry for switching times. 8 Philips Semiconductors Product specification 2-input NAND gate 74HC1G00; 74HCT1G00 PACKAGE OUTLINES Plastic surface mounted package; 5 leads SOT353 D E B y X A HE 5 v M A 4 Q A A1 1 2 e1 3 bp c Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E (2) e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.1 OUTLINE VERSION SOT353 2002 May 15 REFERENCES IEC JEDEC EIAJ SC-88A 9 EUROPEAN PROJECTION ISSUE DATE 97-02-28 Philips Semiconductors Product specification 2-input NAND gate 74HC1G00; 74HCT1G00 Plastic surface mounted package; 5 leads SOT753 D E B y A X HE 5 v M A 4 Q A A1 c 1 2 3 Lp detail X bp e w M B 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.100 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.1 OUTLINE VERSION SOT753 2002 May 15 REFERENCES IEC JEDEC JEITA SC-74A 10 EUROPEAN PROJECTION ISSUE DATE 02-04-16 Philips Semiconductors Product specification 2-input NAND gate 74HC1G00; 74HCT1G00 SOLDERING If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 220 °C for thick/large packages, and below 235 °C for small/thin packages. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Wave soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. 2002 May 15 11 Philips Semiconductors Product specification 2-input NAND gate 74HC1G00; 74HCT1G00 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, HBGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO REFLOW(1) suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2002 May 15 12 Philips Semiconductors Product specification 2-input NAND gate 74HC1G00; 74HCT1G00 DATA SHEET STATUS DATA SHEET STATUS(1) PRODUCT STATUS(2) DEFINITIONS Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2002 May 15 13 Philips Semiconductors Product specification 2-input NAND gate 74HC1G00; 74HCT1G00 NOTES 2002 May 15 14 Philips Semiconductors Product specification 2-input NAND gate 74HC1G00; 74HCT1G00 NOTES 2002 May 15 15 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA74 © Koninklijke Philips Electronics N.V. 2002 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 613508/03/pp16 Date of release: 2002 May 15 Document order number: 9397 750 09714