INTEGRATED CIRCUITS DATA SHEET 74ALVC373 Octal D-type transparent latch; 3-state Product specification File under Integrated Circuits, IC24 2002 Feb 26 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC373 FEATURES DESCRIPTION • Wide supply voltage range from 1.65 to 3.6 V The 74ALVC373 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. • Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V). The 74ALVC373 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all internal latches. • 3.6 V tolerant inputs/outputs • CMOS LOW power consumption • Direct interface with TTL levels (2.7 to 3.6 V) The 74ALVC373 consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D-input changes. • Power-down mode • Latch-up performance exceeds ≤250 mA • ESD protection: 2000 V Human Body Model (JESD22-A114-A) 200 V Machine Model (JESD22-A115-A). When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. The ‘373’ is functionally identical to the ‘573’, but the ‘573’ have a different pin arrangement. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C. SYMBOL tPHL/tPLH PARAMETER propagation delay inputs Dn to output Qn CI input capacitance CPD power dissipation capacitance per buffer CONDITIONS UNIT VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ 3.0 ns VCC = 2.5 V; CL = 30 pF; RL = 500 Ω 2.3 ns VCC = 2.7 V; CL = 50 pF; RL = 500 Ω 2.4 ns VCC = 3.3 V; CL = 50 pF; RL = 500 Ω 2.2 ns 3.5 pF outputs enable 35 pF outputs disabled 14 pF VCC = 3.3 V; notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC and the latch is in transparent mode. 2002 Feb 26 TYP. 2 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC373 ORDERING INFORMATION PACKAGES TYPE NUMBER PINS PACKAGE MATERIAL CODE 74ALVC373D 20 SO plastic SOT163-1 74ALVC373PW 20 TSSOP plastic SOT360-1 FUNCTION TABLE See note 1. INPUT OUTPUTS OE LE Dn INTERNAL LATCHES Enable and read register (transparent mode) L H L L L L H H H H Latch and read register L L l L L L L h H H Latch register and disable outputs H X X X Z H L h H Z OPERATING MODES Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; X = don’t care; Z = high-impedance OFF-state. PINNING PIN SYMBOL DESCRIPTION 1 OE output enable input (active LOW) 2, 5, 6, 9, 12, 15, 16, 19 Q0 to Q7 3-state latch output 3, 4, 7, 8, 13, 14, 17, 18 D0 to D7 data input 10 GND ground (0 V) 11 LE latch enable input (active HIGH) 20 VCC supply voltage 2002 Feb 26 3 Q0 to Q7 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state handbook, halfpage 74ALVC373 OE 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 7 Q1 5 16 Q6 8 15 Q5 13 11 handbook, halfpage 3 4 373 Q2 6 14 D2 7 14 D5 17 D3 8 13 D4 18 Q3 9 12 Q4 GND 10 11 LE LE D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 OE 1 Q7 2 5 6 9 12 15 16 19 MNA186 MNA185 Fig.1 Pin configuration. handbook, halfpage 1 11 3 Fig.2 Logic symbol. handbook, halfpage EN 3 D0 Q0 2 4 D1 Q1 5 2 7 D2 Q2 6 5 8 D3 Q3 9 13 D4 14 D5 Q5 15 17 D6 Q6 16 18 D7 Q7 19 C1 1D 4 7 6 8 9 13 12 14 15 17 16 18 19 LATCH 1 to 8 3-STATE OUTPUTS 11 LE 1 OE MNA184 MNA187 Fig.3 IEE/IEC logic symbol. 2002 Feb 26 Q4 12 Fig.4 Function diagram. 4 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC373 LE handbook, halfpage LE LE D Q MNA692 LE Fig.5 Logic diagram (one latch). D0 D1 D2 D3 D4 D5 D6 D7 handbook, full pagewidth D Q D Q D Q D Q D Q D Q D Q D Q LATCH 1 LATCH 2 LATCH 3 LATCH 4 LATCH 5 LATCH 6 LATCH 7 LATCH 8 LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 MNA199 Fig.6 Logic diagram. 2002 Feb 26 5 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC373 RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC supply voltage 1.65 3.6 V VI input voltage 0 3.6 V VO output voltage VCC V Tamb operating ambient temperature tr, tf input rise and fall times enable mode; VCC = 1.65 to 3.6 V 0 disable mode; VCC = 1.65 to 3.6 V 0 3.6 V Power-down mode; VCC = 0 V 0 3.6 V −40 +85 °C VCC = 1.65 to 2.7 V 0 20 ns/V VCC = 2.7 to 3.6 V 0 10 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER VCC supply voltage IIK input diode current VI input voltage IOK output diode current VO output voltage CONDITIONS MIN. MAX. UNIT −0.5 +4.6 V − −50 mA −0.5 +4.6 V VO > VCC or VO < 0 − ±50 mA enable mode; notes 1 and 2 −0.5 VCC + 0.5 V disable mode −0.5 +4.6 V Power-down mode; note 2 −0.5 +4.6 V VO = 0 to VCC − ±50 mA VI < 0 IO output diode current IGND, ICC VCC or GND current − ±100 mA Tstg storage temperature −65 +150 °C Ptot power dissipation per package SO package above 70 °C derate linearly with 8 mW/K − 500 mW TSSOP package above 60 °C derate linearly with 5.5 mW/K − 500 mW Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. When VCC = 0 V (Power-down mode), the output voltage can be 3.6 V in normal operation. 2002 Feb 26 6 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC373 DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL VIL VOL VOH −40 to +85 PARAMETER VCC (V) OTHER VIH Tamb (°C) HIGH-level input voltage LOW-level input voltage LOW-level output voltage HIGH-level output voltage MIN. TYP.(1) UNIT MAX. 1.65 to 1.95 0.65 × VCC − − V − − V V 2.3 to 2.7 1.7 2.7 to 3.6 2 − − 1.65 to 1.95 − − 0.35 × VCC V 2.3 to 2.7 − − 0.7 V 2.7 to 3.6 − − 0.8 V VI = VIH or VIL; IO = 100 µA 1.65 to 3.6 − − 0.2 V VI = VIH or VIL; IO = 6 mA 1.65 − 0.11 0.3 V VI = VIH or VIL; IO = 12 mA 2.3 − 0.17 0.4 V VI = VIH or VIL; IO = 18 mA 2.3 − 0.25 0.6 V VI = VIH or VIL; IO = 12 mA 2.7 − 0.16 0.4 V VI = VIH or VIL; IO = 18 mA 3.0 − 0.23 0.4 V VI = VIH or VIL; IO = 24 mA 3.0 − 0.30 0.55 V VI = VIH or VIL; IO = −100 µA 1.65 to 3.6 VCC − 0.2 − − V VI = VIH or VIL; IO = −6 mA 1.65 1.25 1.51 − V VI = VIH or VIL; IO = −12 mA 2.3 1.8 2.10 − V VI = VIH or VIL; IO = −18 mA 2.3 1.7 2.01 − V VI = VIH or VIL; IO = −12 mA 2.7 2.2 2.53 − V VI = VIH or VIL; IO = −18 mA 3.0 2.4 2.76 − V VI = VIH or VIL; IO = −24 mA 3.0 2.2 2.68 − V II input leakage current VI = 3.6 V or GND 3.6 − ±0.1 ±5 µA IOZ 3-state output OFF-state current VI = VIH or VIL; VO = 3.6 V or GND; note 2 1.65 to 3.6 − 0.1 ±10 µA Ioff power OFF leakage VI or VO = 0 to 3.6 V current 0.0 − ±0.1 ±10 µA ICC quiescent supply current VI = VCC or GND; IO = 0 3.6 − 0.2 10 µA ∆ICC additional quiescent supply current per input pin VI = VCC − 0.6 V; IO = 0 3.0 to 3.6 − 5 750 µA Notes 1. All typical values are measured at VCC = 3.3 V and Tamb = 25 °C. 2. For transceivers, the parameter IOZ includes the input leakage current. 2002 Feb 26 7 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC373 AC CHARACTERISTICS Tamb (°C) TEST CONDITIONS SYMBOL WAVEFORMS tPHL/tPLH tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tW tsu th propagation delay Dn to Qn propagation delay LE to Qn 3-state output enable time OE to Qn 3-state output disable time OE to Qn LE pulse with HIGH set-up time Dn to LE hold time Dn to LE see Figs 7 and 11 see Figs 8 and 11 see Figs 9 and 11 see Figs 9 and 11 see Figs 8 and 11 see Figs 10 and 11 see Figs 10 and 11 Note 1. All typical values are measured at Tamb = 25 °C. 2002 Feb 26 −40 to +85 PARAMETER 8 VCC (V) MIN. TYP.(1) UNIT MAX. 1.65 to 1.95 1.0 2.5 5.4 ns 2.3 to 2.7 1.0 2.0 3.5 ns 2.7 1.0 2.3 3.6 ns 3.0 to 3.6 1.0 2.2 3.3 ns 1.65 to 1.95 1.0 2.8 6.0 ns 2.3 to 2.7 1.0 2.1 3.8 ns 2.7 1.0 2.4 3.7 ns 3.0 to 3.6 1.0 2.3 3.3 ns 1.65 to 1.95 1.5 3.0 6.4 ns 2.3 to 2.7 1.0 2.4 4.5 ns 2.7 1.5 3.0 4.6 ns 3.0 to 3.6 1.0 2.3 4.0 ns 1.65 to 1.95 1.5 3.4 7.0 ns 2.3 to 2.7 1.0 2.2 4.4 ns 2.7 1.5 2.8 4.4 ns 3.0 to 3.6 1.0 2.7 4.4 ns 1.65 to 1.95 3.8 1.0 − ns 2.3 to 2.7 3.3 0.8 − ns 2.7 3.3 2.0 − ns 3.0 to 3.6 3.3 2.2 − ns 1.65 to 1.95 0.8 0.1 − ns 2.3 to 2.7 0.8 0.1 − ns 2.7 0.8 0.1 − ns 3.0 to 3.6 0.8 0.1 − ns 1.65 to 1.95 0.8 −0.1 − ns 2.3 to 2.7 0.8 −0.2 − ns 2.7 0.8 −0.3 − ns 3.0 to 3.6 0.7 −0.1 − ns Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC373 AC WAVEFORMS handbook, halfpage VI VM Dn input GND t PHL t PLH VOH VM Qn output VOL MNA693 INPUT VCC VM VI tr = tf 0.5 × VCC VCC ≤ 2.0 ns 2.3 to 2.7 V 0.5 × VCC VCC ≤ 2.0 ns 2.7 V 1.5 V 2.7 V ≤ 2.5 ns 3.0 to 3.6 V 1.5 V 2.7 V ≤ 2.5 ns 1.65 to 1.95 V Fig.7 Input Dn to output Qn propagation delay times. 1/fmax handbook, full pagewidth VI LE input VM GND tW t PHL t PLH VOH VM Qn output VOL MNA694 INPUT VCC VM VI tr = tf 1.65 to 1.95 V 0.5 × VCC VCC ≤ 2.0 ns 2.3 to 2.7 V 0.5 × VCC VCC ≤ 2.0 ns 2.7 V 1.5 V 2.7 V ≤ 2.5 ns 3.0 to 3.6 V 1.5 V 2.7 V ≤ 2.5 ns Fig.8 Latch enable (LE) input pulse width and latch enable input to output (Qn) propagation delays. 2002 Feb 26 9 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC373 VI handbook, full pagewidth OE input VM GND t PLZ t PZL VCC Qn output LOW-to-OFF OFF-to-LOW VM VX VOL t PHZ Qn output HIGH-to-OFF OFF-to-HIGH t PZH VOH VY VM GND outputs enabled outputs disabled outputs enabled MNA395 INPUT VCC VM 1.65 to 1.95 V 0.5 × VCC VCC ≤ 2.0 ns 2.3 to 2.7 V 0.5 × VCC VCC ≤ 2.0 ns 2.7 V 1.5 V 2.7 V ≤ 2.5 ns VX = VOL + 0.3 V at VCC ≥ 2.7 V; VX = VOL + 0.15 V at VCC < 2.7 V; VY = VOH − 0.3 V at VCC ≥ 2.7 V; VY = VOH − 0.15 V at VCC < 2.7 V. 3.0 to 3.6 V 1.5 V 2.7 V ≤ 2.5 ns VOL and VOH are typical output voltage drop that occur with the output load. VI tr = tf Fig.9 3-state enable and disable times. 2002 Feb 26 10 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC373 VI handbook, full pagewidth VM Dn input GND th th t su t su VI LE input VM GND MNA695 INPUT VCC VM tr = tf VI 1.65 to 1.95 V 0.5 × VCC VCC ≤ 2.0 ns 2.3 to 2.7 V 0.5 × VCC VCC ≤ 2.0 ns 2.7 V 1.5 V 2.7 V ≤ 2.5 ns 3.0 to 3.6 V 1.5 V 2.7 V ≤ 2.5 ns The shaded areas indicate when the input is permitted to change for predictable output performance. Fig.10 The data set-up and hold times for Dn input to LE input. VEXT handbook, full pagewidth VCC PULSE GENERATOR VI RL VO D.U.T. CL RT RL MNA616 VCC RL VEXT VI CL 1.65 to 1.95 V VCC 30 pF 1 kΩ open GND 2 × VCC 2.3 to 2.7 V VCC 30 pF 500 Ω open GND 2 × VCC 2.7 V 2.7 V 50 pF 500 Ω open GND 6V 3.0 to 3.6 V 2.7 V 50 pF 500 Ω open GND 6V tPLH/tPHL tPZH/tPHZ tPZL/tPLZ RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.11 Load circuitry for switching times. 2002 Feb 26 11 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC373 PACKAGE OUTLINES SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.10 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.050 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 2002 Feb 26 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-05-22 99-12-27 12 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC373 TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.10 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 2002 Feb 26 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 99-12-27 MO-153 13 o Philips Semiconductors Product specification Octal D-type transparent latch; 3-state SOLDERING 74ALVC373 If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 220 °C for thick/large packages, and below 235 °C for small/thin packages. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Wave soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. 2002 Feb 26 14 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC373 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO REFLOW(1) suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2002 Feb 26 15 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74ALVC373 DATA SHEET STATUS DATA SHEET STATUS(1) PRODUCT STATUS(2) DEFINITIONS Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2002 Feb 26 16 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state NOTES 2002 Feb 26 17 74ALVC373 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state NOTES 2002 Feb 26 18 74ALVC373 Philips Semiconductors Product specification Octal D-type transparent latch; 3-state NOTES 2002 Feb 26 19 74ALVC373 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA74 © Koninklijke Philips Electronics N.V. 2002 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 613508/01/pp20 Date of release: 2002 Feb 26 Document order number: 9397 750 09437