INTEGRATED CIRCUITS DATA SHEET 74ALVCH16543 16-bit D-type registered transceiver; 3-state Product specification Supersedes data of 1998 Aug 31 File under Integrated Circuits, IC24 1999 Nov 23 Philips Semiconductors Product specification 16-bit D-type registered transceiver; 3-state FEATURES 74ALVCH16543 Separate latch enable (nLEAB, nLEBA) and output enable (nOEAB, nOEBA) inputs are provided for each register to permit independent control in either direction of the data flow. • In accordance with JEDEC standard no 8-1A • CMOS low power consumption • Direct interface with TTL levels The ‘16543’ contains two sections each consisting of two sets of eight D-type latches with separate inputs and controls for each set. For data flow from A to B, for example, the A-to-B enable (nEAB, where n equals 1 or 2) inputs must be LOW in order to enter data from nA0 to nA7, or take data from nB0 to nB7, as indicated in the function table. With nEAB LOW, a LOW signal on the A-to-B latch enable (nLEAB) input makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the nLEAB signal stores the A data into the latches. With nEAB and nOEAB both LOW, the 3-state B output buffers are active and display the data present at the output of the A latches. Similarly, the nEBA, nLEBA and nOEBA signals control the data flow from B-to-A. • MULTIBYTE flow-through pin-out architecture • 16-bit transceiver with D-type latch • Combines 16245 and 16373 type functions in one chip • Back-to-back registers for storage • Output drive capability 50 Ω transmission lines at 85 °C • Separate controls for data flow in each direction • All data inputs have bus hold • 3-state non-inverting outputs for bus oriented applications • Current drive ±24 mA at 3.0 V. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. DESCRIPTION The 74ALVCH16543 is a dual octal registered transceiver. Each section contains two sets of D-type latches for temporary storage of the data flow in either direction. FUNCTION TABLE See note 1. INPUTS OUTPUTS STATUS nOEXX nEXX nLEXX nBn, nAn H X X X Z disabled X H X X Z disabled disabled and latch L ↑ L h Z L ↑ L l Z L L ↑ h H L L ↑ l L L L L H H L L L L L L L H X NC latch and display transparent hold Note 1. XX = AB for A-to-B direction, BA for B-to-A direction; H = HIGH voltage level; L = LOW voltage level; h = HIGH state must be present one set-up time before the LOW-to-HIGH transition of nLEAB, nLEBA, nEAB or nEBA; l = LOW state must be present one set-up time before the LOW-to-HIGH transition of nLEAB, nLEBA, nEAB or nEBA; X = don’t care; NC = no change; ↑ = LOW-to-HIGH level transition; Z = high-impedance OFF-state. 1999 Nov 23 2 Philips Semiconductors Product specification 16-bit D-type registered transceiver; 3-state 74ALVCH16543 QUICK REFERENCE DATA Ground = 0; Tamb = 25 °C; tr = tf = 2.5 ns SYMBOL PARAMETER CONDITIONS tPHL/tPLH propagation delay nAn, nBn to nBn, nAn CI input capacitance CPD power dissipation capacitance per latch TYPICAL CL = 50 pF; VCC = 3.3 V UNIT 3.8 ns 4.0 pF outputs enabled 44 pF outputs disabled 14 pF notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + Σ (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in Volts; Σ (CL × VCC2 × fo) = sum of outputs. 2. The condition is VI = GND to VCC. ORDERING INFORMATION PACKAGE OUTSIDE NORTH AMERICA 74ALVCH16543DGG NORTH AMERICA TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE −40 to +85 °C 56 TSSOP plastic SOT364-1 ACH16543 DGG PINNING PIN SYMBOL DESCRIPTION 1 and 28 1OEAB, 2OEAB output enable A-to-B for register 1 or 2 2 and 27 1LEAB, 2LEAB latch enable A-to-B for register 1 or 2 3 and 26 1EAB, 2EAB A-to-B enable for register 1 or 2 4, 11, 18, 25, 32, 39, 46 and 53 GND ground (0 V) 5, 6, 8, 9, 10, 12, 13 and 14 1A0 to 1A7 data inputs/outputs 7, 22, 35 and 50 VCC DC supply voltage 15, 16, 17, 19, 20, 21, 23 and 24 2A0 to 2A7 data inputs/outputs 29 and 56 2OEBA, 1OEBA output enable B-to-A for register 1 or 2 30 and 55 2LEBA, 1LEAB latch enable B-to-A for register 1 or 2 31 and 54 2EBA, 1EBA B-to-A enable for register 1 or 2 33, 34, 36, 37, 38, 40, 41 and 42 2B7 to 2B0 data inputs/outputs 43, 44, 45, 47, 48, 49, 51 and 52 1B7 to 1B0 data inputs/outputs 1999 Nov 23 3 Philips Semiconductors Product specification 16-bit D-type registered transceiver; 3-state 74ALVCH16543 handbook, halfpage 1OEAB 1 56 1OEBA 1LEAB 2 55 1LEBA 1EAB 3 54 1EBA GND 4 53 GND 1A0 5 52 1B0 1A1 6 51 1B1 VCC 7 50 VCC 1A2 8 49 1B2 1A3 9 48 1B3 1A4 10 47 1B4 GND 11 46 GND 1A5 12 45 1B5 1A6 13 44 1B6 handbook, halfpage VCC data input to internal circuit MNA300 43 1B7 1A7 14 16543 2A0 15 42 2B0 2A1 16 41 2B1 2A2 17 40 2B2 GND 18 39 GND 2A3 19 38 2B3 2A4 20 37 2B4 2A5 21 36 2B5 VCC 22 35 VCC 2A6 23 34 2B6 2A7 24 33 2B7 GND 25 32 GND 2EAB 26 31 2EBA 2LEAB 27 30 2LEBA 2OEAB 28 29 2OEBA Fig.2 Bus hold circuit. MNA297 Fig.1 Pin configuration. 1999 Nov 23 4 Philips Semiconductors Product specification 16-bit D-type registered transceiver; 3-state handbook, full pagewidth 5 6 8 9 10 12 13 14 56 1 3 54 2 55 1A0 1B0 1A1 1B1 1A2 1B2 1A3 1B3 1A4 1B4 1A5 1B5 1A6 1B6 1A7 1B7 52 15 51 16 49 17 48 19 47 20 45 21 44 23 43 24 1OEBA 29 1OEAB 28 1EAB 26 1EBA 31 1LEAB 27 1LEBA 30 74ALVCH16543 2A0 2A1 2A2 2A3 2B0 2B1 42 2B2 2B3 40 2B4 2B5 2A4 2A5 2B6 2B7 2A6 2A7 2OEBA 2OEAB 2EAB 2EBA 2LEAB 2LEBA MNA298 Fig.3 Logic symbol. handbook, full pagewidth 56 54 55 1 3 2 29 28 30 31 27 26 1EN3 G1 1C5 2EN4 G2 2C6 EN7 [BA] EN8 [AB] C9 G10 C11 G12 52 15 51 16 8 49 17 40 9 48 19 38 10 47 20 37 12 45 21 36 13 44 23 34 14 43 24 33 5 3 6D 6 5D 4 9 12D 11D 10 MNA299 Fig.4 IEC logic symbol. 1999 Nov 23 5 42 41 41 38 37 36 34 33 Philips Semiconductors Product specification 16-bit D-type registered transceiver; 3-state handbook, full pagewidth 74ALVCH16543 nOEAB nEBA nLEBA nOEAB nEAB nLEAB LE D nA1 LE 8 IDENTICAL CHANNELS D to 7 other channels Fig.5 Logic diagram (one section). 1999 Nov 23 nB1 6 MNA301 Philips Semiconductors Product specification 16-bit D-type registered transceiver; 3-state 74ALVCH16543 RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT DC supply voltage VCC for maximum speed performance CL = 30 pF 2.3 2.5 2.7 V for maximum speed performance CL = 50 pF 3.0 3.3 3.6 V 1.2 2.4 3.6 V VI DC input voltage for low-voltage applications 0 − VCC V VO DC output voltage 0 − VCC V Tamb operating ambient temperature in free air −40 − +85 °C tr, tf input rise and fall times VCC = 2.3 to 3.0 V 0 − 20 ns/V VCC = 3.0 to 3.6 V 0 − 10 ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC DC supply voltage −0.5 +4.6 V IIK DC input diode current VI < 0 − −50 mA VI DC input voltage note 1 −0.5 +4.6 V mA IOK DC output diode current VO > VCC or VO < 0 − ±50 VO DC output voltage note 1 −0.5 VCC + 0.5 V IO DC output source or sink current VO = 0 to VCC − ±50 mA ICC, IGND DC VCC or GND current − ±100 mA Tstg storage temperature −65 +150 °C Ptot power dissipation − 600 mW for temperature range: −40 to +125 °C; note 2 Note 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. Above 55 °C the value of Ptot derates linearly with 8 mW/K. 1999 Nov 23 7 Philips Semiconductors Product specification 16-bit D-type registered transceiver; 3-state 74ALVCH16543 DC CHARACTERISTICS Over recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb = −40 TO +85 °C TEST CONDITIONS SYMBOL PARAMETER VI (V) VIH VIL VOH VOL OTHER HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VIH or VIL VIH or VIL VCC (V) TYP.(1) MIN. UNIT MAX. 2.3 to 2.7 1.7 1.2 − V 2.7 to 3.6 2.0 1.5 − V 2.3 to 2.7 − 1.2 0.7 V 2.7 to 3.6 − 1.5 0.8 V − V IO = −100 µA 2.3 to 3.6 VCC − 0.2 VCC IO = −6 mA 2.3 VCC − 0.3 VCC − 0.08 − V IO = −12 mA 2.3 VCC − 0.6 VCC − 0.26 − V IO = −12 mA 2.7 VCC − 0.5 VCC − 0.14 − V IO = −12 mA 3.0 VCC − 0.6 VCC − 0.09 − V IO = −24 mA 3.0 VCC −1.0 VCC − 0.28 − V IO = 100 µA 2.3 to 3.6 − GND 0.20 V IO = 6 mA 2.3 − 0.07 0.40 V IO = 12 mA 2.3 − 0.15 0.70 V IO = 12 mA 2.7 − 0.14 0.40 V IO = 24 mA 3.0 − 0.27 0.55 V 2.3 to 3.6 − 0.1 5 µA Il input leakage current VCC or GND IOZ 3-state output OFF-state current VIH or VIL VO = VCC or GND 2.3 to 3.6 − 0.1 10 µA ICC quiescent supply voltage VCC or GND IO = 0 2.3 to 3.6 − 0.2 40 µA ∆ICC additional quiescent supply VCC − 0.6 current given per data I/O pin with bus hold IO = 0 2.3 to 3.6 − 150 750 µA IBHL bus hold LOW sustaining current 0.7(2) 2.3(2) 45 − 0.8(2) 3.0(2) 75 150 bus hold HIGH sustaining current 1.7(2) 2.3(2) −45 2.0(2) 3.0(2) −75 500 µA −500 µA IBHH IBHLO bus hold LOW overdrive current 3.6(2) IBHHO bus hold LOW overdrive current 3.6(2) Notes 1. All typical values are measured at Tamb = 25 °C. 2. Valid for data inputs of bus hold parts. 1999 Nov 23 8 µA µA −175 Philips Semiconductors Product specification 16-bit D-type registered transceiver; 3-state 74ALVCH16543 AC CHARACTERISTICS FOR VCC = 2.3 TO 2.7 V Ground = 0 V; tr = tf ≤ 2.0 ns; CL = 30 pF. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS tPHL/tPLH VCC (V) Tamb = −40 TO +85 °C MIN. TYP.(1) UNIT MAX. propagation delay nAn, nBn to nBn, nAn see Figs 6 and 10 2.3 to 2.7 1.0 3.4 5.1 ns propagation delay nLEAB, nLEBA to nBn, nAn see Figs 7 and 10 2.3 to 2.7 1.0 3.3 6.5 ns tPZH/tPZL 3-state output enable time see Figs 8 and 10 nOEBA, nOEAB to nAn, nBn 2.3 to 2.7 1.0 3.3 6.8 ns tPHZ/tPLZ 3-state output disable time see Figs 8 and 10 nOEBA, nOEAB to nAn, nBn 2.3 to 2.7 1.0 2.9 5.7 ns tPZH/tPZL 3-state output enable time nEBA, nEAB to nAn, nBn see Figs 8 and 10 2.3 to 2.7 1.0 3.3 7.2 ns tPHZ/tPLZ 3-state output disable time nEBA, nEAB to nAn, nBn see Figs 8 and 10 2.3 to 2.7 1.3 3.3 6.1 ns tW nLEXX pulse width LOW see Figs 7 and 10 2.3 to 2.7 3.3 1.2 − ns tsu set-up time nAn, nBn to nLEXX, nEXX see Figs 9 and 10 2.3 to 2.7 1.2 0.2 − ns th hold time nAn, nBn to nLEXX, nEXX see Figs 9 and 10 2.3 to 2.7 1.2 0.2 − ns Note 1. All typical values are measured at Tamb = 25 °C and VCC = 2.5 V. 1999 Nov 23 9 Philips Semiconductors Product specification 16-bit D-type registered transceiver; 3-state 74ALVCH16543 AC CHARACTERISTICS FOR VCC = 2.7 V AND VCC = 3.0 V TO 3.6 V Ground = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF. Tamb = −40 TO +85 °C TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS tPHL/tPLH tPZH/tPZL tPHZ/tPLZ tPZH/tPZL tPHZ/tPLZ tW tsu th propagation delay nAn, nBn to nBn, nAn see Figs 6 and 10 propagation delay nLEAB, nLEBA to nBn, nAn see Figs 7 and 10 3-state output enable time see Figs 8 and 10 nOEBA, nOEAB to nAn, nBn 3-state output disable time see Figs 8 and 10 nOEBA, nOEAB to nAn, nBn 3-state output enable time nEBA, nEAB to nAn, nBn see Figs 8 and 10 3-state output disable time nEBA, nEAB to nAn, nBn see Figs 8 and 10 nLEXX pulse width LOW see Figs 7 and 10 set-up time nAn, nBn to nLEXX, nEXX see Figs 9 and 10 hold time nAn, nBn to nLEXX, nEXX see Figs 9 and 10 2. Typical values at VCC = 3.0 V. 10 TYP.(1) UNIT MAX. 2.9 4.8 ns 3.0 to 3.6 1.0 3.8(2) 4.3 ns 2.7 − 3.6 6.2 ns 3.0 to 3.6 1.4 3.1(2) 5.0 ns 2.7 − 3.4 6.3 ns 3.0 to 3.6 1.0 2.9(2) 5.3 ns 2.7 − 3.3 4.8 ns 3.0 to 3.6 1.0 3.2(2) 4.6 ns 2.7 − 3.5 6.9 ns 3.0 to 3.6 1.0 3.0(2) 5.6 ns 2.7 − 3.5 6.2 ns 1.1 3.3(2) 5.1 ns 2.7 3.3 1.3 − ns 3.0 to 3.6 3.3 0.9(2) − ns 2.7 0.8 0.2 − ns 3.0 to 3.6 1.3 0.1(2) − ns 2.7 0.4 0.1 − ns 0.7 0.2(2) − ns 3.0 to 3.6 1. All typical values are measured at Tamb = 25 °C. MIN. − 2.7 3.0 to 3.6 Notes 1999 Nov 23 VCC (V) Philips Semiconductors Product specification 16-bit D-type registered transceiver; 3-state AC WAVEFORMS 74ALVCH16543 Notes: VCC = 2.3 to 2.7 V VM = 0.5VCC; VX = VOL + 150 mV; VY = VOH − 150 mV; VI = VCC; VOL and VOH are typical output voltage drop that occur with the output load. handbook, halfpage VI nAn, nBn Notes: VCC = 3.0 to 3.6 V and VCC = 2.7 V VM input GND VM = 1.5 V; tPHL tPLH VX = VOL + 300 mV; VOH nBn, nAn output VY = VOH − 300 mV; VM VI = 2.7 V; VOL Fig.6 MNA302 VOL and VOH are typical output voltage drop that occur with the output load. The inputs nAn, nBn to outputs nBn, nAn propagation delay times. VI handbook, full pagewidth nLEXX input VM GND tW tPHL tPLH VOH nAn, nBn output VM VOL MNA303 Fig.7 The latch enable inputs nLEXX pulse width, the latch enable inputs to output nBn, nAn propagation delays. 1999 Nov 23 11 Philips Semiconductors Product specification 16-bit D-type registered transceiver; 3-state 74ALVCH16543 VI handbook, full pagewidth nOEXX, nEXX input VM GND tPLZ tPZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ tPZH VOH VY output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs enabled outputs disabled MNA304 Fig.8 The 3-state enable and disable times. VI handbook, full pagewidth VM nAn, nBn input GND th th tsu tsu VI nLEXX, nEXX input VM GND MNA305 Fig.9 The data set-up and hold times for the nAn, nBn input to the nLEXX input. 1999 Nov 23 12 Philips Semiconductors Product specification 16-bit D-type registered transceiver; 3-state 74ALVCH16543 S1 handbook, full pagewidth VCC PULSE GENERATOR VI RL 500 Ω VO 2 × VCC open GND D.U.T. CL 50 pF RT RL 500 Ω MNA296 TEST S1 VCC Definitions for test circuit. CL = load capacitance including jig and probe capacitance (See Chapter “AC characteristics”) RL = load resistance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. VI tPLH/tPHL open tPLZ/tPZL 2 × VCC <2.7 V tPHZ/tPZH GND 2.7 to 3.6 V 2.7 V VCC Fig.10 Test circuitry for switching times. 1999 Nov 23 13 Philips Semiconductors Product specification 16-bit D-type registered transceiver; 3-state 74ALVCH16543 PACKAGE OUTLINE TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 E D A X c HE y v M A Z 56 29 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 detail X 28 w M bp e 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 14.1 13.9 6.2 6.0 0.5 8.3 7.9 1.0 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.5 0.1 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT364-1 1999 Nov 23 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 93-02-03 95-02-10 MO-153EE 14 o Philips Semiconductors Product specification 16-bit D-type registered transceiver; 3-state SOLDERING 74ALVCH16543 If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering Manual soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. To overcome these problems the double-wave soldering method was specifically developed. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 1999 Nov 23 15 Philips Semiconductors Product specification 16-bit D-type registered transceiver; 3-state 74ALVCH16543 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable suitable(2) suitable suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1999 Nov 23 16 Philips Semiconductors Product specification 16-bit D-type registered transceiver; 3-state NOTES 1999 Nov 23 17 74ALVCH16543 Philips Semiconductors Product specification 16-bit D-type registered transceiver; 3-state NOTES 1999 Nov 23 18 74ALVCH16543 Philips Semiconductors Product specification 16-bit D-type registered transceiver; 3-state NOTES 1999 Nov 23 19 74ALVCH16543 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com SCA 68 © Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 245004/02/pp20 Date of release: 1999 Nov 23 Document order number: 9397 750 05255