INFINEON Q67100

4M x 32-Bit Dynamic RAM Module
HYM 324020S/GS-50/-60
Advanced Information
•
4 194 304 words by 32-bit organization (alternative 8 388 608 words by 16-bit)
•
Fast access and cycle time
50 ns access time
90 ns cycle time (-50 version)
60 ns access time
110 ns cycle time (-60 version)
•
Fast page mode capability
35 ns cycle time (-50 version)
40 ns cycle time (-60 version)
•
Single + 5 V (± 10 %) supply
•
Low power dissipation
max. 5280 mW active (HYM 324020S/GS-50)
max. 4840 mW active (HYM 324020S/GS-60)
CMOS – 44 mW standby
TTL
–88 mW standby
•
CAS-before-RAS refresh
RAS-only-refresh
Hidden-refresh
•
8 decoupling capacitors mounted on substrate
•
All inputs, outputs and clocks fully TTL compatible
•
72 pin Single in-Line Memory Module with 22.86 mm (900 mil) height
•
Utilizes eight 4Mx4-DRAMs in 300mil wide SOJ packages
•
2048 refresh cycles / 32 ms
•
Optimized for use in byte-write non-parity applications
•
Tin-Lead contact pads (S - version)
•
Gold contact pads (GS - version)
Semiconductor Group
1
12.95
HYM 324020S/GS-50/-60
4M x 32-Bit
The HYM 324020S/GS-50/-60 is a 16 MByte DRAM module organized as 4 194 304 words by
32-bit in a 72-pin single-in-line package comprising eight HYB 5117400BJ 4M x 4 DRAMs in 300
mil wide SOJ-packages mounted together with eight 0.2 µF ceramic decoupling capacitors on a PC
board.
The HYM 324020S/GS-50/-60 can also be used as a 8 388 608 words by 16-bits dynamic RAM
module by means of connecting DQ0 and DQ16, DQ1 and DQ17, DQ2 and DQ18, …, DQ15 and
DQ31, respectively.
Each HYB 5117400BJ is described in the data sheet and is fully electrical tested and processed
according to SIEMENS standard quality procedure prior to module assembly. After assembly onto
the board, a further set of electrical tests is performed.
The speed of the module can be detected by the use of four presence detect pins.
The common I/O feature on the HYM 324020S/GS-50/-60 dictates the use of early write cycles.
Ordering Information
Type
Ordering Code
Package
Description
HYM 324020S-50
on request
L-SIM-72-12
DRAM Module
(access time 50 ns)
HYM 324020S-60
Q67100-Q979
L-SIM-72-12
DRAM Module
(access time 60 ns)
HYM 324020GS-50
on request
L-SIM-72-12
DRAM Module
(access time 50 ns)
HYM 324020GS-60
Q67100-Q2005
L-SIM-72-12
DRAM Module
(access time 60 ns)
Semiconductor Group
2
HYM 324020S/GS-50/-60
4M x 32-Bit
Pin Configuration
Pin Names
VSS
DQ16
DQ17
DQ18
DQ19
N.C.
A1
A3
A5
A10
DQ20
DQ21
DQ22
DQ23
N.C.
A8
N.C.
N.C.
1 DQ0 2
3 DQ1 4
5 DQ2 6
7 DQ3 8
9 VCC 10
11 A0
12
13 A2
14
15 A4 16
17 A6 18
19 DQ4 20
21 DQ5 22
23 DQ6 24
25 DQ7 26
27 A7
28
29 VCC 30
31 A9
32
33 RAS2 34
35 N.C. 36
N.C.
VSS
CAS2
CAS1
N.C.
WE
DQ8
DQ9
DQ10
DQ11
DQ12
VCC
DQ13
DQ14
DQ15
PD0
PD2
N.C.
37 N.C. 38
39 CAS0 40
41 CAS3 42
43 RAS0 44
45 N.C. 46
47 N.C. 48
49 DQ24 50
51 DQ25 52
53 DQ26 54
55 DQ27 56
57 DQ28 58
59 DQ29 60
61 DQ30 62
63 DQ31 64
65 N.C. 66
67 PD1 68
69 PD3 70
71 VSS 72
Semiconductor Group
A0-A10
Address Inputs for
HYM 324020S/GS
DQ0-DQ31
Data Input/Output
CAS0 - CAS3
Column Address Strobe
RAS0, RAS2
Row Address Strobe
WE
Read/Write Input
VCC
Power (+ 5 V)
VSS
Ground
PD
Presence Detect Pin
N.C.
No Connection
Presence Detect Pins
3
-50
-60
PD0
VSS
VSS
PD1
N.C.
N.C.
PD2
VSS
N.C.
PD3
VSS
N.C.
HYM 324020S/GS-50/-60
4M x 32-Bit
RAS0
CAS0
CAS RAS
I/O1-I/O4
OE
D0
DQ0-DQ3
CAS RAS
I/O1-I/O4
OE
D1
DQ4-DQ7
CAS1
DQ8-DQ11
CAS RAS
I/O1-I/O4
OE
D2
DQ12-DQ15
CAS RAS
I/O1-I/O4
OE
D3
RAS2
CAS2
CAS RAS
I/O1-I/O4
OE
D4
DQ16-DQ19
CAS RAS
I/O1-I/O4
OE
D5
DQ20-DQ23
CAS3
DQ24-DQ27
CAS RAS
I/O1-I/O4
OE
D6
DQ28-DQ31
CAS RAS
I/O1-I/O4
D7
OE
A0 - A10
WE
VCC
D0 - D7
D0 - D7
C0 - C7
VSS
Block Diagram
Semiconductor Group
4
HYM 324020S/GS-50/-60
4M x 32-Bit
Absolute Maximum Ratings
Operation temperature range ......................................................................................... 0 to + 70 °C
Storage temperature range......................................................................................... – 55 to 125 °C
Input/output voltage ............................................................................–0.5V to min (Vcc+0.5, 7.0) V
Power supply voltage...................................................................................................... – 1 to + 7 V
Power dissipation................................................................................................................... 6.72 W
Data out current (short circuit) ................................................................................................ 50 mA
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics
TA = 0 to 70 °C, VSS = 0 V, VCC = 5 V ± 10 %; tT = 5 ns
Parameter
Symbol
Limit Values
min.
max.
Unit Test
Condition
Input high voltage
VIH
2.4
Vcc+0.5
V
1)
Input low voltage
VIL
– 0.5
0.8
V
1)
Output high voltage (IOUT = – 5 mA)
VOH
2.4
–
V
1)
Output low voltage (IOUT = 4.2 mA)
VOL
–
0.4
V
1)
Input leakage current
(0 V ≤ VIH ≤ Vcc + 0.3V, all other pins = 0 V)
II(L)
– 20
20
µA
1)
Output leakage current
(DO is disabled, 0 V ≤ VOUT ≤ Vcc + 0.3V)
IO(L)
– 10
10
µA
1)
Average VCC supply current:
ICC1
–
–
960
880
mA
mA
2) 3) 4)
–
16
mA
–
–
–
960
880
mA
mA
2) 4)
–
–
320
280
mA
mA
2) 3) 4)
-50 ns version
-60 ns version
(RAS, CAS, address cycling: tRC = tRC min.)
Standby VCC supply current
(RAS = CAS = VIH)
ICC2
Average VCC supply current, during RAS-only
refresh cycles:
-50 ns version
-60 ns version
(RAS cycling, CAS = VI,H, tRC = tRC min.)
ICC3
Average VCC supply current,
ICC4
during fast page mode:
-50 ns version
-60 ns version
(RAS = VIL, CAS, address cycling:tPC = tPC min.)
Semiconductor Group
5
2) 3) 4)
2) 4)
2) 3) 4)
HYM 324020S/GS-50/-60
4M x 32-Bit
DC Characteristics (cont’d)
TA = 0 to 70 °C, VSS = 0 V, VCC = 5 V ± 10 %; tT = 5 ns
Parameter
Symbol
Standby VCC supply current
(RAS = CAS = VCC – 0.2 V)
ICC5
Average VCC supply current, during CASbefore-RAS refresh mode: -50 ns version
-60 ns version
(RAS, CAS cycling: tRC = tRC min.)
ICC6
Limit Values
min.
max.
Unit Test
Condition
–
8
mA
1)
–
–
960
880
mA
mA
2) 4)
2) 4)
Capacitance
TA = 0 to 70 °C, VCC = 5 V ± 10 %, f = 1 MHz
Parameter
Symbol
Limit Values
min.
max.
Unit
Input capacitance (A0 to A10,WE)
CI1
–
75
pF
Input capacitance (RAS0, RAS2)
CI2
–
45
pF
Input capacitance (CAS0 - CAS3)
CI3
–
25
pF
I/O capacitance
(DQ0-DQ31)
CIO
–
15
pF
Semiconductor Group
6
HYM 324020S/GS-50/-60
4M x 32-Bit
AC Characteristics 5)6)
TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 5 ns
Parameter
Limit Values
Symbol
-50
Unit
Note
-60
min.
max.
min.
max.
common parameters
Random read or write cycle time
tRC
90
–
110
–
ns
RAS precharge time
tRP
30
–
40
–
ns
RAS pulse width
tRAS
50
10k
60
10k
ns
CAS pulse width
tCAS
13
10k
15
10k
ns
Row address setup time
tASR
0
–
0
–
ns
Row address hold time
tRAH
8
–
10
–
ns
Column address setup time
tASC
0
–
0
–
ns
Column address hold time
tCAH
10
–
15
–
ns
RAS to CAS delay time
tRCD
18
37
20
45
RAS to column address delay time
tRAD
13
25
15
30
ns
RAS hold time
tRSH
13
15
–
ns
CAS hold time
tCSH
50
60
–
ns
CAS to RAS precharge time
tCRP
5
–
5
–
ns
Transition time (rise and fall)
tT
3
50
3
50
ns
Refresh period
tREF
–
32
–
32
ms
Access time from RAS
tRAC
–
50
–
60
ns
8, 9
Access time from CAS
tCAC
–
13
–
15
ns
8, 9
Access time from column address
tAA
–
25
–
30
ns
8,10
Column address to RAS lead time
tRAL
25
–
30
–
ns
Read command setup time
tRCS
0
–
0
–
ns
Read command hold time
tRCH
0
–
0
–
ns
11
Read command hold time referenced to
RAS
tRRH
0
–
0
–
ns
11
CAS to output in low-Z
tCLZ
0
–
0
–
ns
8
Output buffer turn-off delay
tOFF
0
13
0
15
ns
12
7
Read Cycle
Semiconductor Group
7
HYM 324020S/GS-50/-60
4M x 32-Bit
AC Characteristics (cont’d) 5)6)
TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 5 ns
Parameter
Limit Values
Symbol
-50
Unit
Note
-60
min.
max.
min.
max.
Early Write Cycle
Write command hold time
tWCH
8
–
10
–
ns
Write command pulse width
tWP
8
–
10
–
ns
Write command setup time
tWCS
0
–
0
–
ns
Write command to RAS lead time
tRWL
13
–
15
–
ns
Write command to CAS lead time
tCWL
13
–
15
–
ns
Data setup time
tDS
0
–
0
–
ns
14
Data hold time
tDH
10
–
10
–
ns
14
Fast page mode cycle time
tPC
35
–
40
–
ns
CAS precharge time
tCP
10
–
10
–
ns
Access time from CAS precharge
tCPA
–
30
–
35
ns
RAS pulse width
tRAS
50
200k
60
200k
ns
CAS precharge to RAS Delay
tRHCP
30
–
35
–
ns
CAS setup time
tCSR
10
–
10
–
ns
CAS hold time
tCHR
10
–
10
–
ns
RAS to CAS precharge time
tRPC
5
–
5
–
ns
Write to RAS precharge time
tWRP
10
–
10
–
ns
Write hold time referenced to RAS
tWRH
10
–
10
–
ns
13
Fast Page Mode Cycle
CAS-before-RAS Refresh Cycle
Semiconductor Group
8
7
HYM 324020S/GS-50/-60
4M x 32-Bit
Notes:
1) All voltages are referenced to VSS.
2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate.
3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open.
4) Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less
during a fast page mode cycle (tPC).
5) An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a
minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume tT = 5 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also
measured between VIH and VIL.
8) Measured with a load equivalent to 2 TTL loads and 100 pF.
9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a
reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by
tCAC.
10)Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a
reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by
tAA.
11)Either tRCH or tRRH must be satisfied for a read cycle.
12)tOFF (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to
output voltage levels
.
13)tWCS is not a restrictive operating parameter. This is included in the data sheet as electrical characteristics
only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high
impedance) through the entire cycle.
14)These parameters are referenced to the CAS leading edge.
Semiconductor Group
9
HYM 324020S/GS-50/-60
4M x 32-Bit
Package Outline
107.95
101.19
R1.57
5.28 max
10.16
6.35
22.86
3.18
3.38
1.27
2.03
6.35
R 1.57 +/- 0.05
6.35 +/- 0.05
95.25
+/- 0.05
1.27
+0.10
-0.08
0.25 max
2.54 min
Detail of Contacts
1.27
1.04 +/- 0.05
Tolerances : +/- 0.13 unless otherwise specified
GLS05835
Module Package, L-SIM-72-12
(Single in-Line Memory Module)
Semiconductor Group
10