HEF4543B BCD to 7-segment latch/decoder/driver Rev. 05 — 27 October 2009 Product data sheet 1. General description The HEF4543B is a BCD to 7-segment latch/decoder/driver for liquid crystal and LED displays. It has four address inputs (D0 to D3), an active LOW latch enable input (LE), an active HIGH blanking input (BL), an active HIGH phase input (PH) and seven buffered segment outputs (Qa to Qg). The circuit provides the function of a 4-bit storage latch and an 8-4-2-1 BCD to 7-segment decoder/driver. It can invert the logic levels of the output combination. The phase (PH), blanking (BL) and latch enable (LE) inputs are used to reverse the function table phase, blank the display and store a BCD code, respectively. For liquid crystal displays, a square-wave is applied to PH and the electrical common back-plane of the display. The outputs of the device are directly connected to the segments of the liquid crystal. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is also suitable for use over the full industrial (−40 °C to +85 °C) temperature range. 2. Features n n n n n Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Operates across the full industrial temperature range −40 °C to +85 °C Complies with JEDEC standard JESD 13-B 3. Applications n Industrial 4. Ordering information Table 1. Ordering information All types operate from −40 °C to +85 °C Type number Package Name Description Version HEF4543BP DIP16 plastic dual in-line package; 16-leads (300 mil) SOT38-4 HEF4543BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 HEF4543B NXP Semiconductors BCD to 7-segment latch/decoder/driver 5. Functional diagram 5 3 2 4 D0 D1 D2 D3 1 LE LATCHES 7 BL DECODER 6 PH DRIVERS Qg Qf Qe Qd Qc Qb Qa 14 15 13 12 11 10 9 001aae742 Fig 1. Functional diagram HEF4543B_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 27 October 2009 2 of 16 HEF4543B NXP Semiconductors BCD to 7-segment latch/decoder/driver BL D0 Qa D1 Qb Qc D2 Qd Qe D3 Qf Qg LE PH Fig 2. 001aae744 Logic diagram HEF4543B_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 27 October 2009 3 of 16 HEF4543B NXP Semiconductors BCD to 7-segment latch/decoder/driver 6. Pinning information 6.1 Pinning HEF4543B LE 1 16 VDD D2 2 15 Qf D1 3 14 Qg D3 4 13 Qe D0 5 12 Qd PH 6 11 Qc BL 7 10 Qb VSS 8 9 Qa 001aae743 Fig 3. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin Description LE 1 latch enable input (active LOW) D0 to D3 5, 3, 2, 4 address (data) input PH 6 phase input (active HIGH) BL 7 blanking input (active HIGH) VSS 8 ground supply voltage Qa to Qg 9, 10, 11, 12, 13, 15, 14 segment output VDD 16 supply voltage HEF4543B_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 27 October 2009 4 of 16 HEF4543B NXP Semiconductors BCD to 7-segment latch/decoder/driver 7. Functional description Function table [1] Table 3. Inputs Outputs LE BL PH X H H H [2] D3 D2 D1 D0 Qa Qb Qc Qd Qe Qf Qg Display L X X X X L L L L L L L blank L L L L L L H H H H H H L 0 L L L L L H L H H L L L L 1 H L L L L H L H H L H H L H 2 H L L L L H H H H H H L L H 3 H L L L H L L L H H L L H H 4 H L L L H L H H L H H L H H 5 H L L L H H L H L H H H H H 6 H L L L H H H H H H L L L L 7 H L L H L L L H H H H H H H 8 H L L H L L H H H H H L H H 9 H L L H L H X L L L L L L L blank H L L H H X X L L L L L L L blank L L L X X X X n.c. n.c as above H as above inverse of above as above [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care,: n.c. = no change. [2] For liquid crystal displays, apply a square-wave to PH; For common cathode LED displays, select PH = LOW; For common anode LED displays, select PH = HIGH. a f g e d b c 001aaj494 Fig 4. Seven segment digital display with segment designation 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min VDD supply voltage −0.5 VI input voltage −0.5 Max +18 VDD + 0.5 Unit V V II/O input/output current - ±10 mA Tstg storage temperature −65 +150 °C Tamb ambient temperature −40 +85 °C HEF4543B_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 27 October 2009 5 of 16 HEF4543B NXP Semiconductors BCD to 7-segment latch/decoder/driver Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Ptot Parameter Conditions total power dissipation P power dissipation Min DIP16 package [1] SO16 package [2] per output [1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C. [2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C. Max Unit - 750 mW - 500 mW - 100 mW 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VDD supply voltage 3 - 15 V VI input voltage Tamb ambient temperature in free air 0 - VDD V −40 - +85 °C ∆t/∆V input transition rise and fall rate VDD = 5 V - - 3.75 µs/V VDD = 10 V - - 0.5 µs/V VDD = 15 V - - 0.08 µs/V 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter VIH VIL VOH VOL IOH HIGH-level input voltage LOW-level input voltage Conditions |IO| < 1 µA |IO| < 1 µA HIGH-level output voltage LOW-level output voltage HIGH-level output current |IO| < 1 µA VO = 2.5 V VDD Tamb = −40 °C Tamb = 85 °C Unit Min Max Min Max Min Max 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 V 5V 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - V 5V 5V - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 V 15 V - 0.05 - 0.05 - 0.05 V −1.7 - −1.4 - −1.1 - 5V mA VO = 4.6 V 5V −0.52 - −0.44 - −0.36 - mA VO = 9.5 V 10 V −1.3 - −1.1 - −0.9 - mA VO = 13.5 V 15 V −3.6 - −3.0 - −2.4 - mA HEF4543B_5 Product data sheet Tamb = 25 °C © NXP B.V. 2009. All rights reserved. Rev. 05 — 27 October 2009 6 of 16 HEF4543B NXP Semiconductors BCD to 7-segment latch/decoder/driver Table 6. Static characteristics …continued VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter IOL LOW-level output current II input leakage current IDD supply current CI Conditions Tamb = −40 °C VDD Tamb = 25 °C Tamb = 85 °C Min Max Min Max Min Max Unit VO = 0.4 V 5V 0.52 - 0.44 - 0.36 - mA VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA 15 V - ±0.3 - ±0.3 - ±1.0 µA 5V - 20 - 20 - 150 µA 10 V - 40 - 40 - 300 µA 15 V - 80 - 80 - 600 µA - - - 7.5 - - pF Max Unit IO = 0 A input capacitance - 11. Dynamic characteristics Table 7. Dynamic characteristics VSS = 0 V; Tamb = 25 °C; For test circuit see Figure 7;unless otherwise specified. Extrapolation formula[1] Min Typ 5V 153 ns + (0.55 ns/pF) CL - 180 360 ns 10 V 64 ns + (0.23 ns/pF) CL - 75 150 ns 15 V 47 ns + (0.16 ns/pF) CL - 55 110 ns 5V 143 ns + (0.55 ns/pF) CL - 170 340 ns 10 V 69 ns + (0.23 ns/pF) CL - 80 160 ns 15 V 52 ns + (0.16 ns/pF) CL - 60 120 ns 5V 118 ns + (0.55 ns/pF) CL - 145 290 ns 10 V 54 ns + (0.23 ns/pF) CL - 65 130 ns 15 V 37 ns + (0.16 ns/pF) CL - 45 90 ns 5V 153 ns + (0.55 ns/pF) CL - 180 360 ns 10 V 64 ns + (0.23 ns/pF) CL - 75 150 ns 15 V 47 ns + (0.16 ns/pF) CL - 55 110 ns Symbol Parameter Conditions VDD tPHL HIGH to LOW propagation delay Dn to Qn; see Figure 5 LE to Qn; see Figure 5 BL to Qn; see Figure 5 tPLH LOW to HIGH propagation delay Dn to Qn; see Figure 5 LE to Qn; see Figure 5 BL to Qn; see Figure 5 tt tsu transition time set-up time pin Qn; see Figure 5 Dn to LE; see Figure 6 5V 163 ns + (0.55 ns/pF) CL - 190 380 ns 10 V 69 ns + (0.23 ns/pF) CL - 80 160 ns 15 V 52 ns + (0.16 ns/pF) CL - 60 120 ns 5V 98 ns + (0.55 ns/pF) CL - 125 250 ns 10 V 54 ns + (0.23 ns/pF) CL - 55 110 ns 15 V 32 ns + (0.16 ns/pF) CL - 40 80 ns 5V 10 ns + (1.00 ns/pF) CL - 60 120 ns 10 V 9 ns + (0.42 ns/pF) CL - 30 60 ns 15 V 6 ns + (0.28 ns/pF) CL 40 ns - 20 5V 40 20 - ns 10 V 20 5 - ns 15 V 15 0 - ns HEF4543B_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 27 October 2009 7 of 16 HEF4543B NXP Semiconductors BCD to 7-segment latch/decoder/driver Table 7. Dynamic characteristics …continued VSS = 0 V; Tamb = 25 °C; For test circuit see Figure 7;unless otherwise specified. Symbol Parameter Conditions th hold time Dn to LE; see Figure 6 pulse width tW [1] VDD pin LE HIGH; minimum width; see Figure 6 Extrapolation formula[1] Min Typ Max Unit 5V 0 −15 - ns 10 V 15 0 - ns 15 V 20 5 - ns 5V 60 30 - ns 10 V 30 15 - ns 15 V 20 10 - ns The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). Table 8. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol Parameter PD dynamic power dissipation VDD Typical formula for PD (µW) where: 5V PD = 2200 × fi + Σ(fo × CL) × VDD2 10 V 15 V fi = input frequency in MHz, PD = 10400 × fi + Σ(fo × CL) × VDD 2 fo = output frequency in MHz, PD = 33000 × fi + Σ(fo × CL) × VDD 2 CL = output load capacitance in pF, VDD = supply voltage in V, Σ(CL × fo) = sum of the outputs. 12. Waveforms VI LE VM VM VSS VI VM D2 VSS VI LT VSS tPHL VI VM BL VSS tPLH tPHL VOH tPLH tPHL tPLH tPLH tPHL 90 % VM Qg 10 % VOL tTHL tTLH 001aaj496 Conditions: D3 = LOW and D0 = D1 =HIGH. Fig 5. Propagation delays and output transitions times HEF4543B_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 27 October 2009 8 of 16 HEF4543B NXP Semiconductors BCD to 7-segment latch/decoder/driver VI VM LE input VSS tW VI D2 input VM VSS tsu th VOH Qg output VOL 001aaj799 Conditions: D3 = BL = LOW; D0 = D1 = LE = HIGH Fig 6. Waveforms showing minimum LE pulse width, set-up, and hold time for DC to LE HEF4543B_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 27 October 2009 9 of 16 HEF4543B NXP Semiconductors BCD to 7-segment latch/decoder/driver tW VI 90 % negative pulse VM VM 10 % 0V tf tr tr tf VI 90 % positive pulse VM VM 10 % 0V tW 001aaj781 a. Input waveforms VDD VI VO G DUT RT CL 001aag182 b. Test circuit Test data is given in Table 9. Definitions for test circuit: RL = Load resistance; CL = Load capacitance including jig and probe capacitance; RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 7. Test circuit for switching times Table 9. Test data Supply voltage 5 V to 15 V Input Load VI VM tr, tf CL VDD 0.5VI ≤ 20 ns 50 pF 13. Application information Some examples of applications for the HEF4543B are: • • • • • Driving LCD displays Driving LED displays Driving fluorescent displays Driving incandescent displays Driving gas discharge displays HEF4543B_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 27 October 2009 10 of 16 HEF4543B NXP Semiconductors BCD to 7-segment latch/decoder/driver VDD common anode LED HEF4543B output common cathode LED HEF4543B PH output VSS PH a. common cathode 001aae746 VDD 001aae745 b. common anode Bipolar transistors may be added for gain where VDD ≤ 10 V or IO ≥ 10 mA. Fig 8. Connection to LED display readout appropriate voltage HEF4543B output PH one of seven segments common back-plane HEF4543B output PH square wave; VSS to VDD VSS 001aae748 001aae747 Fig 9. Connection to LCD readout Fig 10. Connection to incandescent display readout appropriate voltage HEF4543B output HEF4543B PH output VSS PH VSS or appropriate voltage below VSS VSS 001aae749 Fig 11. Connection to gas discharge display readout 001aae750 Fig 12. Connection to fluorescent display readout HEF4543B_5 Product data sheet to filament supply © NXP B.V. 2009. All rights reserved. Rev. 05 — 27 October 2009 11 of 16 HEF4543B NXP Semiconductors BCD to 7-segment latch/decoder/driver 14. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 13. Package outline SOT38-4 (DIP16) HEF4543B_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 27 October 2009 12 of 16 HEF4543B NXP Semiconductors BCD to 7-segment latch/decoder/driver SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 14. Package outline SOT109-1 (SO16) HEF4543B_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 27 October 2009 13 of 16 HEF4543B NXP Semiconductors BCD to 7-segment latch/decoder/driver 15. Abbreviations Table 10. Abbreviations Acronym Description DUT Device Under Test 16. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4543B_5 20091027 Product data sheet - HEF4543B_4 Modifications: • • • Section 2 “Features” ESD entry removed. Section 9 “Recommended operating conditions” ∆t/∆V values updated. Section 15 “Abbreviations” ESD entries removed. HEF4543B_4 20090317 Product data sheet - HEF4543B_CNV_3 HEF4543B_CNV_3 19950101 Product specification - HEF4543B_CNV_2 HEF4543B_CNV_2 19950101 Product specification - - HEF4543B_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 27 October 2009 14 of 16 HEF4543B NXP Semiconductors BCD to 7-segment latch/decoder/driver 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] HEF4543B_5 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 05 — 27 October 2009 15 of 16 HEF4543B NXP Semiconductors BCD to 7-segment latch/decoder/driver 19. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Application information. . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 27 October 2009 Document identifier: HEF4543B_5