PCA9530 2-bit I2C-bus LED dimmer Rev. 03 — 26 February 2009 Product data sheet 1. General description The PCA9530 is a 2-bit I2C-bus and SMBus I/O expander optimized for dimming LEDs in 256 discrete steps for Red/Green/Blue (RGB) color mixing and backlight applications. The PCA9530 contains an internal oscillator with two user programmable blink rates and duty cycles coupled to the output PWM. The LED brightness is controlled by setting the blink rate high enough (> 100 Hz) that the blinking cannot be seen and then using the duty cycle to vary the amount of time the LED is on and thus the average current through the LED. The initial setup sequence programs the two blink rates/duty cycles for each individual PWM. From then on, only one command from the bus master is required to turn individual LEDs ON, OFF, BLINK RATE 1 or BLINK RATE 2. Based on the programmed frequency and duty cycle, BLINK RATE 1 and BLINK RATE 2 will cause the LEDs to appear at a different brightness or blink at periods up to 1.69 second. The open-drain outputs directly drive the LEDs with maximum output sink current of 25 mA per bit and 50 mA per package. To blink LEDs at periods greater than 1.69 second, the bus master (MCU, MPU, DSP, chip set, etc.) must send repeated commands to turn the LED on and off as is currently done when using normal I/O Expanders like the NXP Semiconductors PCF8574 or PCA9554. Any bits not used for controlling the LEDs can be used for General Purpose parallel Input/Output (GPIO) expansion which provides a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, alarm monitoring, fans, etc. The active LOW hardware reset pin (RESET) and Power-On Reset (POR) initialize the registers to their default state causing the bits to be set HIGH (LED off). One hardware address pin on the PCA9530 allows two devices to operate on the same bus. 2. Features n 2 LED drivers (on, off, flashing at a programmable rate) n 2 selectable, fully programmable blink rates (frequency and duty cycle) between 0.591 Hz and 152 Hz (1.69 seconds and 6.58 milliseconds) n 256 brightness steps n Input/output not used as LED drivers can be used as regular GPIOs n Internal oscillator requires no external components n I2C-bus interface logic compatible with SMBus n Internal power-on reset PCA9530 NXP Semiconductors 2-bit I2C-bus LED dimmer n n n n n n n n n n Noise filter on SCL/SDA inputs Active LOW reset input (RESET) 2 open-drain outputs directly drive LEDs to 25 mA Edge rate control on outputs No glitch on power-up Supports hot insertion Low standby current Operating power supply voltage range of 2.3 V to 5.5 V 0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 n Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA n Packages offered: SO8, TSSOP8 (MSOP8) 3. Ordering information Table 1. Ordering information Tamb = −40 °C to +85 °C Type number Topside mark Package Name Description Version PCA9530D PCA9530 SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 PCA9530DP 9530 TSSOP8[1] plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1 [1] Also known as MSOP8. 4. Block diagram A0 PCA9530 SCL SDA INPUT REGISTER INPUT FILTERS I2C-BUS CONTROL LED SELECT (LSn) REGISTER 0 VDD 1 POWER-ON RESET RESET OSCILLATOR VSS PRESCALER 0 REGISTER PWM0 REGISTER BLINK0 PRESCALER 1 REGISTER PWM1 REGISTER BLINK1 LEDn 002aae498 Remark: Only one I/O shown for clarity. Fig 1. Block diagram PCA9530_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 26 February 2009 2 of 24 PCA9530 NXP Semiconductors 2-bit I2C-bus LED dimmer 5. Pinning information 5.1 Pinning A0 1 8 VDD LED0 2 7 SDA LED1 3 6 SCL VSS 4 5 RESET PCA9530D A0 1 8 VDD LED0 2 7 SDA 6 SCL 5 RESET LED1 3 VSS 4 002aae497 002aae496 Fig 2. PCA9530DP Pin configuration for SO8 Fig 3. Pin configuration for TSSOP8 (MSOP8) 5.2 Pin description Table 2. Pin description Symbol Pin Description A0 1 address input 0 LED0 2 LED driver 0 LED1 3 LED driver 1 VSS 4 supply ground RESET 5 active LOW reset input SCL 6 serial clock line SDA 7 serial data line VDD 8 supply voltage 6. Functional description Refer to Figure 1 “Block diagram”. 6.1 Device addressing Following a START condition, the bus master must output the address of the slave it is accessing. The address of the PCA9530 is shown in Figure 4. To conserve power, no internal pull-up resistor is incorporated on the hardware selectable address pin and it must be pulled HIGH or LOW. slave address 1 1 0 0 fixed 0 0 A0 R/W hardware selectable 002aae499 Fig 4. Slave address PCA9530_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 26 February 2009 3 of 24 PCA9530 NXP Semiconductors 2-bit I2C-bus LED dimmer The last bit of the address byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation. 6.2 Control register Following the successful acknowledgement of the slave address, the bus master will send a byte to the PCA9530, which will be stored in the Control register. 0 0 0 AI Auto-Increment flag 0 B2 B1 B0 register address 002aae500 Reset state: 00h Fig 5. Control register The lowest 3 bits are used as a pointer to determine which register will be accessed. If the Auto-Increment flag is set, the three low order bits of the Control register are automatically incremented after a read or write. This allows the user to program the registers sequentially. The contents of these bits will rollover to ‘000’ after the last register is accessed. When Auto-Increment flag is set (AI = 1) and a read sequence is initiated, the sequence must start by reading a register different from the Input register (B2 B1 B0 ≠ 0 0 0). Only the 3 least significant bits are affected by the AI flag. Unused bits must be programmed with zeroes. 6.2.1 Control register definition Table 3. Register summary B2 B1 B0 Symbol Access Description 0 0 0 INPUT read only input register 0 0 1 PSC0 read/write frequency prescaler 0 0 1 0 PWM0 read/write PWM register 0 0 1 1 PSC1 read/write frequency prescaler 1 1 0 0 PWM1 read/write PWM register 1 1 0 1 LS0 read/write LED selector PCA9530_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 26 February 2009 4 of 24 PCA9530 NXP Semiconductors 2-bit I2C-bus LED dimmer 6.3 Register descriptions 6.3.1 INPUT - Input register The INPUT register reflects the state of the device pins. Writes to this register will be acknowledged but will have no effect. Table 4. Bit INPUT - Input register description 7 6 5 4 3 2 1 0 Symbol - - - - - - LED1 LED0 Default 0 0 0 0 0 0 X X Remark: The default value ‘X’ is determined by the externally applied logic level (normally logic 1) when used for directly driving LED with pull-up to VDD. 6.3.2 PCS0 - Frequency Prescaler 0 PSC0 is used to program the period of the PWM output. The period of BLINK0 = (PSC0 + 1) / 152. Table 5. Bit PSC0 - Frequency Prescaler 0 register description 7 6 5 4 3 2 1 0 Symbol PSC0[7] PSC0[6] PSC0[5] PSC0[4] PSC0[3] PSC0[2] PSC0[1] PSC0[0] Default 0 0 0 0 0 0 0 0 6.3.3 PWM0 - Pulse Width Modulation 0 The PWM0 register determines the duty cycle of BLINK0. The outputs are LOW (LED on) when the count is less than the value in PWM0 and HIGH (LED off) when it is greater. If PWM0 is programmed with 00h, then the PWM0 output is always HIGH (LED off). The duty cycle of BLINK0 = PWM0 / 256. Table 6. Bit PWM0 - Pulse Width Modulation 0 register description 7 6 5 4 3 2 1 0 Symbol PWM0 [7] PWM0 [6] PWM0 [5] PWM0 [4] PWM0 [3] PWM0 [2] PWM0 [1] PWM0 [0] Default 1 0 0 0 0 0 0 0 6.3.4 PCS1 - Frequency Prescaler 1 PSC1 is used to program the period of the PWM output. The period of BLINK1 = (PSC1 + 1) / 152. Table 7. Bit PSC1 - Frequency Prescaler 1 register description 7 6 5 4 3 2 1 0 Symbol PSC1[7] PSC1[6] PSC1[5] PSC1[4] PSC1[3] PSC1[2] PSC1[1] PSC1[0] Default 0 0 0 0 0 0 0 0 PCA9530_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 26 February 2009 5 of 24 PCA9530 NXP Semiconductors 2-bit I2C-bus LED dimmer 6.3.5 PWM1 - Pulse Width Modulation 1 The PWM1 register determines the duty cycle of BLINK1. The outputs are LOW (LED on) when the count is less than the value in PWM1 and HIGH (LED off) when it is greater. If PWM1 is programmed with 00h, then the PWM1 output is always HIGH (LED off). The duty cycle of BLINK1 = PWM1 / 256. Table 8. Bit PWM1 - Pulse Width Modulation 1 register description 7 6 5 4 3 2 1 0 Symbol PWM1 [7] PWM1 [6] PWM1 [5] PWM1 [4] PWM1 [3] PWM1 [2] PWM1 [1] PWM1 [0] Default 1 0 0 0 0 0 0 0 6.3.6 LS0 - LED selector The LS0 LED select register determines the source of the LED data. 00 = output is set high-impedance (LED off; default) 01 = output is set LOW (LED on) 10 = output blinks at PWM0 rate 11 = output blinks at PWM1 rate Table 9. LS0 - LED selector register bit description Legend: * default value. Register Bit Value Description LS0 7:4 1111* reserved 3:2 00* LED1 selected 1:0 00* LED0 selected 6.4 Pins used as GPIOs LEDn pins not used to control LEDs can be used as General Purpose I/Os (GPIOs). For use as input, set LEDn to high-impedance (00) and then read the pin state via the INPUT register. For use as output, connect external pull-up resistor to the pin and size it according to the DC recommended operating characteristics. LEDn output pin is HIGH when the output is programmed as high-impedance, and LOW when the output is programmed LOW through the ‘LED selector’ register LS0. The output can be pulse-width controlled when PWM0 or PWM1 are used. 6.5 Power-on reset When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9530 in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9530 registers are initialized to their default states, all the outputs in the OFF state. Thereafter, VDD must be lowered below 0.2 V to reset the device. PCA9530_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 26 February 2009 6 of 24 PCA9530 NXP Semiconductors 2-bit I2C-bus LED dimmer 6.6 External RESET A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The PCA9530 registers and I2C-bus state machine will be held in their default states until the RESET input is once again HIGH. This input requires a pull-up resistor to VDD if no active connection is used. 7. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 7.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 6). SDA SCL data line stable; data valid Fig 6. change of data allowed mba607 Bit transfer 7.1.1 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 7). SDA SCL S P START condition STOP condition mba608 Fig 7. Definition of START and STOP conditions PCA9530_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 26 February 2009 7 of 24 PCA9530 NXP Semiconductors 2-bit I2C-bus LED dimmer 7.2 System configuration A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 8). SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C-BUS MULTIPLEXER SLAVE 002aaa966 Fig 8. System configuration 7.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master 1 S START condition Fig 9. 8 9 clock pulse for acknowledgement 002aaa987 Acknowledgement on the I2C-bus PCA9530_3 Product data sheet 2 © NXP B.V. 2009. All rights reserved. Rev. 03 — 26 February 2009 8 of 24 PCA9530 NXP Semiconductors 2-bit I2C-bus LED dimmer 7.4 Bus transactions SCL 1 2 3 4 5 6 7 8 9 slave address 1 SDA S 1 0 0 0 data to register command byte 0 A0 0 START condition A R/W 0 0 0 AI 0 B2 B1 B0 A DATA 1 A acknowledge from slave acknowledge from slave acknowledge from slave write to register tv(Q) data out from port DATA 1 VALID 002aae502 Fig 10. Write to register slave address SDA S 1 1 0 0 0 command byte 0 A0 0 START condition 0 A 0 1 1 0 AI 0 0 (repeated) START condition 0 A0 1 0 B2 B1 B0 A (cont.) acknowledge from slave R/W acknowledge from slave slave address (cont.) S 0 data from register DATA (first byte) A Auto-Increment register address if AI = 1 R/W acknowledge from slave data from register DATA (last byte) A acknowledge from master NA P STOP condition no acknowledge from master at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter 002aae503 Fig 11. Read from register no acknowledge from master slave address SDA S 1 1 0 0 0 START condition data from port data from port 0 A0 1 R/W A A DATA 1 DATA 4 acknowledge from master acknowledge from slave NA P STOP condition read from port th(D) data into port DATA 1 tsu(D) DATA 2 DATA 3 DATA 4 002aae504 Remark: This figure assumes the command byte has previously been programmed with 00h. Fig 12. Read Input port register PCA9530_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 26 February 2009 9 of 24 PCA9530 NXP Semiconductors 2-bit I2C-bus LED dimmer 8. Application design-in information 5V 3.3 V 10 kΩ 10 kΩ 10 kΩ VDD I2C-BUS/SMBus MASTER SDA SDA LED0 SCL SCL LED1 RESET PCA9530 A0 VSS 002aae501 Fig 13. Typical application 8.1 Minimizing IDD when the I/Os are used to control LEDs When the I/Os are used to control LEDs, they are normally connected to VDD through a resistor as shown in Figure 13. Since the LED acts as a diode, when the LED is off the I/O VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes lower than VDD and is specified as ∆IDD in Table 12 “Static characteristics”. Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to VDD when the LED is off. Figure 14 shows a high value resistor in parallel with the LED. Figure 15 shows VDD less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI at or above VDD and prevent additional supply current consumption when the LED is off. VDD VDD LED 100 kΩ LEDn VDD 5V LED LEDn 002aac189 Fig 14. High value resistor in parallel with the LED PCA9530_3 Product data sheet 3.3 V 002aac190 Fig 15. Device supplied by a lower voltage © NXP B.V. 2009. All rights reserved. Rev. 03 — 26 February 2009 10 of 24 PCA9530 NXP Semiconductors 2-bit I2C-bus LED dimmer 8.2 Programming example The following example will show how to set LED0 to blink at 1 Hz at a 50 % duty cycle. LED1 will be set to be dimmed at 25 % of their maximum brightness (duty cycle = 25 %). Table 10. Programming PCA9530 I2C-bus Program sequence START S PCA9530 address with A0 = LOW C0h PSC0 subaddress + Auto-Increment 11h Set prescaler PSC0 to achieve a period of 1 second: 97h PSC0 + 1 Blink period = 1 = -----------------------152 PSC0 = 151 Set PWM0 duty cycle to 50 %: 80h PWM0 ----------------- = 0.5 256 PWM0 = 128 Set prescaler PCS1 to dim at maximum frequency: 00h Blink period = max PSC1 = 0 Set PWM1 output duty cycle to 25 %: 40h PWM1 ----------------- = 0.25 256 PWM1 = 64 Set LED0 to PWM0, and set LED1 to blink at PWM1 0Eh STOP P 9. Limiting values Table 11. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD Conditions Min Max Unit supply voltage −0.5 +6.0 V VI/O voltage on an input/output pin VSS − 0.5 5.5 V IO(LEDn) output current on pin LEDn - +25 mA ISS ground supply current - 50 mA Ptot total power dissipation - 400 mW Tstg storage temperature −65 +150 °C Tamb ambient temperature −40 +85 °C operating PCA9530_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 26 February 2009 11 of 24 PCA9530 NXP Semiconductors 2-bit I2C-bus LED dimmer 10. Static characteristics Table 12. Static characteristics VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Supplies VDD supply voltage 2.3 - 5.5 V IDD supply current operating mode; VDD = 5.5 V; no load; VI = VDD or VSS; fSCL = 100 kHz - 350 500 µA Istb standby current Standby mode; VDD = 5.5 V; no load; VI = VDD or VSS; fSCL = 0 kHz - 1.9 5.0 µA ∆IDD additional quiescent supply current Standby mode; VDD = 5.5 V; every LED I/O at VI = 4.3 V; fSCL = 0 kHz [2] - - 200 µA VPOR power-on reset voltage no load; VI = VDD or VSS [3] - 1.7 2.2 V Input SCL; input/output SDA VIL LOW-level input voltage −0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 5.5 V IOL LOW-level output current VOL = 0.4 V 3 6.5 - mA IL leakage current VI = VDD = VSS −1 - +1 µA Ci input capacitance VI = VSS - 3.7 5 pF I/Os VIL LOW-level input voltage −0.5 - +0.8 V VIH HIGH-level input voltage 2.0 - 5.5 V IOL LOW-level output current VOL = 0.4 V VDD = 2.3 V [4] 9 - - mA VDD = 3.0 V [4] 12 - - mA VDD = 5.0 V [4] 15 - - mA VDD = 2.3 V [4] 15 - - mA VDD = 3.0 V [4] 20 - - mA VDD = 5.0 V [4] 25 - - mA −1 - +1 µA - 2.1 5 pF VOL = 0.7 V IL input leakage current Cio input/output capacitance VDD = 3.6 V; VI = 0 V or VDD Select inputs A0, RESET VIL LOW-level input voltage −0.5 - +0.8 V VIH HIGH-level input voltage 2.0 - 5.5 V ILI input leakage current −1 - +1 µA Ci input capacitance - 2.3 5 pF VI = VSS [1] Typical limits at VDD = 3.3 V, Tamb = 25 °C. [2] Additional current for one LED I/O at a time where VI = 4.3 V, [3] VDD must be lowered to 0.2 V in order to reset part. [4] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 50 mA. PCA9530_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 26 February 2009 12 of 24 PCA9530 NXP Semiconductors 2-bit I2C-bus LED dimmer 002aac524 20 % percent variation (1) percent variation 0% 002aac525 20 % 0% (1) (2) (2) (3) −20 % −20 % (3) −40 % −40 −20 0 20 40 60 100 Tamb (°C) 80 −40 % −40 −20 (1) maximum (1) maximum (2) average (2) average (3) minimum (3) minimum Fig 16. Typical frequency variation over process at VDD = 2.3 V to 3.0 V 20 40 60 100 80 Tamb (°C) Fig 17. Typical frequency variation over process at VDD = 3.0 V to 5.5 V PCA9530_3 Product data sheet 0 © NXP B.V. 2009. All rights reserved. Rev. 03 — 26 February 2009 13 of 24 PCA9530 NXP Semiconductors 2-bit I2C-bus LED dimmer 11. Dynamic characteristics Table 13. Dynamic characteristics Symbol Parameter Conditions Standard-mode I2C-bus Min Max Fast-mode I2C-bus Min Max Unit fSCL SCL clock frequency 0 100 0 400 tBUF bus free time between a STOP and START condition 4.7 - 1.3 - µs tHD;STA hold time (repeated) START condition 4.0 - 0.6 - µs tSU;STA set-up time for a repeated START condition 4.7 - 0.6 - µs tSU;STO set-up time for STOP condition 4.0 - 0.6 - µs tHD;DAT data hold time tVD;ACK data valid acknowledge time tVD;DAT data valid time kHz 0 - 0 - ns [1] - 600 - 600 ns LOW-level [2] - 600 - 600 ns HIGH-level [2] - 1500 - 600 ns tSU;DAT data set-up time 250 - 100 - ns tLOW LOW period of the SCL clock 4.7 - 1.3 - µs tHIGH HIGH period of the SCL clock 4.0 - 0.6 - µs 20 + 0.1Cb[3] 300 ns 20 + 0.1Cb[3] 300 ns rise time of both SDA and SCL signals tr - 1000 tf fall time of both SDA and SCL signals - 300 tSP pulse width of spikes that must be suppressed by the input filter - 50 - 50 ns tv(Q) data output valid time - 200 - 200 ns tsu(D) data input set-up time 100 - 100 - ns th(D) data input hold time 1 - 1 - µs tw(rst) reset pulse width 6 - 6 - ns trec(rst) reset recovery time 0 - 0 - ns trst reset time 400 - 400 - ns Port timing Reset [4][5] [1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. [2] tVD;DAT = minimum time for SDA data output to be valid following SCL LOW. [3] Cb = total capacitance of one bus line in pF. [4] Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions. [5] Upon reset, the full delay will be the sum of trst and the RC time constant of the SDA bus. PCA9530_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 26 February 2009 14 of 24 PCA9530 NXP Semiconductors 2-bit I2C-bus LED dimmer ACK or read cycle START SCL SDA 30 % trst RESET 50 % 50 % trec(rst) 50 % tw(rst) trst LEDn 50 % LED off 002aac193 Fig 18. Definition of RESET timing SDA tr tBUF tf tHD;STA tSP tLOW SCL tHD;STA P S tSU;STA tHD;DAT tHIGH tSU;DAT Sr tSU;STO P 002aaa986 Fig 19. Definition of timing PCA9530_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 26 February 2009 15 of 24 PCA9530 NXP Semiconductors 2-bit I2C-bus LED dimmer protocol START condition (S) tSU;STA bit 7 MSB (A7) tLOW bit 6 (A6) tHIGH bit 0 (R/W) acknowledge (A) STOP condition (P) 1/f SCL SCL tBUF tr tf SDA tHD;STA tSU;DAT tVD;ACK tVD;DAT tHD;DAT tSU;STO 002aab175 Rise and fall times refer to VIL and VIH. Fig 20. I2C-bus timing diagram 12. Test information VDD PULSE GENERATOR VI VO RL 500 Ω VDD open VSS DUT RT CL 50 pF 002aab880 RL = load resistor for LEDn. RL for SDA and SCL > 1 kΩ (3 mA or less current). CL = load capacitance includes jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generators. Fig 21. Test circuitry for switching times PCA9530_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 26 February 2009 16 of 24 PCA9530 NXP Semiconductors 2-bit I2C-bus LED dimmer 13. Package outline SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 inches 0.069 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.014 0.0075 0.20 0.19 0.16 0.15 0.05 0.01 0.01 0.004 0.028 0.012 0.244 0.039 0.028 0.041 0.228 0.016 0.024 θ 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 22. Package outline SOT96-1 (SO8) PCA9530_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 26 February 2009 17 of 24 PCA9530 NXP Semiconductors 2-bit I2C-bus LED dimmer TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm D E SOT505-1 A X c y HE v M A Z 5 8 A2 pin 1 index (A3) A1 A θ Lp L 1 4 detail X e w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.45 0.25 0.28 0.15 3.1 2.9 3.1 2.9 0.65 5.1 4.7 0.94 0.7 0.4 0.1 0.1 0.1 0.70 0.35 6° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-04-09 03-02-18 SOT505-1 Fig 23. Package outline SOT505-1 (TSSOP8) PCA9530_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 26 February 2009 18 of 24 PCA9530 NXP Semiconductors 2-bit I2C-bus LED dimmer 14. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 15.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 15.3 Wave soldering Key characteristics in wave soldering are: PCA9530_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 26 February 2009 19 of 24 PCA9530 NXP Semiconductors 2-bit I2C-bus LED dimmer • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 15.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 24) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 14 and 15 Table 14. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 15. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 24. PCA9530_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 26 February 2009 20 of 24 PCA9530 NXP Semiconductors 2-bit I2C-bus LED dimmer maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 24. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 16. Abbreviations Table 16. Abbreviations Acronym Description ACPI Advanced Configuration and Power Interface CDM Charged-Device Model DSP Digital Signal Processor DUT Device Under Test ESD ElectroStatic Discharge GPIO General Purpose Input/Output HBM Human Body Model I2C-bus Inter-Integrated Circuit bus I/O Input/Output LED Light Emitting Diode MCU MicroController Unit MM Machine Model MPU MicroProcessor Unit POR Power-On Reset PWM Pulse Width Modulator RC Resistor-Capacitor network RGB Red/Green/Blue SMBus System Management Bus PCA9530_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 26 February 2009 21 of 24 PCA9530 NXP Semiconductors 2-bit I2C-bus LED dimmer 17. Revision history Table 17. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9530_3 20090226 Product data sheet - PCA9530_2 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • • Legal texts have been adapted to the new company name where appropriate. Section 6.6 “External RESET”, 1st sentence: changed from “tW” to “tw(rst)” Figure 10 “Write to register”: symbol changed from “tpv” to “tv(Q)” Figure 11 “Read from register”: – symbol changed from “tph” to “th(D)” – symbol changed from “tps” to “tsu(D)” • Table 11 “Limiting values”: – parameter description for VI/O changed from “DC voltage on an I/O” to “voltage on an input/output pin” – symbol/parameter changed from “II/O, DC output current on an I/O” to “IO(LEDn), output current on pin LEDn” • Table 12 “Static characteristics”: – title of this table changed from “DC characteristics” to “Static characteristics” – descriptive line below table title: deleted “TYP at 3.3 V and 25 °C” (this is moved to new Table note [1], with its reference at column heading “Typ” – Istb Max value changed from “3.0 µA” to “5.0 µA” – parameter description for symbol ∆IDD changed from “additional standby current” to “additional quiescent standby current” – added (new) Table note [2], and its reference at ∆IDD • Table 13 “Dynamic characteristics”: – changed parameter description for fSCL from “operating frequency” to “SCL clock frequency” – (old) symbols “tVD;DAT (L)” and “tVD;DAT (H)” merged to “tVD;DAT” and added separate conditions for LOW-level and HIGH-level – symbol/parameter changed from “tPV, output data valid” to “tv(Q), data output valid time” – symbol/parameter changed from “tPS, input data setup time” to “tsu(D), data input set-up time” – symbol/parameter changed from “tW, Reset pulse width” to “tw(rst), reset pulse width” – symbol/parameter changed from “tREC, Reset recovery time” to “trec(rst), reset recovery time” – symbol/parameter changed from “tRESET, Time to reset” to “trst, reset time” • • added soldering information added Table 16 “Abbreviations” PCA9530_2 (9397 750 14093) 20041001 Product data sheet - PCA9530_1 PCA9530_1 (9397 750 13631) 20040914 Product data sheet - - PCA9530_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 26 February 2009 22 of 24 PCA9530 NXP Semiconductors 2-bit I2C-bus LED dimmer 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 18.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PCA9530_3 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 03 — 26 February 2009 23 of 24 PCA9530 NXP Semiconductors 2-bit I2C-bus LED dimmer 20. Contents 1 2 3 4 5 5.1 5.2 6 6.1 6.2 6.2.1 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.4 6.5 6.6 7 7.1 7.1.1 7.2 7.3 7.4 8 8.1 8.2 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Device addressing . . . . . . . . . . . . . . . . . . . . . . 3 Control register . . . . . . . . . . . . . . . . . . . . . . . . . 4 Control register definition . . . . . . . . . . . . . . . . . 4 Register descriptions . . . . . . . . . . . . . . . . . . . . 5 INPUT - Input register. . . . . . . . . . . . . . . . . . . . 5 PCS0 - Frequency Prescaler 0 . . . . . . . . . . . . . 5 PWM0 - Pulse Width Modulation 0 . . . . . . . . . . 5 PCS1 - Frequency Prescaler 1 . . . . . . . . . . . . . 5 PWM1 - Pulse Width Modulation 1 . . . . . . . . . . 6 LS0 - LED selector . . . . . . . . . . . . . . . . . . . . . . 6 Pins used as GPIOs . . . . . . . . . . . . . . . . . . . . . 6 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 6 External RESET . . . . . . . . . . . . . . . . . . . . . . . . 7 Characteristics of the I2C-bus. . . . . . . . . . . . . . 7 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 START and STOP conditions . . . . . . . . . . . . . . 7 System configuration . . . . . . . . . . . . . . . . . . . . 8 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . . 9 Application design-in information . . . . . . . . . 10 Minimizing IDD when the I/Os are used to control LEDs . . . . . . . . . . . . . . . . . . . . . . . . 10 Programming example . . . . . . . . . . . . . . . . . . 11 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11 Static characteristics. . . . . . . . . . . . . . . . . . . . 12 Dynamic characteristics . . . . . . . . . . . . . . . . . 14 Test information . . . . . . . . . . . . . . . . . . . . . . . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 Handling information. . . . . . . . . . . . . . . . . . . . 19 Soldering of SMD packages . . . . . . . . . . . . . . 19 Introduction to soldering . . . . . . . . . . . . . . . . . 19 Wave and reflow soldering . . . . . . . . . . . . . . . 19 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 19 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 20 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22 18 18.1 18.2 18.3 18.4 19 20 Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 23 23 23 23 23 24 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 26 February 2009 Document identifier: PCA9530_3