PCF2129A Integrated RTC, TCXO and quartz crystal Rev. 02 — 7 May 2010 Product data sheet 1. General description The PCF2129A is a CMOS1 Real Time Clock (RTC) and calendar with an integrated Temperature Compensated Crystal (Xtal) Oscillator (TCXO) and a 32.768 kHz quartz crystal optimized for very high accuracy and very low power consumption. The PCF2129A has a selectable I2C-bus or SPI-bus, a backup battery switch-over circuit, a programmable watchdog function, a timestamp function, and many other features. 2. Features and benefits 1. Temperature Compensated Crystal Oscillator (TCXO) with integrated capacitors Typical accuracy: ±3 ppm from −15 °C to +60 °C Integration of a 32.768 kHz quartz crystal and oscillator in the same package Provides year, month, day, weekday, hours, minutes, and seconds Timestamp function with interrupt capability detection of two different events on one multilevel input pin (e.g. for tamper detection) Two line bidirectional 400 kHz Fast-mode I2C-bus interface (IOL = 3 mA at pin SDA/CE) 3 line SPI-bus with separate data input and output (maximum speed 6.5 Mbit/s) Battery backup input pin and switch-over circuitry Battery backed output voltage pin Battery low detection function Extra power fail detection function with input and output pins Power-On Reset Override (PORO) Oscillator stop detection function Interrupt output (open-drain) Programmable 1 second or 1 minute interrupt Programmable watchdog timer with interrupt and reset capability Programmable alarm function with interrupt capability Programmable square wave open-drain output pin Clock operating voltage: 1.2 V to 4.2 V Low supply current: typical 0.65 μA at VDD = 3.0 V and Tamb = 25 °C Automatic leap year correction The definition of the abbreviations and acronyms used in this data sheet can be found in Section 17. PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 3. Applications Electronic metering for electricity, water, and gas Timekeeping instruments with high precision GPS equipment to reduce time to first fix Applications that require an accurate process timing Products with long automated unattended operation time 4. Ordering information Table 1. Ordering information Type number Package Name PCF2129AT/1 SO20 Description Version plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 5. Marking Table 2. PCF2129A_2 Product data sheet Marking codes Type number Marking code PCF2129AT/1 PCF2129AT All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 2 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 6. Block diagram INT TCXO OSCI DIVIDER AND TIMER 32.768 kHz OSCO CLKOUT BBS VDD VBAT VSS BATTERY BACK UP SWITCH-OVER CIRCUITRY OSCILLATOR MONITOR internal power supply TEMP 1 Hz LOGIC CONTROL RESET ADDRESS REGISTER SPI-BUS INTERFACE SDA/CE SDO SDI SERIAL BUS INTERFACE SELECTOR SCL IFS I2C-BUS INTERFACE PCF2129A RPU TS TEMP TEMPERATURE SENSOR Control_1 00h Control_2 01h Control_3 02h Seconds 03h Minutes 04h Hours 05h Days 06h Weekdays 07h Months 08h Years 09h Second_alarm 0Ah Minute_alarm 0Bh Hour_alarm 0Ch Day_alarm 0Dh Weekday_alarm 0Eh CLKOUT_ctl 0Fh Watchdg_tim_ctl 10h Watchdg_tim_val 11h Timestp_ctl 12h Sec_timestp 13h Min_timestp 14h Hour_timestp 15h Day_timestp 16h Mon_timestp 17h Year_timestp 18h Aging_offset 19h Internal_reg 1Ah Internal_reg 1Bh 001aaj703 Fig 1. Block diagram of PCF2129A PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 3 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 7. Pinning information 7.1 Pinning SCL 1 20 VDD SDI 2 19 VBAT SDO 3 18 BBS SDA/CE 4 17 INT IFS 5 TS 6 CLKOUT 7 14 n.c. VSS 8 13 n.c. n.c. 9 12 n.c. n.c. 10 11 n.c. PCF2129A 16 n.c. 15 n.c. 001aaj704 Top view. For mechanical details, see Figure 44. Fig 2. Pin configuration for PCF2129A (SO20) 7.2 Pin description Table 3. Pin description of PCF2129A Symbol Pin Description SCL 1 combined serial clock input for both I2C-bus and SPI-bus; may float when SDA/CE inactive SDI 2 serial data input for SPI-bus; may float when SDA/CE inactive SDO 3 serial data output for SPI-bus, push-pull SDA/CE 4 combined serial data input and output for the I2C-bus and chip enable input (active LOW) for the SPI-bus IFS 5 interface selector input connect to pin VSS to select the SPI-bus connect to pin BBS to select the I2C-bus PCF2129A_2 Product data sheet TS 6 timestamp input (active LOW) with 200 kΩ internal pull-up resistor (RPU) CLKOUT 7 clock output (open-drain) VSS 8 ground supply voltage n.c. 9 to 16 not connected; do not connect; do not use as feed through INT 17 interrupt output (open-drain; active LOW) BBS 18 output voltage (battery backed) VBAT 19 battery supply voltage (backup) VDD 20 supply voltage All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 4 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8. Functional description The PCF2129A is a Real Time Clock (RTC) and calendar with an on-chip Temperature Compensated Crystal (Xtal) Oscillator (TCXO) and a 32.768 kHz quartz crystal integrated into the same package. Address and data are transferred by a selectable 400 kHz Fast-mode I2C-bus or a 3 line SPI-bus with separate data input and output (see Section 9). The maximum speed of the SPI-bus is 6.5 Mbit/s. The PCF2129A contains 28 8-bit registers that are used for many different functions, such as clock, alarm, watchdog, timestamp etc. (see Section 8.1). The PCF2129A has a backup battery input pin and backup battery switch-over circuit which monitors the main power supply and automatically switches to the backup battery when a power failure condition is detected (see Section 8.5.1). Accurate timekeeping is maintained even when the main power supply is interrupted. A battery low detection circuit monitors the status of the battery (see Section 8.5.3). When the battery voltage goes below a certain threshold value, a flag is set to indicate that the battery must be replaced soon. This ensures the integrity of the data during periods of battery backup. PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 5 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.1 Register overview The PCF2129A contains 28 8-bit registers (see Table 4) with an auto-incrementing address register: the built-in address register will increment automatically after each read or write of a data byte up to the register 1Bh. After register 1Bh the auto-incrementing will wrap around to address 00h (see Figure 3). address register 00h 01h 02h auto-increment 03h ... 19h 1Ah 1Bh Fig 3. wrap around 001aaj398 Handling address registers • The first three registers (memory address 00h, 01h, and 02h) are used as control registers (see Section 8.2). • The memory addresses 03h through to 09h are used as counters for the clock function (seconds up to years). The date is automatically adjusted for months with fewer than 31 days, including corrections for leap years. The clock can operate in 12-hour mode with an AM/PM indication or in 24-hour mode (see Section 8.8). • Addresses 0Ah through 0Eh define the alarm function. It can be selected that an interrupt is generated when an alarm event occurs (see Section 8.9). • The register 0Fh defines the temperature measurement period and the clock out mode. The temperature measurement can be selected from every 4 minutes (default) down to every 30 seconds (see Table 9). CLKOUT frequencies of 32.768 kHz (default) down to 1 Hz for use as a system clock, a microcontroller clock etc. can be chosen (see Table 10). • Address registers 10h and 11h are used for the watchdog timer functions. The watchdog timer has four selectable source clocks allowing for timer periods from less than 1 ms to greater than 4 hours (see Table 32). An interrupt will be generated when the watchdog times out. • Address registers 12h to 18h are used for the timestamp function. When the trigger event happens, the actual time is saved in the timestamp registers (see Section 8.11). • Address register 19h is used for the correction of the crystal aging effect (see Section 8.4.1). • Address registers 1Ah and 1Bh are for internal use only. • The registers Seconds, Minutes, Hours, Days, Months, and Years are all coded in Binary Coded Decimal (BCD) format to simplify application use. Other registers are either bit-wise or standard binary. When one of the RTC registers is written or read, the content of all counters is temporarily frozen. This prevents a faulty writing or reading of the clock and calendar during a carry condition (see Section 8.8.8). PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 6 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal Table 4. Register overview Bit positions labeled as - are not implemented and will return 0 when read. Bits labeled as T must always be written with logic 0. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Address Register name Bit Reset value 7 6 5 4 3 2 1 0 Control registers 00h Control_1 EXT_ TEST T STOP TSF1 POR_ OVRD 12_24 MI SI 0000 0000 01h Control_2 MSF WDTF TSF2 AF T TSIE AIE T 0000 0000 02h Control_3 PWRMNG[2:0] BTSE BF BLF BIE BLIE 0000 0000 Time and date registers 03h Seconds OSF SECONDS (0 to 59) 1XXX XXXX 04h Minutes - MINUTES (0 to 59) - XXX XXXX 05h Hours - - AMPM HOURS (1 to 12) in 12 h mode - - XX XXXX HOURS (0 to 23) in 24 h mode - - XX XXXX - - XX XXXX 06h Days - - DAYS (1 to 31) 07h Weekdays - - - - - - MONTHS (1 to 12) - WEEKDAYS (0 to 6) - - - - - XXX 08h Months - 09h Years YEARS (0 to 99) XXXX XXXX - - - X XXXX Alarm registers 0Ah Second_alarm AE_S SECOND_ALARM (0 to 59) 1XXX XXXX 0Bh Minute_alarm AE_M MINUTE_ALARM (0 to 59) 1XXX XXXX 0Ch Hour_alarm AE_H - 1 - XX XXXX AMPM HOUR_ALARM (1 to 12) in 12 h mode HOUR_ALARM (0 to 23) in 24 h mode 1 - XX XXXX 1 - XX XXXX 0Dh Day_alarm AE_D - DAY_ALARM (1 to 31) 0Eh Weekday_alarm AE_W - - - - WEEKDAY_ALARM (0 to 6) 1 - - - - XXX TCR[1:0] - - - COF[2:0] WD_CD T TI_TP - - - CLKOUT control register 0Fh CLKOUT_ctl 00 - - - 000 Watchdog registers 10h Watchdg_tim_ctl 11h Watchdg_tim_val WATCHDG_TIM_VAL[7:0] TF[1:0] 000 - - - 11 XXXX XXXX Timestamp registers 12h Timestp_ctl TSM TSOFF - 1_O_16_TIMESTP[4:0] 13h Sec_timestp - SECOND_TIMESTP (0 to 59) - XXX XXXX 14h Min_timestp - MINUTE_TIMESTP (0 to 59) - XXX XXXX 15h Hour_timestp - - - - XX XXXX AMPM HOUR_TIMESTP (1 to 12) in 12 h mode HOUR_TIMESTP (0 to 23) in 24 h mode 00 - X XXXX - - XX XXXX 16h Day_timestp - - DAY_TIMESTP (1 to 31) - - XX XXXX 17h Mon_timestp - - - - - - X XXXX 18h Year_timestp YEAR_TIMESTP (0 to 99) MONTH_TIMESTP (1 to 12) XXXX XXXX Aging offset register 19h Aging_offset PCF2129A_2 Product data sheet - - - - AO[3:0] All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 - - - - 1000 © NXP B.V. 2010. All rights reserved. 7 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal Table 4. Register overview …continued Bit positions labeled as - are not implemented and will return 0 when read. Bits labeled as T must always be written with logic 0. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Address Register name Bit Reset value 7 6 5 4 3 2 1 0 Internal registers 1Ah Internal_reg - - - - - - - - ---- ---- 1Bh Internal_reg - - - - - - - - ---- ---- PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 8 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.2 Control registers PCF2129A has 28 8-bit registers. The first 3 registers with the addresses 00h, 01h, and 02h are used as control registers. 8.2.1 Register Control_1 Table 5. Bit 7 Control_1 - control and status register 1 (address 00h) bit description Symbol Value EXT_TEST 0 [1] 1 6 5 T STOP Description Reference normal mode Section 8.13 external clock test mode 0 [2] unused - 0 [1] RTC source clock runs Section 8.14 1 RTC clock is stopped; RTC divider chain flip-flops are asynchronously set logic 0; CLKOUT at 32.768 kHz, 16.384 kHz, or 8.192 kHz is still available 4 TSF1 0 [1] 1 no timestamp interrupt generated Section 8.11.1 flag set when TS input is driven to an intermediate level between power supply and ground; flag must be cleared to clear interrupt 3 POR_OVRD 0 [1] Power-On Reset Override (PORO) facility disabled; Section 8.7.2 set logic 0 for normal operation 1 2 12_24 0 PORO enabled [1] 1 1 MI 0 SI 0 1 PCF2129A_2 Product data sheet Table 18 12 hour mode selected [1] 1 0 24 hour mode selected minute interrupt disabled Section 8.12.1 minute interrupt enabled [1] second interrupt disabled second interrupt enabled [1] Default value. [2] When writing to the register this bit has always to be set logic 0. All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 9 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.2.2 Register Control_2 Table 6. Bit 7 Control_2 - control and status register 2 (address 01h) bit description Symbol MSF Value 0 [1] 1 Description Reference no minute or second interrupt generated Section 8.12 flag set when minute or second interrupt generated; flag must be cleared to clear interrupt 6 WDTF 0 [1] 1 no watchdog timer interrupt or reset generated Section 8.12.3 flag set when watchdog timer interrupt or reset generated; flag cannot be cleared by using the interface (read-only) 5 TSF2 0 [1] 1 no timestamp interrupt generated Section 8.11.1 flag set when TS input is driven to ground; flag must be cleared to clear interrupt 4 AF 0 [1] 1 no alarm interrupt generated Section 8.9.6 flag set when alarm triggered; flag must be cleared to clear interrupt 3 2 T TSIE 0 [2] 0 [1] 1 1 AIE 0 PCF2129A_2 Product data sheet T 0 - no interrupt generated from timestamp flag Section 8.12.5 interrupt generated when timestamp flag set [1] 1 0 unused no interrupt generated from the alarm flag Section 8.12.4 interrupt generated when alarm flag set [2] unused [1] Default value. [2] When writing to the register this bit has always to be set logic 0. All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 - © NXP B.V. 2010. All rights reserved. 10 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.2.3 Register Control_3 Table 7. Bit Control_3 - control and status register 3 (address 02h) bit description Symbol Value Description Reference 7 to 5 PWRMNG[2:0] [1] control of the battery switch-over, battery low detection, and extra power fail detection functions Section 8.5 4 0 no timestamp when battery switch-over occurs Section 8.11.4 BTSE [2] 1 3 BF 0 time-stamped when battery switch-over occurs [2] 1 no battery switch-over interrupt generated Section 8.5.1 flag set when battery switch-over occurs; flag must be cleared to clear interrupt 2 BLF 0 [2] battery status ok; Section 8.5.3 no battery low interrupt generated 1 battery status low; flag cannot be cleared using the interface 1 BIE 0 [2] 1 0 BLIE 0 1 PCF2129A_2 Product data sheet [1] Values see Table 13. [2] Default value. no interrupt generated from the battery flag (BF) Section 8.12.6 interrupt generated when BF is set [2] no interrupt generated from battery low flag (BLF) Section 8.12.7 interrupt generated when BLF is set All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 11 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.3 Register CLKOUT_ctl Table 8. Bit CLKOUT_ctl - CLKOUT control register (address 0Fh) bit description Symbol Value Description 7 to 6 TCR[1:0] see Table 9 temperature measurement period 5 to 3 - - unused 2 to 0 COF[2:0] see Table 10 CLKOUT frequency selection 8.3.1 Temperature compensated crystal oscillator The frequency of tuning fork quartz crystal oscillators is temperature-dependent. In the PCF2129A the frequency drift caused by temperature variation is corrected by adjusting the load capacitance of the crystal oscillator. The load capacitance is changed by switching between two load capacitance values using a modulation signal with a programmable duty cycle. Every chip is calibrated in order to produce, at the measured temperature, the correct duty cycle which compensates for the frequency drift. The frequency accuracy can be evaluated by measuring the frequency of the square wave signal available at the output pin CLKOUT. However, the selection of fCLKOUT = 32.768 kHz (default value) leads to inaccurate measurements. The most accurate frequency measurement occurs when fCLKOUT = 1 Hz is selected (see Table 10). 8.3.1.1 Temperature measurement The PCF2129A has a temperature sensor circuit used to perform the temperature compensation of the frequency. The temperature is measured immediately after power-on and then periodically with a period set by the temperature conversion rate TCR[1:0] in the register CLKOUT_ctl. Table 9. Temperature measurement period TCR[1:0] Temperature measurement period [1] 00 01 4 min 2 min 10 1 min 11 30 seconds [1] Default value. 8.3.2 Clock output A programmable square wave is available at pin CLKOUT. Operation is controlled by the COF[2:0] control bits in register CLKOUT_ctl. Frequencies of 32.768 kHz (default) down to 1 Hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. CLKOUT is an open-drain output and enabled at power-on. When disabled, the output is high-impedance. The duty cycle of the selected clock is not controlled, however, due to the nature of the clock generation all but the 32.768 kHz frequencies will be 50 : 50. PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 12 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal Table 10. PCF2129A_2 Product data sheet CLKOUT frequency selection COF[2:0] CLKOUT frequency (Hz) Typical duty cycle[1] 000[2] 32768 60 : 40 to 40 : 60 001 16384 50 : 50 010 8192 50 : 50 011 4096 50 : 50 100 2048 50 : 50 101 1024 50 : 50 110 1 50 : 50 111 CLKOUT = high-Z - [1] Duty cycle definition: % HIGH-level time : % LOW-level time. [2] Default value. All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 13 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.4 Register Aging_offset Table 11. Bit Aging_offset - crystal aging offset register (address 19h) bit description Symbol Value Description 7 to 4 - - unused 3 to 0 AO[3:0] see Table 12 aging offset value 8.4.1 Crystal aging correction The PCF2129A has an aging offset register Aging_offset to correct the crystal aging effects2. The accuracy of the frequency of a quartz crystal depends on the aging. Crystal suppliers usually specify the first year aging (typically ±1 ppm, maximum ±3 ppm) and/or the 10 years aging (typically ±5 ppm). The aging offset adds an adjustment, positive or negative, in the temperature compensation circuit which allows correcting the aging effect. The change in ppm per AO[3:0] value is different at different temperatures. At 25 °C, the aging offset bits allow a frequency correction of typically 1 ppm per AO[3:0] value, from −7 ppm to +8 ppm. Table 12. Frequency correction at 25 °C, typical AO[3:0] Decimal Binary 0 0000 +8 1 0001 +7 2 0010 +6 3 0011 +5 4 0100 +4 5 0101 +3 6 0110 +2 7 0111 +1 [1] 0 8 1000 9 1001 −1 10 1010 −2 11 1011 −3 12 1100 −4 13 1101 −5 14 1110 −6 15 1111 −7 [1] 2. ppm Default value. For further information please refer to the application note Ref. 3 “AN10857”. PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 14 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.5 Power management functions The PCF2129A has two power supply pins and one power output pin: • VDD - the main power supply input pin • VBAT - the battery backup input pin • BBS - battery backed output voltage pin (equal to the internal power supply) The PCF2129A has two power management functions implemented: • Battery switch-over function • Battery low detection function The power management functions are controlled by the control bits PWRMNG[2:0] in register Control_3: Table 13. Power management control bit description PWRMNG[2:0] Function [1] 000 battery switch-over function is enabled in standard mode; battery low detection function is enabled 001 battery switch-over function is enabled in standard mode; battery low detection function is disabled 010 battery switch-over function is enabled in standard mode; battery low detection function is disabled 011 battery switch-over function is enabled in direct switching mode; battery low detection function is enabled 100 battery switch-over function is enabled in direct switching mode; battery low detection function is disabled 101 battery switch-over function is enabled in direct switching mode; battery low detection function is disabled [2] 111 battery switch-over function is disabled, only one power supply (VDD); battery low detection function is disabled [1] Default value. [2] When the battery switch-over function is disabled, the PCF2129A works only with the power supply VDD; VBAT must be put to ground and the battery low detection function is disabled. 8.5.1 Battery switch-over function The PCF2129A has a backup battery switch-over circuit which monitors the main power supply VDD and automatically switches to the backup battery when a power failure condition is detected. One of two operation modes can be selected: • Standard mode: the power failure condition happens when: VDD < VBAT AND VDD < Vth(sw)bat • Direct switching mode: the power failure condition happens when VDD < VBAT. Direct switching from VDD to VBAT without requiring VDD to drop below Vth(sw)bat Vth(sw)bat is the battery switch threshold voltage. Typical value is 2.5 V. PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 15 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal When a power failure condition occurs and the power supply switches to the battery the following sequence occurs: 1. The battery switch flag BF (register Control_3) is set logic 1. 2. An interrupt is generated if the control bit BIE (register Control_3) is enabled (see Section 8.12.6). 3. If the control bit BTSE (register Control_3) is logic 1, the timestamp registers store the time and date when the battery switch occurred (see Section 8.11.4). 4. The battery switch flag BF is cleared via the interface; it must be cleared to clear the interrupt. The interface is disabled in battery backup operation: • Interface inputs are not recognized, preventing extraneous data being written to the device • Interface outputs are high-impedance 8.5.1.1 Standard mode If VDD > VBAT OR VDD > Vth(sw)bat the internal power supply is VDD. If VDD < VBAT AND VDD < Vth(sw)bat the internal power supply is VBAT. backup battery operation VDD VBBS VBBS VBAT internal power supply (= VBBS) Vth(sw)bat (= 2.5 V) VDD (= 0 V) BF INT cleared via interface 001aaj311 Fig 4. 8.5.1.2 Battery switch-over behavior in standard mode with bit BIE set logic 1 (enabled) Direct switching mode If VDD > VBAT the internal power supply is VDD. If VDD < VBAT the internal power supply is VBAT. PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 16 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal The direct switching mode is useful in systems where VDD is higher than VBAT at all times. The direct switching mode is not recommended if the VDD and VBAT values are similar (e.g. VDD = 3.3 V, VBAT ≥ 3.0 V). In direct switching mode the power consumption is reduced compared to the standard mode because the monitoring of VDD and Vth(sw)bat is not performed. backup battery operation VDD VBBS VBBS VBAT internal power supply (= VBBS) Vth(sw)bat (= 2.5 V) VDD (= 0 V) BF INT cleared via interface 001aaj312 Fig 5. 8.5.1.3 Battery switch-over behavior in direct switching mode with bit BIE set logic 1 (enabled) Battery switch-over disabled: only one power supply (VDD) When the battery switch-over function is disabled: • • • • 8.5.1.4 The power supply is applied on the VDD pin The VBAT pin must be connected to ground The internal power supply, available at the output pin BBS, is equal to VDD The battery flag (BF) is always logic 0 Battery switch-over architecture The architecture of the battery switch-over circuit is shown in Figure 6. PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 17 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal comparators logic switches VDD(int) VCC VDD Vth(sw)bat VDD VDD(int) VCC VBBS (internal power supply) LOGIC Vth(sw)bat VBAT VBAT 001aag061 VDD(int) Fig 6. Battery switch-over circuit, simplified block diagram The internal power supply (available on pin BBS) is equal to VDD or VBAT. It has to be assured that there are decoupling capacitors on the pins VDD, VBAT, and BBS. 8.5.2 Battery backup supply The VBBS voltage on the output pin BBS is equal to the internal power supply, depending on the selected battery switch-over function mode: Table 14. Output pin BBS Battery switch-over function mode Conditions VBBS equals standard VDD > VBAT OR VDD > Vth(sw)bat VDD VDD < VBAT AND VDD < Vth(sw)bat VBAT VDD > VBAT VDD VDD < VBAT VBAT only VDD available, VBAT must be put to ground VDD direct switching disabled 001aaj327 0 VBBS − VDD (mV) −200 VDD = 4.2 V −400 VDD = 3 V VDD = 2 V −600 −800 0 2 4 6 8 IBBS (mA) Fig 7. PCF2129A_2 Product data sheet Typical driving capability of VBBS: (VBBS − VDD) with respect to the output load current IBBS All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 18 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal The output pin BBS can be used as a supply for external devices with battery backup needs, such as SRAM (see Ref. 3 “AN10857”). For this case, Figure 7 shows the typical driving capability when VBBS is driven from VDD. 8.5.3 Battery low detection function The PCF2129A has a battery low detection circuit which monitors the status of the battery VBAT. When VBAT drops below the threshold value Vth(bat)low (typically 2.5 V) the BLF flag (register Control_3) is set to indicate that the battery is low and that it must be replaced. Monitoring of the battery voltage also occurs during battery operation. An unreliable battery cannot prevent that the supply voltage drops below Vlow (typical 1.2 V) and therewith the data integrity gets lost. When VBAT drops below the threshold value Vth(bat)low, the following sequence occurs (see Figure 8): 1. The battery low flag BLF is set logic 1. 2. An interrupt is generated if the control bit BLIE (register Control_3) is enabled (see Section 8.12.7). 3. The flag BLF remains logic 1 until the battery is replaced. BLF cannot be cleared using the interface. It is cleared automatically by the battery low detection circuit when the battery is replaced. VDD = VBBS internal power supply (= VBBS) VBAT Vth(bat)low (= 2.5 V) VBAT BLF INT 001aaj322 Fig 8. PCF2129A_2 Product data sheet Battery low detection behavior with bit BLIE set logic 1 (enabled) All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 19 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.6 Oscillator stop detection function The PCF2129A has an on-chip oscillator detection circuit which monitors the status of the oscillation: whenever the oscillation stops, a reset occurs and the oscillator stop flag OSF (in register Seconds) is set logic 1. • Power-on: a. The oscillator is not running, the chip is in reset (OSF is logic 1). b. When the oscillator starts running and is stable after power-on, the chip exits from reset. c. The flag OSF is still logic 1 and can be cleared (OSF set logic 0) via the interface. • Power supply failure: a. When the power supply of the chip (VDD or VBAT) drops below a certain value (Vlow), typically 1.2 V, the oscillator stops running and a reset occurs. b. When the power supply returns to normal operation, the oscillator starts running again, the chip exits from reset. c. The flag OSF is still logic 1 and can be cleared (OSF set logic 0) via the interface. VDD VDD VBBS VBAT VBBS VBBS Vth(sw)bat (= 2.5 V) VBBS battery discharge internal power supply Vlow (= 1.2 V) VBAT VSS VSS (1) (2) OSF 001aaj409 (1) Theoretical state of the signals since there is no power. (2) The oscillator stop flag (OSF), set logic 1, indicates that the oscillation has stopped and a reset has occurred since the flag was last cleared (OSF set logic 0). In this case the integrity of the clock information is not guaranteed. The OSF flag is cleared using the interface. Fig 9. PCF2129A_2 Product data sheet Power failure event due to battery discharge: reset occurs All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 20 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.7 Reset function The PCF2129A has a Power-On Reset (POR) and a Power-On Reset Override (PORO) function implemented. 8.7.1 Power-On Reset (POR) The POR is active whenever the oscillator is stopped. The oscillator is also considered to be stopped during the time between power-on and stable crystal resonance (see Figure 10). This time may be in the range of 200 ms to 2 s depending on temperature and supply voltage. Whenever an internal reset occurs, the oscillator stop flag is set (OSF set logic 1). chip in reset chip not in reset VDD oscillation internal reset t 001aaf897 Fig 10. Dependency between POR and oscillator After POR, the following mode is entered: • • • • • 32.768 kHz CLKOUT active Power-On Reset Override (PORO) available to be set 24 hour mode is selected Battery switch-over is enabled Battery low detection is enabled The register values after power-on are shown in Table 4. 8.7.2 Power-On Reset Override (PORO) The POR duration is directly related to the crystal oscillator start-up time. Due to the long start-up times experienced by these types of circuits, a mechanism has been built in to disable the POR and therefore speed up on-board test of the device. OSCILLATOR SCL SDA/CE RESET OVERRIDE osc stopped 0 = stopped, 1 = running reset 0 = override inactive 1 = override active CLEAR POR_OVRD 0 = clear override mode 1 = override possible 001aaj324 Fig 11. Power-On Reset (POR) system PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 21 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal The setting of the PORO mode requires that POR_OVRD in register Control_1 is set logic 1 and that the signals at the interface pins SDA/CE and SCL are toggled as illustrated in Figure 12. All timings shown are required minimum. power up 8 ms minimum 500 ns minimum 2000 ns SDA/CE SCL reset override 001aaj326 Fig 12. Power-On Reset Override (PORO) sequence, valid for both I2C-bus and SPI-bus Once the override mode is entered, the device is immediately released from the reset state and the set-up operation can commence. The PORO mode is cleared by writing logic 0 to POR_OVRD. POR_OVRD must be logic 1 before a re-entry into the override mode is possible. Setting POR_OVRD logic 0 during normal operation has no effect except to prevent accidental entry into the PORO mode. PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 22 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.8 Time and date function The majority of this registers are coded in the Binary Coded Decimal (BCD) format. 8.8.1 Register Seconds Table 15. Seconds - seconds and clock integrity register (address 03h) bit description Bit Symbol Value Place value Description 7 OSF 0 - clock integrity is guaranteed 1[1] - clock integrity is not guaranteed: oscillator has stopped and chip reset has occurred since flag was last cleared 6 to 4 SECONDS 0 to 5 ten’s place 3 to 0 0 to 9 unit place [1] actual seconds coded in BCD format Start-up value. Table 16. Seconds coded in BCD format Seconds value in decimal Upper-digit (ten’s place) Digit (unit place) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 0 0 0 0 0 0 0 01 0 0 0 0 0 0 1 02 0 0 0 0 0 1 0 : : : : : : : : 09 0 0 0 1 0 0 1 10 0 0 1 0 0 0 0 : : : : : : : : 58 1 0 1 1 0 0 0 59 1 0 1 1 0 0 1 8.8.2 Register Minutes Table 17. PCF2129A_2 Product data sheet Minutes - minutes register (address 04h) bit description Bit Symbol Value Place value Description 7 - - - unused 6 to 4 MINUTES 0 to 5 ten’s place actual minutes coded in BCD format 3 to 0 0 to 9 unit place All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 23 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.8.3 Register Hours Table 18. Bit Hours - hours register (address 05h) bit description Symbol Value Place value Description - - unused 0 - indicates AM 1 - indicates PM 0 to 1 ten’s place 0 to 9 unit place actual hours coded in BCD format when in 12 hour mode 5 to 4 HOURS 0 to 2 ten’s place 3 to 0 0 to 9 unit place 7 to 6 12 hour 5 mode[1] AMPM 4 HOURS 3 to 0 24 hour mode[1] [1] actual hours coded in BCD format when in 24 hour mode Hour mode is set by the bit 12_24 in register Control_1. 8.8.4 Register Days Table 19. Bit Days - days register (address 06h) bit description Symbol 7 to 6 5 to 4 DAYS[1] 3 to 0 [1] Value Place value Description - - unused 0 to 3 ten’s place actual day coded in BCD format 0 to 9 unit place The RTC compensates for leap years by adding a 29th day to February if the year counter contains a value which is exactly divisible by 4, including the year 00. 8.8.5 Register Weekdays Table 20. Bit Weekdays - weekdays register (address 07h) bit description Symbol Value Description 7 to 3 - - unused 2 to 0 WEEKDAYS 0 to 6 actual weekday value, see Table 21 Although the association of the weekdays counter to the actual weekday is arbitrary, the PCF2129A will assume Sunday is 000 and Monday is 001 for the purposes of determining the increment for calendar weeks. Table 21. Weekday assignments Day[1] 2 1 0 Sunday 0 0 0 Monday 0 0 1 Tuesday 0 1 0 Wednesday 0 1 1 Thursday 1 0 0 Friday 1 0 1 Saturday 1 1 0 [1] PCF2129A_2 Product data sheet Bit These bits may be re-assigned by the user. All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 24 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.8.6 Register Months Table 22. Bit Months - months register (address 08h) bit description Symbol 7 to 5 4 MONTHS 3 to 0 Table 23. Value Place value Description - - unused 0 to 1 ten’s place 0 to 9 unit place actual month coded in BCD format, see Table 23 Month assignments in BCD format Month Upper-digit (ten’s place) Digit (unit place) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 January 0 0 0 0 1 February 0 0 0 1 0 March 0 0 0 1 1 April 0 0 1 0 0 May 0 0 1 0 1 June 0 0 1 1 0 July 0 0 1 1 1 August 0 1 0 0 0 September 0 1 0 0 1 October 1 0 0 0 0 November 1 0 0 0 1 December 1 0 0 1 0 8.8.7 Register Years Table 24. Bit Years - years register (address 09h) bit description Symbol Value Place value Description 7 to 4 YEARS 0 to 9 ten’s place 3 to 0 0 to 9 unit place actual year coded in BCD format 8.8.8 Setting and reading the time Figure 13 shows the data flow and data dependencies starting from the 1 Hz clock tick. During read/write operations, the time counting circuits (memory locations 03h through 09h) are blocked. This prevents • Faulty reading of the clock and calendar during a carry condition • Incrementing the time registers during the read cycle PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 25 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 1 Hz tick SECONDS MINUTES 12_24 hour mode HOURS LEAP YEAR CALCULATION DAYS WEEKDAY MONTHS YEARS 001aaf901 Fig 13. Data flow of the time function After this read/write access is completed, the time circuit is released again and any pending request to increment the time counters that occurred during the read/write access is serviced. A maximum of 1 request can be stored; therefore, all accesses must be completed within 1 second (see Figure 14). t<1s START SLAVE ADDRESS DATA DATA STOP 013aaa215 Fig 14. Access time for read/write operations As a consequence of this method, it is very important to make a read or write access in one go, that is, setting or reading seconds through to years should be made in one single access. Failing to comply with this method could result in the time becoming corrupted. As an example, if the time (seconds through to hours) is set in one access and then in a second access the date is set, it is possible that the time may increment between the two accesses. A similar problem exists when reading. A roll over may occur between reads thus giving the minutes from one moment and the hours from the next. Therefore it is advised to read all time and date registers in one access. PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 26 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.9 Alarm function When one or more of the alarm bit fields are loaded with a valid second, minute, hour, day, or weekday and its corresponding alarm enable bit (AE_x) is logic 0, then that information is compared with the actual second, minute, hour, day, and weekday (see Figure 15). example check now signal AE_S AE_S = 1 SECOND ALARM = 1 0 SECOND TIME AE_M MINUTE ALARM = MINUTE TIME AE_H HOUR ALARM = set alarm flag AF (1) HOUR TIME AE_D DAY ALARM = DAY TIME AE_W WEEKDAY ALARM = 013aaa236 WEEKDAY TIME (1) Only when all enabled alarm settings are matching. Fig 15. Alarm function block diagram The generation of interrupts from the alarm function is described in Section 8.12.4. 8.9.1 Register Second_alarm Table 25. Bit Symbol Value Place value Description 7 AE_S 0 - Product data sheet second alarm is enabled 1[1] - second alarm is disabled 6 to 4 SECOND_ALARM 0 to 5 ten’s place 3 to 0 0 to 9 unit place second alarm information coded in BCD format [1] PCF2129A_2 Second_alarm - second alarm register (address 0Ah) bit description Default value. All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 27 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.9.2 Register Minute_alarm Table 26. Minute_alarm - minute alarm register (address 0Bh) bit description Bit Symbol Value Place value Description 7 AE_M 0 - minute alarm is enabled 1[1] - minute alarm is disabled 6 to 4 MINUTE_ALARM 0 to 5 ten’s place 3 to 0 0 to 9 unit place minute alarm information coded in BCD format [1] Default value. 8.9.3 Register Hour_alarm Table 27. Hour_alarm - hour alarm register (address 0Ch) bit description Bit Symbol Value Place value Description 7 AE_H 0 - hour alarm is enabled 1[1] - hour alarm is disabled - - unused 0 - indicates AM 1 - indicates PM hour alarm information coded in BCD format when in 12 hour mode 6 - 12 hour mode[2] 5 AMPM 4 HOUR_ALARM 0 to 1 ten’s place 0 to 9 unit place 5 to 4 HOUR_ALARM 0 to 2 ten’s place 3 to 0 0 to 9 unit place 3 to 0 24 hour mode[2] [1] Default value. [2] Hour mode is set by the bit 12_24 in register Control_1. hour alarm information coded in BCD format when in 24 hour mode 8.9.4 Register Day_alarm Table 28. Symbol Value Place value Description 7 AE_D 0 - day alarm is enabled 1[1] - day alarm is disabled 6 - - unused 5 to 4 DAY_ALARM 0 to 3 ten’s place 3 to 0 0 to 9 unit place day alarm information coded in BCD format [1] PCF2129A_2 Product data sheet Day_alarm - day rearm register (address 0Dh) bit description Bit - Default value. All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 28 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.9.5 Register Weekday_alarm Table 29. Weekday_alarm - weekday alarm register (address 0Eh) bit description Bit Symbol Value Description 7 AE_W 0 weekday alarm is enabled 1[1] weekday alarm is disabled 6 to 3 - - unused 2 to 0 WEEKDAY_ALARM 0 to 6 weekday alarm information [1] Default value. 8.9.6 Alarm flag When all enabled comparisons first match, the alarm flag AF (register Control_2) is set. AF will remain set until cleared by using the interface. Once AF has been cleared it will only be set again when the time increments to match the alarm condition once more. For clearing the flags see Section 8.10.5 Alarm registers which have their alarm enable bit AE_x at logic 1 are ignored. minutes counter 44 minute alarm 45 45 46 AF INT when AIE = 1 001aaf903 Example where only the minute alarm is used and no other interrupts are enabled. Fig 16. Alarm flag timing diagram PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 29 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.10 Timer functions The PCF2129A has a watchdog timer function. The timer can be switched on and off by using the control bit WD_CD in the register Watchdg_tim_ctl. The watchdog timer has four selectable source clocks. It can, for example, be used to detect a microprocessor with interrupt and reset capability which is out of control (see Section 8.10.3) To control the timer function and timer output, the registers Control_2, Watchdg_tim_ctl, and Watchdg_tim_val are used. 8.10.1 Register Watchdg_tim_ctl Table 30. Bit 7 Watchdg_tim_ctl - watchdog timer control register (address 10h) bit description Symbol Value WD_CD 0[1] Description watchdog timer disabled 1 watchdog timer enabled; the interrupt pin INT is activated when timed out 6 5 T 0[2] unused TI_TP 0[1] the interrupt pin INT is configured to generate a permanent active signal when MSF (register Control_2) is set 1 the interrupt pin INT is configured to generate a pulsed signal when MSF flag is set (see Figure 19) - unused 4 to 2 1 to 0 TF[1:0] timer source clock for watchdog timer 00 4.096 kHz 01 64 Hz 10 1 Hz 11[1] 1⁄ 60 Hz [1] Default value. [2] When writing to the register this bit has always to be set logic 0. 8.10.2 Register Watchdg_tim_val Table 31. Bit Watchdg_tim_val - watchdog timer value register (address 11h) bit description Symbol 7 to 0 WATCHDG_TIM_VAL[7:0] Value Description 00 to FF countdown period in seconds: n CountdownPeriod = -------------------------------------------------------------SourceClockFrequency where n is the countdown value PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 30 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal Table 32. Programmable watchdog timer TF[1:0] Timer source clock frequency Units Minimum timer period (n = 1) Units Maximum timer period (n = 255) Units 00 4.096 kHz 244 μs 62.256 ms 01 64 Hz 15.625 ms 3.984 s 10 1 Hz 1 s 255 s 11 1⁄ Hz 60 s 15300 s 60 8.10.3 Watchdog timer function The watchdog timer function is enabled or disabled by the WD_CD bit of the register Watchdg_tim_ctl (see Table 30). The two bits TF[1:0] in register Watchdg_tim_ctl determine one of the four source clock frequencies for the watchdog timer: 4.096 kHz, 64 Hz, 1 Hz, or 1⁄60 Hz (see Table 32). When the watchdog timer function is enabled, the 8-bit timer in register Watchdg_tim_val (see Table 32) determines the watchdog timer period. The watchdog timer counts down from the software programmed 8-bit binary value n in register Watchdg_tim_val. When the counter reaches 1 the watchdog timer flag WDTF (register Control_2) is set logic 1 and an interrupt will be generated. The counter does not automatically reload. When WD_CD is logic 0 (watchdog timer disabled) and the microcontroller unit (MCU) loads a watchdog timer value n, then: • the flag WDTF is reset • INT is cleared • the watchdog timer starts again Loading the counter with 0 will: • reset the flag WDTF • clear INT • stop the watchdog timer Remark: WDTF is read only and cannot be cleared with the interface. WDTF can be cleared by: • loading a value in register Watchdg_tim_val • reading of the register Control_2 Writing a logic 0 or logic 1 to WDTF has no effect. PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 31 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal MCU watchdog timer value n=1 n WDTF INT 001aag062 Counter reached 1, WDTF is logic 1, and an interrupt is generated. Fig 17. WD_CD set logic 1: watchdog activates an interrupt when timed out • When the watchdog timer counter reaches 1, the watchdog timer flag WDTF (register Control_2) is set logic 1 • When a minute or second interrupt occurs, the minute/second flag MSF (register Control_2) is set logic 1 (see Section 8.12.1). 8.10.4 Pre-defined timers: second and minute interrupt PCF2129A has two pre-defined timers which are used to generate an interrupt either once per second or once per minute. The pulse generator for the minute or second interrupt operates from an internal 64 Hz clock. It is independent of the watchdog timer. Each of these timers can be enabled by the bits SI (second interrupt) and MI (minute interrupt) in register Control_1. 8.10.5 Clearing flags The flags MSF, AF, and TSFx can be cleared by using the interface. To prevent one flag being overwritten while clearing another, a logic AND is performed during the write access. A flag is cleared by writing logic 0 whilst a flag is not cleared by writing logic 1. Writing logic 1 will result in the flag value remaining unchanged. Two examples are given for clearing the flags. Clearing a flag is made by a write command: • Bits labeled with - must be written with their previous values • Bits labeled with T have to be written with logic 0 • WDTF is read only and has to be written with logic 0 Repeatedly re-writing these bits has no influence on the functional behavior. Table 33. Register Control_2 PCF2129A_2 Product data sheet Flag location in register Control_2 Bit 7 6 5 4 3 2 1 0 MSF WDTF TSF2 AF T - - T All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 32 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal Table 34. Register Control_2 Example values in register Control_2 Bit 7 6 5 4 3 2 1 0 1 0 1 1 0 0 0 0 The following tables show what instruction must be sent to clear the appropriate flag. Table 35. Register Example to clear only AF (bit 4) Bit 7 Control_2 [1] 1 Register Control_2 Product data sheet 1 4 0 3 2 1 0 0 0[1] 0[1] 0 3 2 1 0 0 0[1] 0[1] 0 Example to clear only MSF (bit 7) Bit 7 PCF2129A_2 0 5 The bits labeled as - have to be rewritten with the previous values. Table 36. [1] 6 0 6 0 5 1 4 1 The bits labeled as - have to be rewritten with the previous values. All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 33 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.11 Timestamp function The PCF2129A has an active LOW timestamp input pin TS, internally pulled with an on-chip pull-up resistor to the internal power supply of the device. It also has a timestamp detection circuit which can detect two different events: 1. Input on pin TS is driven to an intermediate level between power supply and ground. 2. Input on pin TS is driven to ground. 1 16 2 3 15 VDD 4 5 TS R2 = 200 kΩ ±5% 6 R1 = 200 kΩ ± 20 % 14 13 12 11 7 10 8 PCF212xA 9 push-button 1 connected to cover 1 push-button 2 connected to cover 2 013aaa176 VSS Fig 18. Timestamp detection with two push-buttons on one the TS pin (e.g. for tamper detection) The timestamp function is enabled by default after power-on and it can be switched off by setting the control bit TSOFF (register Timestp_ctl). A most common application of the timestamp function is described in Ref. 3 “AN10857”. See Section 8.12.5 for a description of interrupt generation from the timestamp function. 8.11.1 Timestamp flag 1. When the TS input pin is driven to an intermediate level between the power supply and ground then the following sequence occurs: a. The actual date and time are stored in the timestamp registers. b. The timestamp flag TSF1 (register Control_1) is set. c. If the TSIE bit (register Control_2) is active, an interrupt on the INT pin is generated. The TSF1 flag can be cleared by using the interface. Clearing the flag will clear the interrupt. Once TSF1 is cleared it will only be set again when a new negative edge on pin TS is detected. 2. When the TS input pin is driven to ground the following sequence occurs: a. The actual date and time are stored in the timestamp registers. b. In addition to the TSF1 flag, the TSF2 flag (register Control_2) is set. c. If the TSIE bit is active, an interrupt on the INT pin is generated. PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 34 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal The TSF1 and TSF2 flags can be cleared by using the interface; clearing both flags will clear the interrupt. Once TSF2 is cleared it will only be set again when TS pin is driven to ground once again. 8.11.2 Timestamp mode The timestamp function has two different modes selected by the control bit TSM (timestamp mode) in register Timestp_ctl: • If TSM is logic 0 (default): in subsequent trigger events without clearing the timestamp flags, the last timestamp event is stored • If TSM is logic 1: in subsequent trigger events without clearing the timestamp flags, the first timestamp event is stored The timestamp function also depends on the control bit BTSE in register Control_3, see Section 8.11.4. 8.11.3 Timestamp registers 8.11.3.1 Register Timestp_ctl Table 37. Timestp_ctl - timestamp control register (address 12h) bit description Bit Symbol Value Description 7 TSM 0[1] in subsequent events without clearing the timestamp flags, the last event is stored 1 in subsequent events without clearing the timestamp flags, the first event is stored 0[1] timestamp function active 1 timestamp function disabled - unused 6 TSOFF 5 - 4 to 0 1_O_16_TIMESTP[4:0] [1] 8.11.3.2 Product data sheet second timestamp information coded in BCD format Register Sec_timestp Sec_timestp - second timestamp register (address 13h) bit description Bit Symbol Value Place value Description 7 - - - unused 6 to 4 SECOND_TIMESTP 0 to 5 ten’s place 3 to 0 unit place second timestamp information coded in BCD format 0 to 9 Register Min_timestp Table 39. PCF2129A_2 16 Default value. Table 38. 8.11.3.3 1⁄ Min_timestp - minute timestamp register (address 14h) bit description Bit Symbol Value Place value Description 7 - - - unused 6 to 4 MINUTE_TIMESTP 0 to 5 ten’s place 3 to 0 0 to 9 unit place minute timestamp information coded in BCD format All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 35 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.11.3.4 Register Hour_timestp Table 40. Bit Hour_timestp - hour timestamp register (address 15h) bit description Symbol 7 to 6 - Value Place value Description - - unused 0 - indicates AM 1 - indicates PM hour timestamp information coded in BCD format when in 12 hour mode 12 hour mode[1] 5 AMPM 4 HOUR_TIMESTP 0 to 1 ten’s place 0 to 9 unit place 5 to 4 HOUR_TIMESTP 0 to 2 ten’s place 3 to 0 0 to 9 unit place 3 to 0 24 hour mode[1] [1] 8.11.3.5 Hour mode is set by the bit 12_24 in register Control_1. Register Day_timestp Table 41. Bit 8.11.3.6 Day_timestp - day timestamp register (address 16h) bit description Symbol Value Place value Description 7 to 6 - - - unused 5 to 4 DAY_TIMESTP 0 to 3 ten’s place 3 to 0 0 to 9 unit place day timestamp information coded in BCD format Register Mon_timestp Table 42. Bit Mon_timestp - month timestamp register (address 17h) bit description Symbol Value Place value Description 7 to 5 - - - unused 4 0 to 1 ten’s place 0 to 9 unit place month timestamp information coded in BCD format MONTH_TIMESTP 3 to 0 8.11.3.7 Register Year_timestp Table 43. Bit PCF2129A_2 Product data sheet hour timestamp information coded in BCD format when in 24 hour mode Year_timestp - year timestamp register (address 18h) bit description Symbol Value Place value Description 7 to 4 YEAR_TIMESTP 0 to 9 ten’s place 3 to 0 0 to 9 unit place year timestamp information coded in BCD format All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 36 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.11.4 Dependency between Battery switch-over and timestamp The timestamp function depends on the control bit BTSE in register Control_3: Table 44. Battery switch-over and timestamp BTSE BF 0 Description - [1] 0 [1] 1 the battery switch-over does not affect the timestamp registers If a battery switch-over event occurs: the timestamp registers store the time and date when the switch-over occurs; after this event occurred BF is set logic 1 1 the timestamp registers are not modified; in this condition subsequent battery switch-over events or falling edges on pin TS are not registered [1] PCF2129A_2 Product data sheet Default value. All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 37 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.12 Interrupt output, INT PCF2129A has an interrupt output pin INT which is open-drain, active LOW. Interrupts may be sourced from different places: • • • • • • second or minute timer watchdog timer alarm timestamp battery switch-over battery low detection SI SECONDS COUNTER MI MINUTES COUNTER MSF: MINUTE SECOND FLAG SET CLEAR to interface: read MSF PULSE GENERATOR 1 TRIGGER CLEAR SI/MI 0 1 TI_TP INT pin from interface: clear MSF WD_CD = 1 WATCHDOG COUNTER MCU loading watchdog counter set alarm flag, AF WDTF: WATCHDOG TIMER FLAG SET CLEAR to interface: read AF AIE TSFx: TIMESTAMP FLAG SET CLEAR to interface: read TSFx TSIE BF: BATTERY FLAG SET CLEAR to interface: read BF BIE BLF: BATTERY LOW FLAG SET CLEAR to interface: read BLF BLIE from interface: clear TSF set battery flag, BF from interface: clear BF set battery low flag, BLF WD_CD = 0 AF: ALARM FLAG SET CLEAR from interface: clear AF set timestamp flag, TSFx to interface: read WD_CD from battery low detection circuit: clear BF 001aaj399 When SI, MI, WD_CD, AIE, TSIE, BIE, BLIE are all disabled, INT will remain high-impedance. Fig 19. Interrupt block diagram PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 38 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal The control bit TI_TP (register Watchdg_tim_ctl) is used to configure whether the interrupts generated from the second/minute timer (flag MSF in register Control_2) are pulsed signals or a permanently active signal. All the other interrupt sources generate a permanently active interrupt signal which follows the status of the corresponding flags. When the interrupt sources are all disabled, INT remains high-impedance. • The flags MSF, AF, TSFx, and BF can be cleared by using the interface. • The flag WDTF is read only. How it can be cleared is explained in Section 8.10.5. • The flag BLF is read only. It is cleared automatically from the battery low detection circuit when the battery is replaced. 8.12.1 Minute and second interrupts Minute and second interrupts are generated by predefined timers. The timers can be enabled independently from one another by the bits MI and SI in register Control_1. However, a minute interrupt enabled on top of a second interrupt will not be distinguishable since it will occur at the same time. The minute/second flag MSF (register Control_2) is set logic 1 when either the seconds or the minutes counter increments according to the actually enabled interrupt (see Table 45). The MSF flag can be read and cleared by the interface. Table 45. Effect of bits MI and SI on pin INT and bit MSF MI SI Result on INT Result on MSF 0 0 no interrupt generated MSF never set 1 0 an interrupt once per minute MSF set when minutes counter increments 0 1 an interrupt once per second MSF set when seconds counter increments 1 1 an interrupt once per second MSF set when seconds counter increments When MSF is set logic 1: • If TI_TP is logic 1 the interrupt is generated as a pulsed signal. • If TI_TP is logic 0 the interrupt is permanently active signal that remains until MSF is cleared. seconds counter 58 59 minutes counter 59 00 11 12 00 01 INT when SI enabled MSF when SI enabled INT when only MI enabled MSF when only MI enabled 001aaf905 In this example, bit TI_TP is logic 1 and the MSF flag is not cleared after an interrupt. Fig 20. INT example for SI and MI when TI_TP is logic 1 PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 39 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal seconds counter 58 59 minutes counter 59 00 11 12 00 01 INT when SI enable MSF when SI enable INT when only MI enabled MSF when only MI enabled 001aag072 In this example, bit TI_TP is logic 0 and the MSF flag is cleared after an interrupt. Fig 21. INT example for SI and MI when TI_TP is logic 0 The pulse generator for the minute/second interrupt operates from an internal 64 Hz clock and generates a pulse of 1⁄64 seconds in duration. 8.12.2 INT pulse shortening If the MSF flag (register Control_2) is cleared before the end of the INT pulse, then the INT pulse is shortened. This allows the source of a system interrupt to be cleared immediately when it is serviced, i.e. the system does not have to wait for the completion of the pulse before continuing; see Figure 22. Instructions for clearing the bit MSF can be found in Section 8.10.5. seconds counter 58 59 MSF INT (1) SCL 8th clock instruction CLEAR INSTRUCTION 001aaf908 (1) Indicates normal duration of INT pulse. The timing shown for clearing bit MSF is also valid for the non-pulsed interrupt mode, i.e. when TI_TP is logic 0, where the INT pulse may be shortened by setting both bits MI and SI logic 0. Fig 22. Example of shortening the INT pulse by clearing the MSF flag 8.12.3 Watchdog timer interrupts The generation of interrupts from the watchdog timer is controlled using the WD_CD bit (register Watchdg_tim_ctl). The interrupt is generated as an active signal which follows the status of the watchdog timer flag WDTF (register Control_2). No pulse generation is possible for watchdog timer interrupts. PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 40 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal The interrupt is cleared when the flag WDTF is reset. WDTF is a read only bit and cannot be cleared by using the interface. Instructions for clearing it can be found in Section 8.10.5. 8.12.4 Alarm interrupts Generation of interrupts from the alarm function is controlled via the bit AIE (register Control_2). If AIE is enabled, the INT pin will follow the status of bit AF (register Control_2). Clearing AF will immediately clear INT. No pulse generation is possible for alarm interrupts. minute counter 44 minute alarm 45 45 AF INT SCL 8th clock instruction CLEAR INSTRUCTION 001aaf910 Example where only the minute alarm is used and no other interrupts are enabled. Fig 23. AF timing diagram 8.12.5 Timestamp interrupts Interrupt generation from the timestamp function is controlled using the TSIE bit (register Control_2). If TSIE is enabled the INT pin follows the status of the flags TSFx. Clearing the flags TSFx immediately clears INT. No pulse generation is possible for timestamp interrupts. 8.12.6 Battery switch-over interrupts Generation of interrupts from the battery switch-over is controlled via the BIE bit (register Control_3). If BIE is enabled, the INT pin follows the status of bit BF in register Control_3 (see Table 44). Clearing BF immediately clears INT. No pulse generation is possible for battery switch-over interrupts. 8.12.7 Battery low detection interrupts Generation of interrupts from the battery low detection is controlled via the BLIE bit (register Control_3). If BLIE is enabled the INT pin will follow the status of bit BLF (register Control_3). The interrupt is cleared when the battery is replaced (BLF is logic 0) or when bit BLIE is disabled (BLIE is logic 0). BLF is read only and therefore cannot be cleared via the interface. PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 41 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.13 External clock test mode A test mode is available which allows on-board testing. In this mode it is possible to set up test conditions and control the operation of the RTC. The test mode is entered by setting bit EXT_TEST logic 1 (register Control_1). Then pin CLKOUT becomes an input. The test mode replaces the internal clock signal (64 Hz) with the signal applied to pin CLKOUT. Every 64 positive edges applied to pin CLKOUT generate an increment of one second. The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a maximum period of 1000 ns. The internal clock, now sourced from CLKOUT, is divided down by a 26 divider chain called prescaler (see prescaler in Table 46). The prescaler can be set into a known state by using bit STOP. When bit STOP is logic 1, the prescaler is reset to 0. STOP must be cleared before the prescaler can operate again. From a stop condition, the first 1 second increment will take place after 32 positive edges on pin CLKOUT. Thereafter, every 64 positive edges will cause a 1 second increment. Remark: Entry into test mode is not synchronized to the internal 64 Hz clock. When entering the test mode, no assumption as to the state of the prescaler can be made. Operating example: 1. Set EXT_TEST test mode (register Control_1, EXT_TEST is logic 1). 2. Set bit STOP (register Control_1, STOP is logic 1). 3. Set time registers to desired value. 4. Clear STOP (register Control_1, STOP is logic 0). 5. Apply 32 clock pulses to CLKOUT. 6. Read time registers to see the first change. 7. Apply 64 clock pulses to CLKOUT. 8. Read time registers to see the second change. Repeat 7 and 8 for additional increments. PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 42 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 8.14 STOP bit function The function of the STOP bit is to allow for accurate starting of the time circuits. STOP will cause the upper part of the prescaler (F9 to F14) to be held in reset and thus no 1 Hz ticks are generated. The time circuits can then be set and will not increment until the STOP bit is released. STOP will not affect the CLKOUT signal but the output of the prescaler in the range of 32 Hz to 1 Hz (see Figure 24). The lower stages of the prescaler, F0 to F8, are not reset and because the I2C-bus and the SPI-bus are asynchronous to the crystal oscillator, the accuracy of re-starting the time circuits is between 0 and one 64 Hz cycle (0.484375 s and 0.500000 s), see Table 46 and Figure 25. Table 46. First increment of time circuits after stop release Bit STOP Prescaler bits[1] F0 to F8 - F9 to F14 1 Hz tick Time hh:mm:ss Comment 12:45:12 prescaler counting normally Clock is running normally 0 010000111-010100 STOP bit is activated by user. F0 to F8 are not reset and values cannot be predicted externally 1 xxxxxxxxx-000000 12:45:12 prescaler is reset; time circuits are frozen 08:00:00 prescaler is reset; time circuits are frozen 08:00:00 prescaler is now running New time is set by user 1 xxxxxxxxx-000000 STOP bit is released by user xxxxxxxxx-000000 0 xxxxxxxxx-100000 0 xxxxxxxxx-100000 0 xxxxxxxxx-110000 : : 0 111111111-111110 0 000000000-000001 08:00:01 0 100000000-000001 08:00:01 : : : 0 111111111-111111 08:00:01 0 000000000-000000 0 100000000-000000 : : : 0 111111111-111110 08:00:01 0 000000000-000001 08:00:02 0.484375 - 0.500000 s 0 08:00:00 08:00:00 08:00:00 : 1s 08:00:00 0 to 1 transition of F14 increments the time circuits 08:00:01 0 to 1 transition of F14 increments the time circuits 001aaj479 [1] F0 is clocked at 32.768 kHz. PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 43 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal LOWER PRESCALER 32768 Hz 16384 Hz F0 8192 Hz F1 UPPER PRESCALER 128 Hz 4096 Hz F2 64 Hz F8 F9 F10 F13 F14 RES RES RES RES OSC 1 Hz tick stop 001aaj342 Fig 24. STOP bit functional diagram 64 Hz stop released 0 ms - 15.625 ms 001aaj343 Fig 25. STOP bit release timing PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 44 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 9. Interfaces The PCF2129A has a selectable I2C-bus or SPI-bus interface. The selection is done using the interface selection pin IFS (see Table 47). Table 47. Interface selection input pin IFS Pin Connection Bus interface Reference IFS VSS SPI-bus Section 9.1 BBS I2C-bus Section 9.2 VDD VDD SCL RPU RPU SDI SDO SCL CE SDA SCL SDI SDO SDA/CE IFS 1 20 2 19 3 18 4 17 5 6 VSS SCL VDD SDI SDO BBS SDA/CE IFS 16 15 14 8 13 9 12 10 11 VSS VSS 001aaj706 2 19 3 18 4 17 5 VDD BBS 16 PCF2129A 15 7 14 8 13 9 12 10 11 VSS 001aaj707 To select the I2C-bus interface pin IFS has to be connected to pin BBS. To select the SPI-bus interface, pin IFS has to be connected to pin VSS. a. SPI-bus interface selection 20 6 PCF2129A 7 1 b. I2C-bus interface selection Fig 26. Interface selection PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 45 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 9.1 SPI-bus interface Data transfer to and from the device is made via a 3 line SPI-bus (see Table 48). The data lines for input and output are split. The data input and output line can be connected together to facilitate a bidirectional data bus (see Figure 27). The SPI-bus is initialized whenever the chip enable line pin SDA/CE is inactive. SDI SDI SDO SDO two wire mode single wire mode 001aai560 Fig 27. SDI, SDO configurations Table 48. Serial interface Symbol Function SDA/CE SCL Description chip enable input; active LOW [1] serial clock input when HIGH, the interface is reset; input may be higher than VDD when SDA/CE is HIGH, input may float; input may be higher than VDD SDI serial data input when SDA/CE is HIGH, input may float; input may be higher than VDD; input data is sampled on the rising edge of SCL SDO serial data output push-pull output; drives from VSS to VBBS; output data is changed on the falling edge of SCL [1] The chip enable must not be wired permanently LOW. 9.1.1 Data transmission The chip enable signal is used to identify the transmitted data. Each data transfer is a byte, with the Most Significant Bit (MSB) sent first. The transmission is controlled by the active LOW chip enable signal SDA/CE. The first byte transmitted is the command byte. Subsequent bytes will be either data to be written or data to be read (see Figure 28). data bus COMMAND DATA DATA DATA SDA/CE 013aaa311 Fig 28. Data transfer overview The command byte defines the address of the first register to be accessed and the read/write mode. The address counter will auto increment after every access and will reset to zero after the last valid register is accessed. The R/W bit defines if the following bytes will be read or write information. PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 46 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal Table 49. Command byte definition Bit Symbol 7 R/W 6 to 5 Value Description data read or write selection SA 0 write data 1 read data 01 subaddress; other codes will cause the device to ignore data transfer 4 to 0 R/W b7 0 RA addr 03h SA b6 0 b5 1 00h to 1Bh register address b4 0 b3 0 b2 0 seconds data 45BCD b1 1 b0 1 b7 0 b6 1 b5 0 b4 0 b3 0 b2 1 minutes data 10BCD b1 0 b0 1 b7 0 b6 0 b5 0 b4 1 b3 0 b2 0 b1 0 b0 0 SCL SDI SDA/CE address counter xx 03 04 05 001aaj348 In this example, the register Seconds is set to 45 seconds and the register Minutes to 10 minutes. Fig 29. SPI-bus write example R/W b7 1 addr 08h SA b6 0 b5 1 b4 0 b3 1 b2 0 months data 11BCD b1 0 b0 0 b7 0 b6 0 b5 0 b4 1 b3 0 b2 0 years data 06BCD b1 0 b0 1 b7 0 b6 0 b5 0 b4 0 b3 0 b2 1 b1 1 b0 0 SCL SDI SDO SDA/CE address counter xx 08 09 0A 001aaj349 In this example, the registers Months and Years are read. The pins SDI and SDO are not connected together. For this configuration, it is important that pin SDI is never left floating. It must always be driven either HIGH or LOW. If pin SDI is left open, high IDD currents may result. Fig 30. SPI-bus read example PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 47 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 9.2 I2C-bus interface The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial Clock Line (SCL). Both lines are connected to a positive supply via a pull-up resistor. Data transfer is initiated only when the bus is not busy. 9.2.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line remains stable during the HIGH period of the clock pulse as changes in the data line at this time are interpreted as control signals (see Figure 31). SDA SCL data line stable; data valid change of data allowed mbc621 Fig 31. Bit transfer 9.2.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH, is defined as the START condition S. A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition P (see Figure 32). SDA SDA SCL SCL S P START condition STOP condition mbc622 Fig 32. Definition of START and STOP conditions Remark: For the PCF2129A a repeated START is not allowed. Therefore a STOP has to be released before the next START. 9.2.3 System configuration A device generating a message is a transmitter; a device receiving a message is the receiver. The device that controls the message is the master; and the devices which are controlled by the master are the slaves. The PCF2129A can act as a slave transmitter and a slave receiver. PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 48 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal SDA SCL MASTER TRANSMITTER RECEIVER SLAVE TRANSMITTER RECEIVER SLAVE RECEIVER MASTER TRANSMITTER RECEIVER MASTER TRANSMITTER mba605 Fig 33. System configuration 9.2.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle. • A slave receiver which is addressed must generate an acknowledge after the reception of each byte. • Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. • The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). • A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C-bus is illustrated in Figure 34. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master 1 2 8 9 S START condition clock pulse for acknowledgement mbc602 Fig 34. Acknowledgement on the I2C-bus 9.2.5 I2C-bus protocol After a start condition a valid hardware address has to be sent to a PCF2129A device. The appropriate I2C-bus slave address is 1010001. The entire I2C-bus slave address byte is shown in Table 50. PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 49 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal I2C slave address byte Table 50. Slave address Bit 7 6 5 4 3 2 1 0 0 1 0 0 0 1 R/W MSB LSB 1 The R/W bit defines the direction of the following single or multiple byte data transfer (read is logic 1, write is logic 0). For the format and the timing of the START condition (S), the STOP condition (P), and the acknowledge (A) refer to the I2C-bus specification Ref. 13 “UM10204” and the characteristics table (Table 55). In the write mode a data transfer is terminated by sending either a STOP condition or the START condition of the next data transfer. acknowledge from PCF2129A S 1 0 1 0 0 0 1 slave address 0 acknowledge from PCF2129A acknowledge from PCF2129A A A A register address 00h to 1Dh write bit 0 to n data bytes P/S START/ STOP 001aaj723 Fig 35. Bus protocol, writing to registers acknowledge from PCF2129A S 1 0 1 0 0 0 1 slave address 0 acknowledge from PCF2129A A A register address 00h to 1Dh write bit acknowledge from PCF2129A S 1 0 1 0 0 slave address 0 1 1 A read bit DATA BYTE set register address P STOP acknowledge from master no acknowledge A A LAST DATA BYTE 0 to n data bytes P read register data 001aaj724 Fig 36. Bus protocol, reading from registers PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 50 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 10. Internal circuitry VDD SCL VBAT BBS SDI SDO INT SDA/CE IFS TS CLKOUT VSS PCF2129A 001aaj705 Fig 37. Device diode protection diagram of PCF2129A PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 51 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 11. Limiting values Table 51. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD Conditions Min Max Unit supply voltage −0.5 +4.5 V IDD supply current −50 +50 mA Vi input voltage −0.5 +6.5 V II input current −10 +10 mA VO output voltage −0.5 +6.5 V IO output current at pin SDA/CE VBAT battery supply voltage Ptot total power dissipation mA +20 mA −0.5 +4.5 V - 300 mW HBM - ±3000 V MM [2] - ±250 V CDM [3] - ±1500 V latch-up current [4] - 200 mA Tstg storage temperature [5] −55 +85 °C Toper operating temperature −40 +85 °C Ilu Product data sheet +10 −10 [1] VESD PCF2129A_2 −10 electrostatic discharge voltage [1] Pass level; Human Body Model (HBM) according to Ref. 7 “JESD22-A114”. [2] Pass level; Machine Model (MM), according to Ref. 8 “JESD22-A115”. [3] Pass level; Charged-Device Model (CDM), according to Ref. 9 “JESD22-C101”. [4] Pass level; latch-up testing according to Ref. 10 “JESD78” at maximum ambient temperature (Tamb(max)). [5] According to the NXP store and transport requirements (see Ref. 12 “NX3-00092”) the devices have to be stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to 75 %. For long term storage products deviant conditions are described in that document. All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 52 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 12. Static characteristics Table 52. Static characteristics VDD = 1.8 V to 4.2 V; VSS = 0 V; Tamb = −40 °C to +85 °C, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies [1] VDD supply voltage 1.8 - 4.2 V VBAT battery supply voltage 1.8 - 4.2 V VDD(cal) calibration supply voltage - 3.3 - V Vlow low voltage - 1.2 - V IDD supply current - - 800 μA - - 200 μA interface active SPI-bus fSCL = 6.5 MHz I2C-bus fSCL = 400 kHz interface inactive (fSCL = 0 Hz) CLKOUT disabled (COF[2:0]) = 111), one power supply VDD (PWRMNG[2:0] = 111), timestamp detection disabled (TSOFF = 1)[2] VDD = 2.0 V - 500 - nA VDD = 3.3 V - 700 1500 nA VDD = 4.2 V - 800 - nA CLKOUT enabled at 32 kHz (default), one power supply VDD (PWRMNG[2:0] = 111), timestamp detection disabled (TSOFF = 1) VDD = 2.0 V - 600 - nA VDD = 3.3 V - 850 - nA VDD = 4.2 V - 1050 - nA CLKOUT disabled (COF[2:0]) = 111), power management functions enabled (default), timestamp detection enabled (default) VDD = 2.0 V - 1800 - nA VDD = 3.3 V - 2150 - nA VDD = 4.2 V - 2350 3500 nA CLKOUT enabled at 32 kHz (default); power management functions enabled (default), timestamp detection enabled (default) IBAT battery supply current VDD = 2.0 V - 1900 - nA VDD = 3.3 V - 2300 - nA VDD = 4.2 V - 2600 - nA - 50 100 nA VDD active; VBAT = 3.0 V Power management Vth(sw)bat battery switch threshold voltage - 2.5 - V Vth(bat)low low battery threshold voltage - 2.5 - V PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 53 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal Table 52. Static characteristics …continued VDD = 1.8 V to 4.2 V; VSS = 0 V; Tamb = −40 °C to +85 °C, unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit −0.5 - VDD + 0.5 V - - 0.25VDD V - - 0.3VDD V 0.7VDD - - V −1 0 +1 μA - - 7 pF on pins CLKOUT, INT, referring to external pull-up −0.5 - 5.5 V on pin SDO −0.5 - VBBS + 0.5 V Inputs VI input voltage VIL LOW-level input voltage Tamb = −20 °C to +85 °C; VDD > 2.0 V VIH HIGH-level input voltage ILI input leakage current Ci input capacitance VI = VDD or VSS [3] Outputs output voltage VO LOW-level output current IOL output sink current; VOL = 0.4 V on pin SDA/CE [4] on all other outputs 3 17 - mA 1.0 - - mA IOH HIGH-level output current output source current; on pin SDO; VOH = 3.8 V; VDD = 4.2 V 1.0 - - mA ILO output leakage current VO = VDD or VSS −1 0 1 μA [1] For reliable oscillator start-up at power-on: VDD(po)min = VDD(min) + 0.3 V. [2] Timer source clock = 1⁄60 Hz, level of pins SDA/CE, SDI, and SCL is VDD or VSS. [3] Tested on sample basis. [4] For further information, see Figure 38. PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 54 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 12.1 Current consumption characteristics, typical 001aal763 22 IOL (mA) 18 14 10 6 1.5 2.5 3.5 4.5 VDD (V) Typical value; VOL = 0.4 V. Fig 38. IOL on pin SDA/CE 001aaj432 2.0 IDD (μA) 1.6 1.2 VDD = 3 V VDD = 2 V 0.8 0.4 0 −40 −20 0 20 40 60 80 100 Temperature (°C) CLKOUT disabled; PWRMNG[2:0] = 111; TSOFF = 1; TS input floating. Fig 39. IDD as a function of temperature PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 55 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 001aaj433 2.0 IDD (μA) 1.6 1.2 CLKOUT enabled at 32 kHz 0.8 CLKOUT OFF 0.4 0 1.8 2.2 2.6 3.0 3.4 3.8 4.2 VDD (V) a. PWRMNG[2:0] = 111; TSOFF = 1; Tamb = 25 °C; TS input floating. 001aaj434 4.0 IDD (μA) 3.2 CLKOUT enabled at 32 kHz 2.4 CLKOUT OFF 1.6 0.8 0 1.8 2.2 2.6 3.0 3.4 3.8 4.2 VDD (V) b. PWRMNG[2:0] = 000; TSOFF = 0; Tamb = 25 °C; TS input floating. Fig 40. IDD as a function of VDD PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 56 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 12.2 Frequency characteristics Table 53. Frequency characteristics VDD = 1.8 V to 4.2 V; VSS = 0 V; Tamb = +25 °C, unless otherwise specified. Symbol Parameter Conditions Min Typ fo output frequency on pin CLKOUT; VDD or VBAT = 3.3 V; COF[2:0] = 000; AO[3:0] = 1000 - 32.768 - Δf/f frequency stability VDD or VBAT = 3.3 V Unit kHz Tamb = −15 °C to +60 °C [1] - ±3 ±5 ppm Tamb = −25 °C to −15 °C and Tamb = +60 °C to +65 °C [1] - ±5 ±10 ppm [2] - - ±3 ppm - ±1 - ppm/V Δfxtal/fxtal relative crystal frequency variation crystal aging, first year; VDD or VBAT = 3.3 V Δf/ΔV on pin CLKOUT frequency variation with voltage Max [1] ±1 ppm corresponds to a time deviation of ±0.0864 seconds per day. [2] Not production tested. Effects of reflow solder not included (see Ref. 3 “AN10857”). 001aaj650 40 Frequency stability (ppm) ± 10 ppm ± 5 ppm ± 10 ppm 0 (1) −40 (2) −80 −40 −20 0 20 40 60 80 100 Temperature (°C) (1) Temperature compensated frequency. (2) Uncompensated typical tuning-fork crystal frequency. Fig 41. Characteristic of frequency with respect to temperature PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 57 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 13. Dynamic characteristics 13.1 SPI-bus timing characteristics Table 54. SPI-bus characteristics VDD = 1.8 V to 4.2 V; VSS = 0 V; Tamb = −40 °C to +85 °C, unless otherwise specified. All timing values are valid within the operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage swing of VSS to VDD (see Figure 42). Symbol Parameter Conditions VDD = 1.8 V VDD = 4.2 V Min Min Max Unit Max Pin SCL fclk(SCL) SCL clock frequency - 2.0 - 6.5 MHz tSCL SCL time 800 - 140 - ns tclk(H) clock HIGH time 100 - 70 - ns tclk(L) clock LOW time 400 - 70 - ns tr rise time for SCL signal - 100 - 30 ns tf fall time for SCL signal - 100 - 30 ns 60 - 30 - ns Pin SDA/CE tsu(CE_N) CE_N set-up time th(CE_N) CE_N hold time 40 - 25 - ns trec(CE_N) CE_N recovery time 100 - 30 - ns tw(CE_N) CE_N pulse width - 0.99 - 0.99 s Pin SDI tsu set-up time set-up time for SDI data 70 - 20 - ns th hold time hold time for SDI data 70 - 20 - ns SDO read delay time CL = 50 pF - 225 - 55 ns tdis(SDO) SDO disable time [1] - 90 - 25 ns tt(SDI-SDO) transition time from SDI to SDO to avoid bus conflict 0 - 0 - ns Pin SDO td(R)SDO [1] No load value; bus will be held up by bus capacitance; use RC time constant with application values. PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 58 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal tw(CE_N) CE tsu(CE_N) trec(CE_N) tr tf tclk(SCL) th(CE_N) 80% SCL 20% tclk(L) tclk(H) WRITE tsu th SDI SDO R/W SA2 RA0 b6 b0 b7 b6 b0 high-Z READ SDI b7 tt(SDI-SDO) td(R)SDO SDO high-Z b7 tdis(SDO) b6 b0 013aaa152 Fig 42. SPI-bus timing PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 59 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 13.2 I2C-bus timing characteristics Table 55. I2C-bus characteristics All timing characteristics are valid within the operating supply voltage and ambient temperature range and reference to 30 % and 70 % with an input voltage swing of VSS to VDD (see Figure 43). Symbol Parameter Standard mode Fast-mode (Fm) Unit Min Max Min Max 0 100 0 400 kHz Pin SCL [1] fSCL SCL clock frequency tLOW LOW period of the SCL clock 4.7 - 1.3 - μs tHIGH HIGH period of the SCL clock 4.0 - 0.6 - μs Pin SDA/CE tSU;DAT data set-up time 250 - 100 - ns tHD;DAT data hold time 0 - 0 - ns Pins SCL and SDA/CE tBUF bus free time between a STOP and START condition 4.7 - 1.3 - μs tSU;STO set-up time for STOP condition 4.0 - 0.6 - μs tHD;STA hold time (repeated) START condition 4.0 - 0.6 - μs tSU;STA set-up time for a repeated START condition 4.7 - 0.6 - μs tr rise time of both SDA and SCL signals [2][3][4] - 1000 20 + 0.1Cb 300 ns tf fall time of both SDA and SCL signals [2][3][4] - 300 20 + 0.1Cb 300 ns tVD;ACK data valid acknowledge time [5] 0.1 3.45 0.1 0.9 μs tVD;DAT data valid time [6] 300 - 75 - ns pulse width of spikes that must be suppressed by the input filter [7] - 50 - 50 ns tSP PCF2129A_2 Product data sheet [1] The minimum SCL clock frequency is limited by the bus time-out feature which resets the serial bus interface if either the SDA or SCL is held LOW for a minimum of 25 ms. The bus time-out feature must be disabled for DC operation. [2] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to bridge the undefined region of the SCL’s falling edge. [3] Cb is the total capacitance of one bus line in pF. [4] The maximum tf for the SDA and SCL bus lines is 300 ns. The maximum fall time for the SDA output stage, tf is 250 ns. This allows series protection resistors to be connected between the SDA/CE pin, the SCL pin, and the SDA/SCL bus lines without exceeding the maximum tf. [5] tVD;ACK is the time of the acknowledgement signal from SCL LOW to SDA (out) LOW. [6] tVD;DAT is the minimum time for valid SDA (out) data following SCL LOW. [7] Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns. All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 60 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal PROTOCOL START CONDITION (S) tSU;STA BIT 7 MSB (A7) tLOW BIT 6 (A6) tHIGH BIT 0 LSB (R/W) ACKNOWLEDGE (A) STOP CONDITION (P) 1 / fSCL SCL tBUF tr tf SDA tHD;STA tSU;DAT tHD;DAT tVD;DAT tSU;STO mbd820 Fig 43. I2C-bus timing diagram; rise and fall times refer to 30 % and 70 % 14. Application information For information about application configuration see Ref. 3 “AN10857”. PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 61 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 15. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 10 1 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 44. Package outline SOT163-1 (SO20) PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 62 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 16. Soldering For information about soldering see Ref. 3 “AN10857”. 17. Abbreviations Table 56. PCF2129A_2 Product data sheet Abbreviations Acronym Description AM Ante Meridiem BCD Binary Coded Decimal CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DC Direct Current GPS Global Positioning System HBM Human Body Model I2C Inter-Integrated Circuit IC Integrated Circuit LSB Least Significant Bit MCU Microcontroller Unit MM Machine Model MSB Most Significant Bit PM Post Meridiem POR Power-On Reset PORO Power-On Reset Override PPM Parts Per Million RC Resistance-Capacitance RTC Real Time Clock SCL Serial Clock Line SDA Serial DAta line SPI Serial Peripheral Interface SRAM Static Random Access Memory TCXO Temperature Compensated Xtal Oscillator Xtal crystal All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 63 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 18. References [1] AN10365 — Surface mount reflow soldering description [2] AN10853 — Handling precautions of ESD sensitive devices [3] AN10857 — Application and soldering information for PCF2127A and PCF2129A TCXO RTC [4] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [5] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena [6] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices [7] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) [8] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) [9] JESD22-C101 — Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components [10] JESD78 — IC Latch-Up Test [11] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices [12] NX3-00092 — NXP store and transport requirements [13] UM10204 — I2C-bus specification and user manual PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 64 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 19. Revision history Table 57. Revision history Document ID Release date Data sheet status Change notice Supersedes PCF2129A_2 20100507 Product data sheet - PCF2129A_1 Modifications: PCF2129A_1 PCF2129A_2 Product data sheet • • Removed Fast-mode plus (Fm+) I2C-bus specification Added Figure 38. 20100113 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 - © NXP B.V. 2010. All rights reserved. 65 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 20. Legal information 20.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 20.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 20.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 66 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 20.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 21. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 67 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 22. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.2.1 8.2.2 8.2.3 8.3 8.3.1 8.3.1.1 8.3.2 8.4 8.4.1 8.5 8.5.1 8.5.1.1 8.5.1.2 8.5.1.3 8.5.1.4 8.5.2 8.5.3 8.6 8.7 8.7.1 8.7.2 8.8 8.8.1 8.8.2 8.8.3 8.8.4 8.8.5 8.8.6 8.8.7 8.8.8 8.9 8.9.1 8.9.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Register overview . . . . . . . . . . . . . . . . . . . . . . . 6 Control registers . . . . . . . . . . . . . . . . . . . . . . . . 9 Register Control_1 . . . . . . . . . . . . . . . . . . . . . . 9 Register Control_2 . . . . . . . . . . . . . . . . . . . . . 10 Register Control_3 . . . . . . . . . . . . . . . . . . . . . 11 Register CLKOUT_ctl . . . . . . . . . . . . . . . . . . . 12 Temperature compensated crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Temperature measurement . . . . . . . . . . . . . . 12 Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Register Aging_offset . . . . . . . . . . . . . . . . . . . 14 Crystal aging correction . . . . . . . . . . . . . . . . . 14 Power management functions . . . . . . . . . . . . 15 Battery switch-over function . . . . . . . . . . . . . . 15 Standard mode . . . . . . . . . . . . . . . . . . . . . . . . 16 Direct switching mode . . . . . . . . . . . . . . . . . . 16 Battery switch-over disabled: only one power supply (VDD) . . . . . . . . . . . . . 17 Battery switch-over architecture . . . . . . . . . . . 17 Battery backup supply . . . . . . . . . . . . . . . . . . 18 Battery low detection function. . . . . . . . . . . . . 19 Oscillator stop detection function . . . . . . . . . . 20 Reset function . . . . . . . . . . . . . . . . . . . . . . . . 21 Power-On Reset (POR) . . . . . . . . . . . . . . . . . 21 Power-On Reset Override (PORO) . . . . . . . . 21 Time and date function . . . . . . . . . . . . . . . . . . 23 Register Seconds . . . . . . . . . . . . . . . . . . . . . . 23 Register Minutes. . . . . . . . . . . . . . . . . . . . . . . 23 Register Hours . . . . . . . . . . . . . . . . . . . . . . . . 24 Register Days . . . . . . . . . . . . . . . . . . . . . . . . . 24 Register Weekdays. . . . . . . . . . . . . . . . . . . . . 24 Register Months . . . . . . . . . . . . . . . . . . . . . . . 25 Register Years . . . . . . . . . . . . . . . . . . . . . . . . 25 Setting and reading the time. . . . . . . . . . . . . . 25 Alarm function. . . . . . . . . . . . . . . . . . . . . . . . . 27 Register Second_alarm . . . . . . . . . . . . . . . . . 27 Register Minute_alarm . . . . . . . . . . . . . . . . . . 28 8.9.3 8.9.4 8.9.5 8.9.6 8.10 8.10.1 8.10.2 8.10.3 8.10.4 Register Hour_alarm . . . . . . . . . . . . . . . . . . . Register Day_alarm . . . . . . . . . . . . . . . . . . . . Register Weekday_alarm. . . . . . . . . . . . . . . . Alarm flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer functions. . . . . . . . . . . . . . . . . . . . . . . . Register Watchdg_tim_ctl . . . . . . . . . . . . . . . Register Watchdg_tim_val . . . . . . . . . . . . . . . Watchdog timer function . . . . . . . . . . . . . . . . Pre-defined timers: second and minute interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.10.5 Clearing flags . . . . . . . . . . . . . . . . . . . . . . . . . 8.11 Timestamp function . . . . . . . . . . . . . . . . . . . . 8.11.1 Timestamp flag. . . . . . . . . . . . . . . . . . . . . . . . 8.11.2 Timestamp mode . . . . . . . . . . . . . . . . . . . . . . 8.11.3 Timestamp registers. . . . . . . . . . . . . . . . . . . . 8.11.3.1 Register Timestp_ctl . . . . . . . . . . . . . . . . . . . 8.11.3.2 Register Sec_timestp. . . . . . . . . . . . . . . . . . . 8.11.3.3 Register Min_timestp . . . . . . . . . . . . . . . . . . . 8.11.3.4 Register Hour_timestp . . . . . . . . . . . . . . . . . . 8.11.3.5 Register Day_timestp. . . . . . . . . . . . . . . . . . . 8.11.3.6 Register Mon_timestp . . . . . . . . . . . . . . . . . . 8.11.3.7 Register Year_timestp . . . . . . . . . . . . . . . . . . 8.11.4 Dependency between Battery switch-over and timestamp . . . . . . . . . . . . . . 8.12 Interrupt output, INT. . . . . . . . . . . . . . . . . . . . 8.12.1 Minute and second interrupts. . . . . . . . . . . . . 8.12.2 INT pulse shortening . . . . . . . . . . . . . . . . . . . 8.12.3 Watchdog timer interrupts . . . . . . . . . . . . . . . 8.12.4 Alarm interrupts . . . . . . . . . . . . . . . . . . . . . . . 8.12.5 Timestamp interrupts . . . . . . . . . . . . . . . . . . . 8.12.6 Battery switch-over interrupts . . . . . . . . . . . . 8.12.7 Battery low detection interrupts . . . . . . . . . . . 8.13 External clock test mode . . . . . . . . . . . . . . . . 8.14 STOP bit function . . . . . . . . . . . . . . . . . . . . . . 9 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 SPI-bus interface . . . . . . . . . . . . . . . . . . . . . . 9.1.1 Data transmission . . . . . . . . . . . . . . . . . . . . . 9.2 I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . 9.2.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.2 START and STOP conditions. . . . . . . . . . . . . 9.2.3 System configuration . . . . . . . . . . . . . . . . . . . 9.2.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.5 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 10 Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 11 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 12 Static characteristics . . . . . . . . . . . . . . . . . . . 28 28 29 29 30 30 30 31 32 32 34 34 35 35 35 35 35 36 36 36 36 37 38 39 40 40 41 41 41 41 42 43 45 46 46 48 48 48 48 49 49 51 52 53 continued >> PCF2129A_2 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 02 — 7 May 2010 © NXP B.V. 2010. All rights reserved. 68 of 69 PCF2129A NXP Semiconductors Integrated RTC, TCXO and quartz crystal 12.1 12.2 13 13.1 13.2 14 15 16 17 18 19 20 20.1 20.2 20.3 20.4 21 22 Current consumption characteristics, typical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency characteristics. . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . SPI-bus timing characteristics . . . . . . . . . . . . I2C-bus timing characteristics . . . . . . . . . . . . . Application information. . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information. . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 57 58 58 60 61 62 63 63 64 65 66 66 66 66 67 67 68 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 7 May 2010 Document identifier: PCF2129A_2