INTEGRATED CIRCUITS PDI1394L11 1394 AV link layer controller Product specification 1997 Oct 21 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 1.0 FEATURES • IEEE 1394–1995 Standard Link Layer Controller • Hardware Support for the IEC61883 International Standard of designed to pack and un-pack application data packets for transmission over an IEEE 1394 bus using isochronous data transfers. Digital Interface for Consumer Electronics The application data is packetized according to the IEC 61883 International Standard of Digital Interface for Consumer Electronic Audio/Video Equipment. The AV layer interface is a byte-wide port capable of accommodating various MPEG–2 and DVC codecs. An 80C51 compatible byte-wide host interface is provided for internal register configuration as well as performing asynchronous data transfers. • Interface to any IEEE 1394–1995 Physical Layer Interface • 5V Tolerant I/Os • Single 3.3V supply voltage 2.0 DESCRIPTION The PDI1394L11 is powered by a single 3.3V power supply and the inputs and outputs are 5V tolerant. It is available in the PQFP80 package. The PDI1394L11, Philips Semiconductors 1394 Audio/Video (AV) Link Layer Controller, is an IEEE 1394–1995 compliant link layer controller featuring an embedded AV layer interface. The AV layer is 3.0 QUICK REFERENCE DATA GND = 0V; Tamb = 25°C PARAMETER SYMBOL CONDITIONS VDD Functional supply voltage range IDD Supply current @ VDD=3.3V SCLK Device clock MIN TYP MAX 3.0 3.3 3.6 20 49.147 UNIT V mA 49.152 49.157 MHz 4.0 ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 80-pin plastic PQFP80 0°C to +70°C PDI1394L11 BA PDI1394L11 BA SOT318-2 RESERVED RESERVED PHY D1 PHY D2 43 42 41 PHY CTL1 VDD GND PHY D0 44 45 ISO_N PHY CTL0 47 46 GND VDD 49 48 51 50 52 LREQ AVERR0 AVERR1 N/C 53 SCLK AVENDPCK 56 55 54 AVCLK AVSYNC 57 AVFSYNCOUT AVFSYNCIN 60 59 58 N/C AVVALID GND 61 VDD 64 63 62 5.0 PIN CONFIGURATION 65 PHY D3 VDD RESERVED 66 67 40 39 38 AV D0 68 37 GND PHY D4 AV D1 69 36 PHY D5 AV D2 AV D3 70 71 35 34 PHY D7 VDD 72 GND AV D4 AV D5 73 74 75 AV D6 AV D7 VDD_ 33 32 PDI1394L11 AV LINK LAYER CONTROLLER PHY D6 CYCLEOUT VDD 22 23 24 HIF A0 GND VDD HIF A2 HIF A1 19 20 21 17 18 HIF A4 HIF A3 16 HIF A6 HIF A5 13 VDD HIF A8 HIF A7 14 15 12 GND CLK 25 9 10 11 HIF D0 HIF D1 HIF D5 HIF D7 8 25 HIF D2 80 6 7 N/C 5 HIF RD_N GND 27 26 VDD HIF D3 HIF INT _N 78 79 GND RESET_N 28 4 29 77 HIF D4 76 1 2 3 CYCLEIN HIF D6 31 30 GND HIF WR_N HIF CS_N SV00270 1997 Oct 21 2 853-2038 18592 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 6.0 FUNCTIONAL DIAGRAM HIF A[8:0] PHY D[0:7] HIF WR_N PHY CTL[0:1] HIF RD_N LREQ HIF CS_N ISO_N PHY HOST HIF D[7:0] SCLK HIF INT_N RESET_N CYCLEIN CYCLEOUT PDI1394L11 IEEE 1394 AV LINK LAYER CONTROLLER VDD GND AV D[7:0] AV LAYER AVCLK AVVALID AVSYNC AVFSYNCIN AVFSYNCOUT AVENDPCK AVERR[1:0] SV00267 7.0 INTERNAL BLOCK DIAGRAM CYCLEOUT AV D[7:0] CYCLEIN AVCLK AVSYNC AVVALID AFSYNCIN AVFSYNCOUT AV LAYER TRANSMITTER AND RECEIVER AVENDPCK AVERR1 PHY D[0:7] 5KB BUFFER MEMORY (ISOCH & ASYNC PACKETS) LINK CORE PHY CTL[0:1] LREQ ISO_N SCLK AVERR0 HIF A[8:0] HIF D[7:0] HIF WR_N 8-BIT INTERFACE ASYNC TRANSMITTER AND RECEIVER HIF RD_N CONTROL AND STATUS REGISTERS RESET_N HIF CS_N HIF INT_N SV00269 1997 Oct 21 3 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 8.0 APPLICATION DIAGRAM MPEG OR DVC DECODER AV INTERFACE PDI1394L11 AV LINK PHY–LINK INTERFACE PDI1394P11 PHY 1394 CABLE INTERFACE DATA 8/ ADDRESS 9/ INTERRUPT & CONTROL HOST CONTROLLER SV00268 9.0 PIN DESCRIPTION 9.1 Host Interface PIN No. PIN SYMBOL I/O 14, 15, 16, 17, 18, 19, 20, 21, 22 HIF A[8:0] I 1, 2, 3, 4, 7, 8, 9, 10 HIF D[7:0] I/O NAME AND FUNCTION Host Interface Address 0 through 8. Provides the host with a byte wide interface to internal registers. See description of Host Interface for addressing rules. Host Interface Data 7 (MSB) through 0. Byte wide data path to internal registers. 26 HIF WR_N I Write enable. When asserted (LOW) in conjunction with HIF CS_N, a write to the PDI1394L11 internal registers is requested. (NOTE: HIF WR_N and HIF RD_N : if these are both LOW in conjunction with HIF CS_N, then a write cycle takes place. This can be used to connect CPUs that use R/W_N line rather than separate RD_N and WR_N lines. In that case, connect the R/W_N line to the HIF WR_N and tie HIF RD_N LOW.) 27 HIF RD_N I Read enable. When asserted (LOW) in conjunction with HIF CS_N, a read of the PDI1394L11 internal registers is requested. 25 HIF CS_N I Chip Select (active LOW). Host bus control signal to enable access to the FIFO and control and status registers. 28 HIF INT_N O Interrupt (active LOW). Indicates a interrupt internal to the PDI1394L11. Read the General Interrupt Register for more information. This pin is open drained and requires a 1K pullup resistor. I Reset (active LOW). The asynchronous master reset to the PDI1394L11. 29 RESET_N 6, 13, 24, 32, 39, 45, 49, 64, 72, 78 VDD 3.3V ± 0.3V power supply 5, 12, 23, 31, 38, 44, 50, 63, 73, 79 GND Ground reference 1997 Oct 21 4 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 9.2 AV Interface PIN No. PIN SYMBOL I/O 77, 76, 75, 74, 71, 70, 69, 68 NAME AND FUNCTION AV D[7:0] I/O 58 AVCLK I 57 AVSYNC I/O 59 AVFSYNCIN I Frame sync input. Used for Digital Video (DV). The signal is time stamped and transmitted in the SYT field of ITXHQ2. 60 AVFSYNCOUT O Frame sync output. Signal is derived from SYT field of IRXHQ2. 56 AVENDPCK I End of application packet indication from data source. Required only if input packet is not multiple of 4 bytes. It can be tied LOW for data packets that are 4*N in size. 61 AVVALID I/O Indicates data on AV D [7:0] is valid 53 AVERR0 O CRC error, indicates bus packet containing AV D [7:0] had a CRC error, the current AV packet is unreliable. 52 AVERR1 O Sequence Error. Indicates at least one source packet was lost before the current AV D [7:0] PIN SYMBOL I/O Audio/Video Data 7 (MSB) through 0. Byte-wide interface to the AV layer. External application clock. Rising edge active. Start of packet indicator; should only be used when AVVALID is active. 9.3 Phy Interface PIN No. NAME AND FUNCTION 34, 35, 36, 37, 40, 41, 42, 43 PHY D[0:7] I/O Data 0 (MSB) through 7 (NOTE: To preserve compatibility to the specified Link-Phy interface of the IEEE 1394–1995 standard, Annex J, bit 0 is the most significant bit). Data is expected on AV D[0:1] for 100Mb/s, AV D[0:3] for 200Mb/s, and AV D[0:7] for 400Mb/s. See IEEE 1394–1995 standard, Annex J for more information. 46, 47 PHY CTL[0:1] I/O Control Lines between Link and Phy. See 1394 Specification for more information. 48 ISO_N I Isolation barrier. This terminal is asserted (LOW) when an isolation barrier is present. See IEEE 1394–1995 standard, Annex J for more information (used to request arbitration or read/write PHY registers). 54 LREQ O Link Request. Bus request to access the PHY. See IEEE 1394–1995 standard, Annex J for more information. 55 SCLK I System clock. 49.152MHz input from the PHY (the PHY-LINK interface operates at this frequency). PIN No. PIN SYMBOL I/O 65, 66, 67 RESERVED NA These pins are reserved for factory testing. For normal operation they should be connected to ground. 51, 62, 80 N/C NA These are test mode pins and should not be connected or terminated. 30 CYCLEIN I Provides the capability to supply an external cycle timer signal for the beginning of 1394 bus cycles. 33 CYCLEOUT O Reproduces the 8kHz cycle clock of the cycle master. 11 CLK 25 O Auxiliary clock, value is SCLK/2 (usually 24.576 MHz) 9.4 Other Pins 1997 Oct 21 NAME AND FUNCTION 5 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 10.0 RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL VCC PARAMETER CONDITIONS DC supply voltage VI Input voltage VIH High-level input voltage VIL Low-level input voltage IOH IOL UNIT MIN MIN. MAX MAX. 3.0 3.6 V 0 5 V 2.0 V 0.8 V High-level output current 8 mA Low-level output current –8 mA dT/dV Input transition rise or fall time 0 20 ns/V Tamb Operating ambient temperature range 0 +70 °C SCLK System clock 49.147 49.157 MHz AVCLK AV interface clock 0 24 MHz tr Input rise time 10 ns tf input fall time 10 ns 11.0 ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V) LIMITS SYMBOL VDD PARAMETER CONDITIONS DC supply voltage UNIT MIN MAX –0.5 +4.6 V – –50 mA –0.5 +5.5 V – ±50 mA –0.5 VDD +0.5 V IIK DC input diode current VI DC input voltage IOK DC output diode current VO DC output voltage IO DC output source or sink current – ±50 mA DC VCC or GND current – ±150 mA –60 150 °C 0 70 °C 0.6 W IGND, ICC Tstg Storage temperature range Tamb Operating ambient temperature Ptot Power dissipation per package NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 1997 Oct 21 6 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 11.1 Buffer Memory Sizes BUFFER MEMORY SIZE (Quadlets) Asynchronous Receive Transaction Response FIFO 64 Asynchronous Receive Transaction Request FIFO 64 Asynchronous Transmit Transaction Response FIFO 64 Asynchronous Transmit Transaction Request FIFO 64 AV Transmit/Receive Buffer 1024 12.0 FUNCTIONAL DESCRIPTION 12.1 Overview packet header. This allows the AV receiver to provide the AV packet for output at the appropriate time. The PDI1394L11 is an IEEE 1394–1995 compliant link layer controller. It provides a direct interface between a 1394 bus and various MPEG–2 and DVC codecs. Via this interface, the AV Link maps and unmaps these AV datastreams from these codecs onto 1394 isochronous bus packets. The AV Link also provides an 8051 compatible microcontroller interface for an attached host controller. Through the host interface port, the host controller can configure the AV layer for transmission or reception of AV datastreams. The host interface port also allows the host controller to transmit and receive 1394 asynchronous data packets. When the DV video is enabled (via the format code of the CIP header), the frame synchronization signal AVFSYNCIN is time stamped and placed in the SYT field. The timestamp value is 3 cycle times (duration of 125ms) in the future and is transmitted in the SYT field of the current CIP header. On the receiver side, when the SYT stamp matches the cycle timer register, a pulse is generated on the AVFSYNCOUT output. The timing for AVFSYNCIN and AVFSYNCOUT are independent of AV clock. 12.2.2 IEC 61883 International Standard The PDI1394L11 is specifically designed to support the proposed IEC61883 International Standard of Digital Interface for Consumer Electronic Audio/Video Equipment. The IEC specification defines a scheme for mapping various types of AV datastreams onto 1394 isochronous data packets. The standard also defines a software protocol for managing isochronous connections in a 1394 bus called Connection Management Protocol (CMP). It also provides a framework for transfer of functional commands, called Function Control Protocol (FCP). 12.2 AV interface and AV layer The AV interface and AV layer allow AV packets to be transmitted from one node to another. The AV transmitter and receiver within the AV layer perform all the functions required to pack and unpack AV packet data for transfer over a 1394 network. Once the AV layer is properly configured for operation, no further host controller service should be required. The operation of the AV layer is half-duplex, i.e., the AV layer can either receive or transmit AV packets at a particular time. 12.2.1 The AV Interface The AV Link provides an 8 bit data path to the AV layer. The 8 bit data path is designed with associated clock and control signals to be compatible with various MPEG–2 and DVC codecs. 12.2.3 CIP Headers A feature of the IEC61883 International Standard is the definition of Common Isochronous Packet (CIP) headers. These CIP headers contain information about the source and type of datastream mapped onto the isochronous packets. The AV interface port buffer, if so programmed, can time stamp incoming AV packets. The AV packet data is stored in the embedded memory buffer, along with its time stamp information. After the AV packet has been written into the AV layer, the AV layer creates an isochronous bus packet with the appropriate CIP header. The bus packet along with the CIP header is transferred over the appropriate isochronous channel/packet. The size and configuration of isochronous data packet payload transmitted is determined by the AV layer’s configuration registers accessible through the host interface. The AV Layer supports the use of CIP headers. CIP headers are added to transmitted isochronous data packets at the AV data source. When receiving isochronous data packets, the AV layer automatically analyzes their CIP headers. The analysis of the CIP headers determines the method the AV layer uses to unpack the AV data from the isochronous data packets. The information contained in the CIP headers is accessible via registers in the host interface. (See IEC61883 International Standard of Digital Interface for Consumer Electronic Audio/Video Equipment for more details on CIP headers). The AV interface port waits for the assertion for AVVALID and AVSYNC. Note: Do not assert AVSYNC without AVVALID. AVSYNC is aligned with the rising edge of AVCLK and the first byte of data on AVDATA[7:0]. The duration of AVSYNC is one AVCLK cycle. AVSYNC signals the AV layer that the transfer of an AV packet has begun. At the time the AVSYNC is asserted, the AV layer creates a new time stamp in the buffer memory. (This only happens if so configured. The DVC format does not require these time stamps). The time stamp is then transmitted as part of the standard 1997 Oct 21 12.3 The host interface The host interface allows an 8 bit CPU to access all registers and the asynchronous packet queues. It is specifically designed for an 8051 microcontroller but can also be used with other CPUs. There are 64 register addresses (for quadlet wide registers). To access 7 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 bytes rather than quadlets the address spaces is 256 bytes, requiring 8 address lines. shadow register. During a read cycle address lines HIF A0 and HIF A1 are used to select which of the 4 bytes currently stored in the read shadow register is output onto the CPU data bus. This selection is done by combinatorial logic only, enabling external hardware to toggle these lines through values 0 to 3 while keeping the chip in a read access mode to get all 4 bytes out very fast (in a single extended read cycle), for example into an external quadlet register. The use of an 8 bit interface introduces an inherent problem that must be solved: register fields can be more than 8 bits wide and be used (control) or changed (status) at every internal clock tick. If such a field is accessed through an 8 bit interface it requires more than one read or write cycle, and the value should not change in between to maintain consistency. To overcome this problem accesses to the chip’s internal register space are always 32 bits, and the host interface must act as a converter between the internal 32 bit accesses and external 8 bit accesses. This is where the shadow registers come in. This solution requires a control line to direct the host interface to make a snapshot of an internal register when needed, as well as the internal address of the target register. The register address is connected to input address lines HIF A2..HIF A7, and the update control line to input address line HIF A8. To let the host interface take a new snapshot the target address must be presented on HIF A2..HIF A7 and HIF A8 must be raised while executing a read access. The new value will be stored in the read shadow register and the selected byte (HIF A0, HIF A1) appears on the output. 12.3.1 Read accesses To read an internal register the host interface can make a snapshot (copy) of that specific register which is then made available to the CPU 8 bits at a time. The register that holds the snapshot copy of the real register value inside the host interface is called the read TR 8 CPU MUX 32 READ SHADOW REGISTER MUX Q 32 Q REGISTERS 32 HIF A0..1 HIF A2..7 HIF A8 UPDATE/COPY CONTROL SV00803 NOTES: 1. It is not required to read all 4 bytes of a register before reading another register. For example, if only byte 2 of register 0x54 is required a read of byte address 0x100 + (0×54) + 2 = 0x156 is sufficient. 2. The update control line does not necessarily have to be connected to the CPU address line HIF A8. This input could also be controlled by other means, for example a combinatorial circuit that activates the update control line whenever a read access is done for byte 0. This makes the internal updating automatic for quadlet reading. 3. Reading the bytes of the read shadow register can be done in any order and as often as needed. 1997 Oct 21 8 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 12.3.2 Write accesses To write to an internal register the host interface must collect the 4 byte values into a 32 bit value and then write the result to the target register in a single clock tick. This requires a register to hold the 32 bit value being compiled until it is ready to be written to the actual target register. This temporary register inside the host interface is called the write shadow register. During all write cycles address lines HIF A0 and HIF A1 are used to select which of the 4 bytes of the write shadow register is to be written with the value on the CPU data bus. Only one byte can be written in a single write access cycle. This solution requires a control line to direct the host interface to copy the write shadow register to the actual destination register when ready, as well as the internal address of that register. The destination register address is connected to input address lines HIF A2..HIF A7, and the update control line to input address line HIF A8. To let the host interface make the internal transfer the target address must be presented on HIF A2..HIF A7 and HIF A8 must be raised while executing a write access. The current value on the CPU data bus will be stored in the write shadow register at the selected byte (HIF A0, HIF A1) and the result will be copied into the specified destination register. MUX 8 CPU WRITE SHADOW REGISTER TR MUX Q 32 Q REGISTERS 32 HIF A0..1 HIF A2..7 HIF A8 UPDATE/COPY CONTROL SV00804 NOTES: 1. It is not required to write all 4 bytes of a register: those bytes that are either reserved (undefined) or don’t care do not have to be written in which case they will be assigned the value that was left in the corresponding byte of the write shadow register from a previous write access. For example, to acknowledge an interrupt for the isochronous receiver (external address 0x04C), a single byte write to location 0x100+(0x4C)+3 = 0x14F is sufficient. The value 256 represents setting HIF A8=1. The host interface cannot directly access the FIFOs, but instead reads from/writes into a transfer register (shown as TR in the Figures above). Data is moved between FIFO and TR by internal logic as soon as possible without CPU intervention. 2. The update control line does not necessarily have to be connected to the CPU address line HIF A8. This input could also be controlled by other means, for example a combinatorial circuit that activates the update control line whenever a write access is done for byte 3. This makes the internal updating automatic for quadlet writing. 3. Writing the bytes of the read shadow register can be done in any order and as often as needed (new writes simply overwrite the old value). 1997 Oct 21 9 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 12.3.3 Byte order The bytes in each quadlet are numbered 0..3 from left (most significant) to right (least significant) as shown in Figure 1. To access a register at internal address N the CPU should use addresses E: E=4N ; to access the upper 8 bits of the register. E=4N+1 ; to access the upper middle 8 bits of the register. E=4N+2 ; to access the lower middle 8 bits of the register. E=4N+3 ; to access the lower 8 bits of the register. register. Once the data is copied into the read shadow register it is no longer available in the queue itself so the CPU should always read all 4 bytes before attempting any other read access (be careful with interrupt handlers for AVLink!). A similar argument applies to the transmitter queues. Data cannot be written arbitrarily, but only to the next available free location. Since the transmitter needs to know when the packet is complete (all data stored in memory, so that it may start the arbitration process on the 1394 bus) two separate register locations are reserved per transmitter queue: one to write all but the last packet quadlet to, and one to write the last quadlet of every packet to. Writing to any of these register locations stores the data in the queue and makes the next memory location accessible for writing. 12.3.4 Accessing the packet queues Although entire incoming packets are stored in the receiver buffer memory they are not randomly accessible. These buffers act like fifos and only the frontmost (oldest) data quadlet entry is accessible for reading. Therefore only one location (register address) is allocated to each of the two receiver queues. Reading this location returns the head entry of the queue, and at the same time removes it from the queue, making the next stored data quadlet accessible. NOTE: 1. Because of the way it is implemented memory access is not always immediate; consequently it may take some time before the next data quadlet in the queue is accessible after reading or writing the current one. Status flags are provided to the CPU to indicate availability. With the current host interface such a read is in fact a move operation of the data quadlet from the queue to the read shadow 3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BYTE 0 BYTE 1 BYTE 2 BYTE 3 SV00656 Figure 1. Byte order in quadlets as implemented in the host interface 12.3.5 The CPU bus interface signals The CPU interface is directly compatible with an 8051 microcontroller. It uses a separate HIF RD_N and HIF WR_N inputs and a HIF CS_N chip select line, all of which are active LOW. There are 9 address inputs (HIF A0..HIF A8) and 8 data in/out lines HIF D0..HIF D7. An open drain HIF INT_N output is used to signal interrupts to the CPU. Very shortly after the start of the cycle, the selected byte in the read shadow register will be output (indicated in Figure 2 as RSRO). If HIF A8 is asserted then the target register value will be copied into the read shadow register, leading to a new value RSRn some time later in the read cycle. If HIF A8 is LOW, then the read shadow register will not change. A write access starts when the later of HIF CS_N and HIF WR_N becomes LOW (see Figure 3). Data is written to the shadow register, following which, if HIF A8 is asserted, the shadow register value is copied to the addressed register. The CPU is not required to run at a clock that is synchronous to the 1394 base clock. The control signals will be resampled by the host interface before being used internally. An access through the host interface starts when HIF CS_N = 0 and either HIF WR_N = 0 or HIF RD_N = 0. Typically the chip select signal is derived from the upper address lines of the CPU (address decode stage), but it could also be connected to a port pin of the CPU to avoid the need for an external address decoder in very simple CPU systems. When both HIF CS_N = 0 and HIF RD_N = 0 the host interface will start a read access cycle, so the cycle is triggered at the falling edge of either HIF CS_N or HIF RD_N, whichever is later. 1997 Oct 21 NOTES: 1. The time between the end of any access and the start of the next access must be at least tCH which needs to be greater than (2 x SCLK). 2. When HIF A8 = 0 for either write or read access the address bits HIF A2..HIF A7 are ignored. 3. If both HIF WR_N = 0 and HIF RD_N = 0 while HIF CS_N = 0, then a write cycle takes place. 10 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 HIF CS_N TAS HIF RD_N TAS HIF WR_N HIF A8 HIF A0..HIF A7 TACC TACC HIF D0..HIF D7 RSRO RSRn RSRn SV00686 Figure 2. Read cycle signal timing (2 independent read cycles) HIF CS_N TAS HIF RD_N HIF WR_N TAS HIF A0..HIF A8 HIF D0..HIF D7 <VALID ADDRESS> <VALID ADDRESS> <WRITE DATA> <WRITE DATA> SV00687 Figure 3. Write cycle signal timing (2 independent write cycles) 12.4.2 Writing an Asynchronous Packet An asynchronous packet intended for transmission is first stored in the appropriate Transmitter FIFO. Once writing to the FIFO is complete, the link layer controller arbitrates for the bus to transmit the packet. 12.4 The Asynchronous Packet Interface The PDI1394L11 provides an interface to asynchronous data packets through the registers in the host interface. The format of the asynchronous packets is specified in the following sections. 12.4.1 Reading an Asynchronous Packet Upon reception of a packet, the packet data is stored in the appropriate receive FIFO, either the Request or Response FIFO. The location of the packet is indicated by either the RREQQQAV or RRSPQAV status bit being set in the Asynchronous Interrupt Acknowledge (ASYINTACK) register. The packet is transferred out of the FIFO by successive reads of the Asynchronous Receive Request (RREQ) or Asynchronous Receive Response (RRSP) register. The end of the packet (the last quadlet) is indicated by either the RREQQLASTQ or RRSPQLASTQ bit set in ASYINTACK. Attempting to read the FIFO when either RREQQQAV bit or RRSPQQAV bit is set to 0 (in the Asynchronous RX/TX interrupt acknowledge (ASYINTACK) register) will result in a queue read error. 1997 Oct 21 To generate an asynchronous packet, the first and next to last quadlets of the packet must be written to the Asynchronous Transmit Request Next (TX_RQ_NEXT) register, for request type packets, or the Asynchronous Transmit Response Next (TX_RP_NEXT) register, for response type packets. The last quadlet of the packet is written to the Asynchronous Transmit Request Last (TX_RQ_LAST) register, for request type packets, or the Asynchronous Transmit Response Last (TX_RP_LAST) register, for response type packets. After writing the last quadlet, the packet is automatically queued by the AVlink layer controller for transmission over the bus. 11 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 12.5 Link Packet Data Formats The data formats for transmission and reception of data are shown below. The transmit format describes the expected organization for data presented to the link at the asynchronous transmit, physical response, or isochronous transmit FIFO interfaces. 12.5.1 Asynchronous Transmit Packet Formats These sections describe the formats in which packets need to be delivered to the queues (FIFOs) for transmission. There are four basic formats as follows: ITEM 1 2 3 4 FORMAT TRANSACTION CODE (tCode) USAGE Quadlet read requests 4 Quadlet/block write responses 2 Qaudlet write requests 0 Quadlet read responses 6 Block read requests 5 Block write requests 1 Block read responses 7 Lock requests 9 No packet data No-packet Quadlet packet Block Packet Unformatted transmit Lock responses Bhex Concatenated self-ID / PHY packets Ehex Each packet format uses several fields (see names and descriptions below). More information about these fields (not the format) can be found in the 1394 specification. Grey fields are reserved and should be set to zero values. 12.5.1.1 No-data Transmit The no-data transmit formats are shown in Figures 4 and 5. The first quadlet contains packet control information. The second and third quadlets contain 16-bit destination ID and either the 48-bit, quadlet aligned destination offset (for requests) or the response code (for responses). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 spd tLabel destinationID rt tCode 0000 destinationOffsetHigh destinationOffsetLow SV00250 Figure 4. Quadlet Read Request Transmit Format 1997 Oct 21 12 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 spd destinationID tLabel rt tCode 0000 rCode SV00249 Figure 5. Quadlet/Block Write Response Packet Transmit Format Table 1. No-Data Transmit Format Field Name Description spd This field indicates the speed at which this packet is to be sent. 00=100 Mbs, 01=200 Mbs, and 10=400 Mbs. 11 = undefined tLabel This field is the transaction label, which is used to pair up a response packet with its corresponding request packet. rt The retry code for this packet. Supported values are: 00=retry1, and 01=retryX. tCode The transaction code for this packet. DestinationID Contains a node ID value. DestinationOffsetHigh DestinationOffsetLow The concatenation of these two field addresses a quadlet in the destination node’s address space. rCode Response code for write response packet. 12.5.1.2 Quadlet Transmit Three quadlet transmit formats are shown below. In these figures: The first quadlet contains packet control information. The second and third quadlets contain 16-bit destination ID and either the 48-bit quadlet-aligned destination offset (for requests) or the response code (for responses). The fourth quadlet contains the quadlet data for read response and write quadlet request formats, or the upper 16 bits contain the data length for the block read request format. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 spd tLabel destinationID rt tCode 0000 destinationOffsetHigh destinationOffsetLow quadlet data SV00251 Figure 6. Quadlet Write Request Transmit Format 1997 Oct 21 13 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 spd tLabel destinationID rt tCode 0000 rCode quadlet data SV00252 Figure 7. Quadlet Read Response Transmit Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 spd tLabel destinationID rt tCode 0000 destinationOffsetHigh destinationOffsetLow data length SV00253 Figure 8. Block Read Request Transmit Format Table 2. Quadlet Transmit Fields Field Name Description spd, tLabel, rt, tCode, destinationID, destinationOffsetHigh, destinationOffsetLow, rCode See Table 1. Quadlet data For quadlet write requests and quadlet read responses, this field holds the data to be transferred Data length The number of bytes requested in a block read request 1997 Oct 21 14 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 12.5.1.3 Block Transmit The block transmit format is shown below, this is the generic format for reads and writes. The first quadlet contains packet control information. The second and third quadlets contain the 16-bit destination node ID and either the 48-bit destination offset (for requests) or the response code and reserved data (for responses). The fourth quadlet contains the length of the data field and the extended transaction code (all zeros except for lock transaction). The block data, if any, follows the extended transaction code. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 spd tLabel rt tCode 0000 destinationOffsetHigh destinationID destinationOffsetLow dataLength extendedTcode Block data padding (if needed) SV00254 Figure 9. Block Packet Transmit Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 spd destinationID tLabel rt tCode 0000 rCode dataLength extendedTcode Block data padding (if needed) SV00255 Figure 10. Block Read or Lock Response Transmit Format 1997 Oct 21 15 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 Table 3. Block Transmit Field Field Name Description spd, tLabel, rt, tCode, destinationID, destinationOffsetHigh, destinationOffsetLow, rCode See Table 2. dataLength The number of bytes of data to be transmitted in this packet extendedTcode The tCode indicates a lock transaction, this specifies the actual lock action to be performed with the data in this packet. block data The data to be sent. If dataLength=0, no data should be written into the FIFO for this field. Regardless of the destination or source alignment of the data, the first byte of the block must appear in the high order byte of the first quadlet. padding If the dataLength mod 4 is not zero, then zero–value bytes are added onto the end of the packet to guarantee that a whole number of quadlets is sent. 12.5.1.4 Unformatted Transmit The unformatted transmit format is shown in Figure 11. The first quadlet contains packet control information. The remaining quadlets contain data that is transmitted without any formatting on the bus. No CRC is appended on the packet, nor is any data in the first quadlet sent. This is used to send PHY configuration and Link-on packets. Note that the bit-inverted check quadlet must be included in the FIFO since the AV Link core will not generate it. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spd tLabel 1110 0000 unformatted packet data SV00256 Figure 11. Unformatted Transmit Format 12.5.2 Asynchronous Receive Packet Formats This section describes the asynchronous receive packet formats. Four basic asynchronous data packet formats and one confirmation format exist: Table 4. Asynchronous Data Packet Formats ITEM FORMAT 1 No packet data No-packet 2 Quadlet packet 3 Block Packet USAGE TRANSACTION CODE Quadlet read requests 4 Quadlet/block write responses 2 Qaudlet write requests 0 Quadlet read responses 6 Block read requests 5 Block write requests 1 Block read responses 7 Lock requests 9 Lock responses Bhex 4 Self-ID / PHY packet Concatenated self-ID / PHY packets Ehex 5 Confirmation packet Confirmation of packet transmission 8 Each packet format uses several fields. More information about most of these fields can be found in the 1394 specification. 1997 Oct 21 16 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 Table 5. Asynchronous Receive Fields Field Name Description destinationID This field is the concatenation of busNumbers (or all ones for “local bus”) and nodeNumbers (or all ones for broadcast) for this node. tLabel This field is the transaction label, which is used to pair up a response packet with its corresponding request packet. rt The retry code for this packet. 00=retry1, 01=retryX, 10=retryA, 11=retryB. tCode The transaction code for this packet. priority The priority level for this packet (0000 for cable environment). sourceID This is the node ID of the sender of this packet. destinationOffsetHigh, destinationOffsetLow The concatenation of these two field addresses a quadlet in this node’s address space. rCode Response code for response packets. quadlet data For quadlet write requests and quadlet read responses, this field holds the data received. dataLength The number of bytes of data to be received in a block packet. extendedTcode If the tCode indicates a lock transaction, this specifies the actual lock action to be performed with the data in this packet. block data The data received. If dataLength=0, no data will be written into the FIFO for this field. Regardless of the destination or source alignment of the data, the first byte of the block will appear in the high order byte of the first quadlet. padding If the dataLength mod 4 is not zero, then zero–value bytes are added onto the end of the packet to guarantee that a whole number of quadlets is sent. u Unsolicited response tag bit. This bit is set to one (1) if the received response was unsolicited. ackSent This field contains the acknowledge code that the link layer returned to the sender of the received packet. For packets that do not need to be acknowledged (such as broadcasts) the field contains the acknowledge value that would have been sent if an acknowledge had been required. The values for this field are listed in Table 6 (they also can be found in the IEEE 1394 standard). Table 6. Acknowledge codes Code Name Description 0001 ack_complete The node has successfully accepted the packet. If the packet was a request subaction, the destination node has successfully completed the transaction and no response subaction shall follow. 0010 ack_pending The node has successfully accepted the packet. If the packet was a request subaction, a response subaction will follow at a later time. This code shall not be returned for a response subaction. 0100 ack_busy_X The packet could not be accepted. The destination transaction layer may accept the packet on a retry of the subaction. 0101 ack_busy_A The packet could not be accepted. The destination transaction layer will accept the packet when the node is not busy during the next occurrence of retry phase A. 0110 ack_busy_B The packet could not be accepted. The destination transaction layer will accept the packet when the node is not busy during the next occurrence of retry phase B. 1101 ack_data_error The node could not accept the block packet because the data field failed the CRC check, or because the length of the data block payload did not match the length contained in the dataLength field. This code shall not be returned for any packet that does not have a data block payload. 1110 ack_type_error A field in the request packet header was set to an unsupported or incorrect value, or an invalid transaction was attempted (e.g., a write to a read-only address). 0000, 0011, 0111 – 1100, and 1111 1997 Oct 21 reserved 17 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 12.5.2.1 No-Data Receive The no-data receive formats are shown below. The first quadlet contains the destination node ID and the rest of the packet header. The second and third quadlet contain 16-bit source ID and either the 48-bit, quadlet-aligned destination offset (for requests) or the response code (for responses). The last quadlet contains packet reception status. 3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 destinationID tLabel rt tCode priority destinationOffsetHigh sourceID destinationOffsetLow spd ackSent SV00257 Figure 12. Quadlet Read Request Receive Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 destinationID tLabel sourceID rt tCode priority rCode spd u ackSent SV00258 Figure 13. Write Response Receive Format 12.5.2.2 Quadlet Receive The quadlet receive formats are shown below. The first quadlet contains the destination node ID and the rest of the packet header. The second and third quadlets contain 16-bit source ID and either the 48-bit, quadlet-aligned destination offset (for requests) or the response code (for responses). The fourth quadlet is the quadlet data for read responses and write quadlet requests, and is the data length and reserved for block read requests. The last quadlet contains packet reception status. 1997 Oct 21 18 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 destinationID tLabel rt tCode priority destinationOffsetHigh sourceID destinationOffsetLow quadlet data spd ackSent SV00259 Figure 14. Quadlet Write Request Receive Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 destinationID tLabel sourceID rt tCode priority rCode quadlet data spd u ackSent SV00260 Figure 15. Quadlet Read Response Receive Format 1997 Oct 21 19 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 destinationID tLabel rt tCode priority destinationOffsetHigh sourceID destinationOffsetLow data length spd ackSent SV00261 Figure 16. Block Read Request Receive Format 12.5.2.3 Block receive The block receive format is shown below. The first quadlet contains the destination node ID and the rest of the packet header. The second and third quadlets contain 16-bit sourceID and either the 48-bit destination offset (for requests) or the response code and reserved data (for responses). The fourth quadlet contains the length of the data field and the extended transaction code (all zeros except for lock transactions). The block data, if any, follows the extended code. The last quadlet contains packet reception status. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 destinationID tLabel sourceID rt tCode priority destinationOffsetHigh destinationOffsetLow dataLength extendedTcode Block data padding (if needed) spd ackSent SV00262 Figure 17. Block Write or Lock Request Receive Format 1997 Oct 21 20 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 destinationID tLabel sourceID rt tCode priority rCode dataLength extendedTcode Block data padding (if needed) spd u ackSent SV00263 Figure 18. Block Read or Lock Response Receive Format 12.5.2.4 Self-ID and PHY packets receive The self-ID and PHY packet receive formats are shown below. The first quadlet contains a synthesized packet header with a tCode of 0xE (hex). For self-ID information, the remaining quadlets contain data that is received from the time a bus reset ends to the first subaction gap. This is the concatenation of all the self-ID packets received. Note that the bit-inverted check quadlet is included in the Read Request FIFO and the application must check it. 3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 11102 00002 self ID packet data 00 ackSent SV00264 Figure 19. Self-ID Receive Format The “ackSent” field will either be “ACK_DATA_ERROR” if a non-quadlet-aligned packet is received or there was a data overrun, or “ACK_COMPLETE” if the entire string of self-ID packets was received. 1997 Oct 21 21 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 11102 00002 PHY packet first quadlet SV00265 Figure 20. PHY Packet Receive Format For PHY packets, there is a single following quadlet which is the first quadlet of the PHY packet. The check quadlet has already been verified and is not included. 12.5.2.5 Transaction data confirmation formats After a packet from one of the queues has been transmitted, the asynchronous transmitter assembles a confirmation (see Figure 21) which is used to confirm the result of the transmission to the higher layers. Separate confirmations are assembled for request and response transmissions. Request confirmations are written into the request queue and response confirmations are written into the response queue. 3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 destinationID tLabel 002 10002 conf SV00821 Figure 21. Request and response confirmation format Table 7. Confirmation codes CODE1 DESCRIPTION 0 Non-broadcast packet transmitted; addressed node returned no acknowledge. 1 Broadcast packet transmitted or non-broadcast packet transmitted; addressed node returned an acknowledge complete. 2 Non-broadcast packet transmited; addressed node returned an acknowledge pending. 4 Retry limit exceeded; destination node hasn’t accepted the non-broadcast packet within the maximum number of retries. D16 Acknowledge data error received (transaction complete). E16 Acknowledge type error received (transaction complete). NOTE: 1. All other codes are reserved. For every packet written in a transmitter queue by the CPU, there will be one confirmation written in the corresponding receiver queue by the AV layer logic. 12.5.3 Interrupts The PDI1394L11 provides a single interrupt line (HIF INT_N) for connection to a host controller. Status indications from four major areas of the device are collected and ORed together to activate HIF INT_N. Status from four major areas of the device are collected in four status registers; LNKPHYINTACK, ITXINTACK, IRXINTACK, and ASYINTACK. At this level, each individual status can be enabled to generate a chip-level interrupt by activating HIF INT_N. To aid in determining the source of a chip-level interrupt, the major area of the device generating an interrupt is indicated in the lower 4 bits of the GLOBCSR register. These bits are non-latching Read-Only status bits and do not need to be acknowledged. To acknowledge and clear a standing interrupt, the bit in LNKPHYINTACK, ITXINTACK, IRXINTACK, or ASYINTACK causing the interrupt status has to be written to a logic ‘1’; Note: Writing a value of ‘0’ to the bit has no effect. 1997 Oct 21 22 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 12.5.3.1 Determining and Clearing Interrupts When responding to an interrupt event generated by the PDI1394L11, or operating in polled mode, the first register examined is the GLOBCSR register. The least significant nibble contains interrupt status bits from general sections of the device; the link layer controller, the AV transmitter, the AV receiver, and the asynchronous transceiver. The bits in GLOBCSR[3:0] are self clearing status bits. They represent the logical OR of all the enabled interrupt status bits in their section of the AV Link Layer Controller. Once an interrupt, or status is detected in GLOBCSR, the appropriate interrupt status register needs to be read, see the Interrupt Hierarchy diagram for more detail. After all the interrupt indications are dealt with in the appropriate interrupt status register, the interrupt status indication will automatically clear in the GLOBCSR. All interrupt status bits in the various interrupt status registers are latching unless otherwise noted. 12.5.3.2 Interrupt Hierarchy HIF INT_N ASYTx/Rx ITXINT IRXINT LNKPHYINT 3 2 1 0 GLOBCSR (0x018) TCERR CYTMOUT CYSEC CYSTART CYDONE CYPEND CYLOST PHYRST TxRDY RxDATA ITBADFMT ATBADFMT SNT_REJ HDRERR CMDRST FAIRGAP ARBGAP PHYINT PHYRRX 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LNKPHYINTACK (0x008) CIPTAGFLT RCVBP SQOV IRXFULL IRXEMPTY FSYNC SEQERR CRCERR 7 6 5 4 3 2 1 0 IRXINTACK (0x04C) ITXFULL ITXEMPTY TRMSYT TRMBP DBCERR INPERR DISCARD 6 5 4 3 2 1 0 ITXINTACK (0x02C) RRSPQFULL RREQQFULL SIDQAV RRSPQLASTQ RREQQLASTQ RRSPQRDERR RREQQRDERR RRSPQQAV RREQQQAV TIMEOUT RCVDRSP TRSPQFULL TREQQFULL TRSPQWRERR TREQQWRERR TRSPQWR TREQQWR 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ASYINTACK (0x0A0) SV00271 1997 Oct 21 23 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 13.0 REGISTER MAP Registers are 32 bits (quadlet) wide and all accesses are always done on a quadlet basis. This means that it is not possible to write just the lower 8 bits, and leave the other bits unaffected (see Section 12.3.2 for more information). The values written to undefined fields/bits are ignored and thus DON’T CARE. A full bitmap of all registers is listed in Table 8. The meaning of shading and bit cell values is as follows: A bit/field with no name written in it and dark shading is reserved and not used. A bit/field with a name in it and light shading is a READ ONLY (status) bit/field. A one bit value (0 or 1) written at the bottom of a writable (control) bit is the default value after power-on-reset. Table 8. Full Bitmap of all Registers (consists of three tables shown on the following pages) 1997 Oct 21 24 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 24 31 23 16 15 8 7 0 REGISTER ADDRESS IDREG BUS ID VERSION_CODE VERSION CODE NODE ID ROOT BUSYFLAG CYSEC CYSTART CYCLE_NUMBER CYLOST 0 0 ECYLOST 0 CYDONE 0 CYPEND 0 0 ECYPEND 0 0 ECYDONE 0 0 ECYSTART 0 0 ETCERR CYTMOUT TCERR 0 ECYTMOUT SNT_REJ HDRERR CYSOURCE CYTMREN 0 EHDRERR CYMASTER 0 ESNT_REJ 0 ATBADFMT 0 0 EATBADFMT 0 0 ITBADFMT 0 0 0 EITBADFMT ETXRDY STRICTISOCH 0 0 RxDATA 0 0 ERXDATA PHYRST TxRDY 0 EPHYRST 0 0 0 ATACK ECYSEC CYCLE_SECONDS CYCTM 0 0 PHYINT 0x00C 0 PHYRRX LNKPHYINTE 0 0 EPHYINT 0x008 0 EPHYRRX LNKPHYINTACK FAIRGAP 0 ARBGAP 0 EARBGAP 1 CMDRST 1 ECMDRST 0 EFAIRGAP 0 RST Tx 0 RST Rx 1 RxENABLE 0 BSYCTRL TxENABLE IDVALID LNKCTL 0x004 RCVSELFID 0x000 0 0 0 0 0 0 0 0 0 CYCLE_OFFSET PHYRGAD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PHYRXAD PHYRGDATA 0 0 0 GLOBCSR 0x018 0 PHYRXDATA 0 1 0 0 0 0 LNKIPHYINT 0 IRXINT 0 ITXINT 0 ASYITX/RX 0 ELNKPHYINT 0 EIRXINT 0 EITXINT 0 0 EASYTX/RX 0 0 TXMODE 0x014 0 WRPHY PHYACS 0 RDPHY 0x010 <RESERVED> MAXBL 0x020 0 0 0 0 0 0 ITXHQ1 0x024 0 0 0 0 0 0 DBS 0 0 ITXHQ2 0 FMT 0 0 0 0 FN 0 0 0 0 0 0 0 0 0 0 QPC 0 0 0 0 0 0 0 1 0 0 0 0 0 0 PM SPH 0 RST_ITX TRDEL EN_ITX ITXPKCTL EN_FS 0x01C FDF SYT 0x028 0 0 0 0 0 0 0 0 0 0 ITXEMPTY 0 0 0 0 0 0 0 0 EITXEMPTY 0 ITXFULL 0 EITXFULL 0 INPERR 0 DISCARD 0 EDISCARD 0 EINPERR 0 0 DBCERR 0 EDBCERR 0 ITXINTACK 0x02C ITXINTE 0x030 0 0 0 0 0 TRMBP 0 TRMSYT 0 ETRMBP 0 ETRMSYT 0 0 0 SV00799 1997 Oct 21 25 Philips Semiconductors Product specification 1394 AV link layer controller 31 REGISTER ADDRESS 24 PDI1394L11 23 16 ITXCTL 15 8 TAG 7 0 SPD CHANNEL SYNC 0 0 0 0 0 0 ITXMEM 0x038 0 0 0 0 ITXME 0 ITXM5AV 0 ITXMF 0 ITXMAF 0 SPAV 0x034 <RESERVED> 1 F0 SID DBS FN 0 0 0 0 1 SPH E0 F1 0x044 E1 IRXHQ1 BPAD EN_FS 0x040 RST_IRX IRXPKCTL EN_IRX RMVUAP 0x03C QPC IRXHQ2 IRXCTL SPD TAG CHANNEL SEQERR CRCERR CIPTAGFLT RCVBP SQOV 0 0 0 0 0 0 0 ECRCERR ECIPTAGFLT ERCVBP ESQOV 0x050 0 ESEQERR IRXINTE FSYNC 0x04C EFSYNC IRXINTACK IRXFULL SYT IRXEMPTY FDF EIRXFULL FMT EIRXEMPTY 0x048 0 0 0 0 0 0 0 0 ERR SYNC 0x054 0 0 0 0 0x058 IRXM5AV 0 IRXME 0 IRXMF IRXMEM 0 IRXMAF 0 <RESERVED> 0x05C . . . <RESERVED> 0x07C SV00800 1997 Oct 21 26 Philips Semiconductors Product specification 1394 AV link layer controller TREQQAF TREQQ5AV TREQQE TREQQWR 0 0 0 0 0 ETREQQWR 0 TRSPQWR 0 TREQQWRERR TRSPQE TREQQF 0 ETRSPQWR 0 ETREQQWRERR 0 TRSPQWRERR 0 1 TREQQFULL 0 ETRSPQWRERR 1 TRSPQAF 1 TRSPQ5AV 0 RREQQE 0 TRSPQF 0 RREQQAF 0 RREQQ5AV 0 RRSPQE 0 RREQQF 0 0 TOF RRSPQ5AV 0 RRSPQF 0 RRSPQAF 0 TREQQIDLE 1 7 ETREQQFULL TX_RQ_NEXT 1 8 TOS CMDRST 0x084 0 15 MAXRC TRSPQIDLE ASYMEM 16 ATXRST 0x080 23 ARXALL ASYCTL 24 ARXRST 31 REGISTER ADDRESS PDI1394L11 0 0 0 0 0 FIRST/MIDDLE QUADLET OF PACKET FOR TRANSMITTER REQUEST QUEUE (WRITE ONLY) 0x088 TX_RQ_LAST 0x08C TX_RP_NEXT LAST QUADLET OF PACKET FOR TRANSMITTER REQUEST QUEUE (WRITE ONLY) FIRST/MIDDLE QUADLET OF PACKET FOR TRANSMITTER RESPONSE QUEUE (WRITE ONLY) 0x090 TX_RP_LAST LAST QUADLET OF PACKET FOR TRANSMITTER RESPONSE QUEUE (WRITE ONLY) 0x094 RREQ QUADLET OF PACKET FROM RECEIVER REQUEST QUEUE (TRANSFER REGISTER) 0x098 RRSP QUADLET OF PACKET FROM RECEIVER RESPONSE QUEUE (TRANSFER REGISTER) RCVDRSP TRSPQFULL 0 0 0 0 0 0 ETRSPQFULL 0 ERCVDRSP 0 TIMEOUT 0 RREQQQAV 0 0 ETIMEOUT RRSPQQAV 0 ERREQQQAV RREQQRDERR 0 0 ERRSPQQAV 0 0 ERREQQRDERR 0 RRSPQRDERR 0 ERRSPQRDERR RRSPQLASTQ RREQQLASTQ 0 0 ERRSPQLASTQ 0 0 ERREQQLASTQ 0 SIDQAV 0 ESIDQAV 0x0A4 RRSPQFULL ASYINTE RREQQFULL 0x0A0 ERRSPQFULL ASYINTACK ERREQQFULL 0x09C <RESERVED> 0x0A8 . . . <RESERVED> 0x0F8 SV00801 1997 Oct 21 27 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 13.1 Link Control Registers 13.1.1 ID Register (IDREG) – Base Address: 0x000 The ID register is automatically updated by the attached PHY with the proper Node ID after completion of the bus reset. 3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BUS ID NODE ID VERSION_CODE SV00272 Reset Value 0xFFFF0002 Bit 31..22: R/W Bus ID:The 10-bit bus number that is used with the Node ID in the source address for outgoing packets and used to accept or reject incoming packets. This field reverts to all ‘1’s (0x3FF) upon bus reset. Bit 21..16: R/W Node ID: Used in conjunction with Bus ID in the source address for outgoing packets and used to accept or reject incoming packets. This register auto-updates with the node ID assigned after the 1394 bus Tree-ID sequence. Bit 15..0: R Version_Code: Version of the PDI1394L11 13.1.2 General Link Control (LNKCTL) – Base Address: 0x004 The General Link control register is used to program the Link Layer isochronous transceiver, as well as the overall link transceiver. It also provides general link status. BUSYFLAG ROOT CYMASTER CYSOURCE CYTMREN STRICTISOCH RST Tx RST Rx RxENABLE BSYCTRL TxENABLE RCVSELFID IDVALID 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ATACK SV00273 Reset Value 0x46000000 Bit 31: R/W ID Valid: When equal to one, the PDI1394L11 accepts the packets addressed to this node. This bit is automatically set after selfID complete and node ID is updated. Bit 30: R/W Receive Self ID: When asserted, the self-identification packets, generated by each PHY device on the bus, during bus initialization are received and placed into the asynchronous request queue as a single packet. Bit 29..27: R/W Busy Control: These bits control what busy status the chip returns to incoming packets. The field is defined below: 000 = use protocol requested by received packet (either dual phase or single phase) 001 = send busy A when it is necessary to send a busy acknowledge (testing/diagnostics) 010 = send a busy B when it is necessary to send a busy acknowledge (testing/diagnostics) 011 = use single phase retry protocol 100 = use protocol requested in packet, always send a busy ack (for all packets) 101 = busy A all incoming packets 110 = busy B all incoming packets are ‘1’ 111 = use single phase retry protocol, always send a busy ack Bit 26: R/W Transmitter Enable: When this bit is set, the link layer transmitter will arbitrate and send packets. Bit 25: R/W Receiver Enable: When this bit is set, the link layer receiver will receive and respond to bus packets. Bit 21: R/W Reset Transmitter: When set to one, this synchronously resets the transmitter within the link layer. Bit 20: R/W Reset Receiver: When set to one, this synchronously resets the receiver within the link layer. Bit 12: R/W Strict Isochronous: Used to accept or reject isochronous packets sent outside of specified isochronous cycles (between a Cycle Start and subaction gap). A ‘1’ rejects packets sent outside the specified cycles, a “0” accepts isochronous packets sent outside the specified cycle. Bit 11: R/W Cycle Master: When asserted and the PDI1394L11 is attached to the root PHY (ROOT bit = 1), and the cycle_count field of the cycle timer register increments, the transmitter sends a cycle-start packet. Cycle Master function will be disabled if a cycle timeout is detected (CYTMOUT bit 5 in LNKPHYINTACK). To restart the Cycle Master function in such a case, first reset CYMASTER, then set it again. 1997 Oct 21 28 Philips Semiconductors Product specification 1394 AV link layer controller Bit 10: R/W Bit 9: Bit 5: Bit 4: R/W R R Bit 3..0: R PDI1394L11 Cycle Source: When asserted, the cycle_count field increments and the cycle_offset field resets for each positive transition of CYCLEIN. When deasserted, the cycle count field increments when the cycle_offset field rolls over. Cycle Timer Enable: When asserted, the cycle offset field increments. Root: Indicates this device is the root on the bus. This automatically updates after the self_ID phase. Busy Flag: The type of busy acknowledge which will be sent next time an acknowledge is required. 0 = Busy A, 1 = Busy B (only meaningful during a dual-phase busy/retry operation). AT acknowledge received: The last acknowledge received by the transmitter in response to a packet sent from the transmit-FIFO interface while the ATF is selected (diagnostic purposes). 13.1.3 Link /Phy Interrupt Acknowledge (LNKPHYINTACK) – Base Address: 0x008 The Link/Phy Interrupt Acknowledge register indicates various status and error conditions in the Link and Phy which can be programmed to generate an interrupt. The interrupt enable register (LNKPHYINTE) is a mirror of this register. Acknowledgment of an interrupt is accomplished by writing a ‘1’ to a bit in this register that is set. This action reset the bit indication to a ‘0’. Writing a ‘1’ to a bit that is already “0” will have no effect on the register. CMDRST FAIRGAP ARBGAP PHYINT PHYRRX PHYRST TxRDY RxDATA ITBADFMT ATBADFMT SNT_REJ HDRERR TCERR CYTMOUT CYSEC CYSTART CYDONE CYPEND CYLOST 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SV00274 Reset Value 0x00000000 Bit 18: R/W Command Reset Received: A write request to RESET-START has been received. Bit 17: R/W Fair Gap: The serial bus has been idle for a fair-gap time (called subaction gap in the IEEE 1394 specification). Bit 16: R/W Arbitration Reset Gap: The serial bus has been idle for an arbitration reset gap. Bit 15: R/W Phy Chip Int: The Phy chip has signaled an interrupt through the Phy interface. Bit 14: R/W Phy Register Information Received: A register has been transferred by the Physical Layer device into the Link. Bit 13: R/W Phy Reset Started: A Phy-layer reconfiguration has started. This interrupt clears the ID valid bit. (Called Bus Reset in the IEEE 1394 specification). Bit 12: R/W Transmitter Ready: The transmitter is idle and ready. Bit 11: R/W Receiver has Data: The receiver has confirmed data to the receiver response/request FIFO. Used for diagnostic purposes only. Bit 10: R/W Isochronous Transmitter is Stuck: The transmitter has detected invalid data at the transmit-FIFO interface when the ITF is selected. Bit 9: R/W Asynchronous Transmitter is Stuck: The transmitter expected start of new async packet in queue, but found other data (out of sync with user). Reset to clear. Bit 8: R/W Busy Acknowledge Sent by Receiver: The receiver was forced to send a busy acknowledge to a packet addressed to this node because the receiver response/request FIFO overflowed. Bit 7: R/W Header Error: The receiver detected a header CRC error on an incoming packet that may have been addressed to this node. Bit 6: R/W Transaction Code Error: The transmitter detected an invalid transaction code in the data at the transmit FIFO interface. Bit 5: R/W Cycle Timed Out. ISOCH cycle lasted more than 125µs from Cycle-Start to Fair Gap: Disables cycle master function Bit 4: R/W Cycle Second incremented: The cycle second field in the cycle-timer register incremented. This occurs approximately every second when the cycle timer is enabled. Bit 3: R/W Cycle Started: The transmitter has sent or the receiver has received a cycle start packet. Bit 2: R/W Cycle Done: A fair gap has been detected on the bus after the transmission or reception of a cycle start packet. This indicates that the isochronous cycle is over; Note: Writing a value of ‘0’ to the bit has no effect. Bit 1: R/W Cycle Pending: Cycle pending is asserted when cycle timer offset is set to zero (rolled over or reset) and stays asserted until the isochronous cycle has ended. Bit 0: R/W Cycle Lost: The cycle timer has rolled over twice without the reception of a cycle start packet. This only occurs when cycle master is not asserted. 1997 Oct 21 29 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 13.1.4 Link / Phy Interrupt Enable (LNKPHYINTE) – Base Address: 0x00C This register is a mirror of the Link/Phy Interrupt Acknowledge (LNKPHYINTACK) register. Enabling an interrupt is accomplished by writing a ‘1’ to the bit corresponding to the interrupt desired. This register enables the interrupts described in the Link /Phy Interrupt Acknowledge register (LNKPHYINTACK) description. A one in any of the bits enables that function to create an interrupt. A zero disables the interrupt, however the status is readable in the Link /Phy Interrupt Acknowledge register. EHDRERR ETCERR ECYTMOUT ECYSEC ECYSTART ECYDONE ECYPEND ECYLOST ERXDATA EITBADFMT EATBADFMT ESNT_REJ EARBGAP EPHYINT EPHYRRX EPHYRST ETXRDY ECMDRST EFAIRGAP 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SV00275 Reset Value 0x00000000 Bits 18..0 are interrupt enable bits for the Link/Phy Interrupt Acknowledge (LNKPHYINTACK). 13.1.5 Cycle Timer Register (CYCTM) – Base Address: 0x010 Cycle Timer Register operation is controlled by the Cycle Timer Enable (CYTMREN) bit in the General Control Register. 3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CYCLE_SECONDS CYCLE_NUMBER CYCLE_OFFSET SV00276 Reset Value 0x00000000 Bit 31..25: R/W Seconds count: 1-Hz cycle timer counter. Bit 24..12: R/W Cycle Number: 8kHz cycle timer counter. Bit 11..0: R/W Cycle Offset: 24.576MHz cycle timer counter. 13.1.6 Phy Register Access (PHYACS) – Base Address: 0x014 This register provides access to the internal registers on the Phy. There are special considerations when reading or writing to this register. When reading a PHY register, the address of the register is written to the PHYRGAD field with the RDPHY bit set. The PHY data will be valid when the PHYRRX bit (LNKPHYINTACK register bit 14) is set. Once this happens the register data is available in the PHYRXDATA, the address of the register just read is also available in the PHYRXAD fields. When writing a Phy register, the address of the register to be written is set in the PHYRGAD field and the data to be written to the register is set in PHYRGDATA, along with the WRPHY bit being set. Once the write is complete, the WRPHY bit will be cleared. Do not write a new Read/Write command until the previous one has been completed. After the Self-ID phase, PHY register 0 will be read automatically. RDPHY WRPHY 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PHYRGAD PHYRGDATA PHYRXAD PHYRXDATA SV00277 Reset Value 0x00000000 Bit 31: R/W Read Phy Chip Register: When asserted, the PDI1394L11 sends a read register request with address equal to Phy Rg Ad to the Phy interface. This bit is cleared when the request is sent. Bit 30: R/W Write Phy Chip Register: When asserted, the PDI1394L11 sends a write register request with address equal to Phy Rg Ad to the Phy interface. This bit is cleared when the request is sent. Bit 27..24: R/W Phy Chip Register Address: This is the address of the Phy-chip register that is to be accessed. Bit 23..16: R/W Phy Chip Register Data: This is the data to be written to the Phy-chip register indicated in Phy Rg Ad. Bit 11..8: R Phy Chip Register Received Address: Address of register from which Phy Rx Data came. Bit 7..0: R Phy Chip Register Received Data: Data from register addressed by Phy Rx Ad. 1997 Oct 21 30 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 13.1.7 Global Interrupt Status and TX Control (GLOBCSR) – Base Address: 0x018 This register is the top level interrupt status register. If the external interrupt line is set, this register will indicate which major portion of the AV Link generated the interrupt. There is no interrupt acknowledge required at this level. These bits auto clear when the interrupts in the appropriate section of the device are cleared or disabled. Control of the AV transceiver is also provided by this register. 5 4 3 2 1 0 LNKPHYINT 6 ITXINT 7 IRXINT 8 ASYITX/RX 9 ELNKPHYINT EITXINT TXMODE EASYTX/RX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 EIRXINT Bits 0 to 3 are used to identify which internal modules are currently generating an interrupt. After identifying the module, the appropriate register in that module must be read to determine the exact cause of the interrupt. NOTES 1. There can be more than one interrupt source active at the same time. 2. The HIF INT_N signal (pin 28) remains active as long as there is at least one more enabled active interrupt status bit. SV00278 Reset Value 0x00010000 Bit 16: R/W Transmit Mode: Control bit, a ‘1’ enables the AV transmitter. A ‘0’ enables the AV receiver. The register defaults to ‘1’ on reset. Also this bit directly controls the direction of the bi-directional pins of the AV interface. Bit 11: R/W Enables generation of external interrupt by asynchronous transmitter and receiver module (ASYTX/RX, bit 3) when set (1). Disables such interrupts when clear (0) (regardless of ASYINTE contents). Bit 10: R/W Enables generation of external interrupt by the isochronous transmitter module (ITXINT, bit 2) when set (1). Disables such interrupts when clear (0) (regardless of ITXINTE contents). Bit 9: R/W Enables generation of external interrupt by the isochronous receiver module (IRXINT, bit 1) when set (1). Disables such interrupts when clear (0) (regardless of IRXINTE contents). Bit 8: R/W Enables generation of external interrupt by general link/phy module (LKPHYINT, bit 0) when set (1). Disables such interrupts when clear (0) (regardless of LNKPHYINTE contents). Bit 3: R Asynchronous Transmitter/ Receiver Interrupt: Interrupt source is in the Asynchronous Transmitter/ Receiver Interrupt Acknowledge/Source register. Bit 2: R AV Transmitter Interrupt: Interrupt source is in the AV Transmitter Interrupt Acknowledge/Source register. Bit 1: R AV Receiver Interrupt: Interrupt source is in the AV Receiver Interrupt Acknowledge/Source register. Bit 0: R Link-Phy Interrupt: Interrupt source is in the Link Phy Interrupt Acknowledge register. 13.2 AV (Isochronous) Transmitter and Receiver Registers 13.2.1 Isochronous Transmit Packing Control and Status (ITXPKCTL) – Base Address: 0x020 This register allows the user to set up the appropriate AV packets from data entered into the AV interface. The packing and control parameters (TRDEL, MAXBL, DBS, FN, QPC, and SPH) should never be changed while the transmitter is operating. The only exception to this is the MAXBL parameter when in MPEG-2 packing mode. MAXBL PM EN_FS RST_ITX TRDEL EN_ITX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SV00279 Reset Value 0x00000001 Bit 27..16: R/W TRDEL: Transport delay. Value added to cycle timer to produce time stamps. Lower 4 bits add to upper 4 bits of cycle_offset, (Cycle Timer Register, CYCTM). Remainder adds to cycle_count field. Bit 15..8: R/W MAXBL: The (maximum) number of data blocks to be put in a payload. Bit 4: R/W EN_ITX: Enable receipt of new application packets and generation of isochronous bus packets in every cycle. This bit also enables the Link Layer to arbitrate for the transmitter in each subsequent bus cycle. When this bit is disabled (0), the current packet will be transmitted and then the transmitter will shut down. 1997 Oct 21 31 Philips Semiconductors Product specification 1394 AV link layer controller Bit 3..2: R/W Bit 1: Bit 0: R/W R/W PDI1394L11 PM: packing mode: 00 = variable sized bus packets, most generic mode. 01 = fixed size bus packets. 10 = MPEG–2 packing mode. 11 = No data, just CIP headers are transmitted. EN_FS:enable generation/insertion of SYT stamps (Time Stamps) in CIP header. Reset Isochronous Transmitter: causes transmitter to be reset when ‘1’. In order for synchronous reset of ITX to work properly, the application must supply an AVCLK and ensure that the reset bit is kept (programmed) HIGH for at least the duration of one AVCLK period. Failure to do so may cause the application interface of this module to be improperly reset (or not reset at all). 13.2.2 Common Isochronous Transmit Packet Header Quadlet 1 (ITXHQ1) – Base Address: 0x024 The AV Transmit Packing Control register holds the specification for the packing scheme used on the AV data stream. This information is included in Common Isochronous Packet (CIP) header quadlet 1. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FN QPC SPH DBS SV00280 Reset Value 0x00000000 Bit 10: R/W SPH: Indicates that a 25-bit CYCTM based time stamp has to be inserted before each application packet. Bit 11..13: R/W QPC: Number of dummy quadlets to append to each source packet before it is divided into data blocks of the specified size. The value QPC must be less than DBS and less than 2FN. Bit 14..15: R/W FN: (Fraction Number) The encoding for the number of data blocks into which each source packet shall be divided (00 = 1, 01 = 2, 10 = 4, 11 = 8). Bit 16..23: R/W DBS: Size of the data blocks from which AV payload is constructed. The value 0 represents a length of 256 quadlets. 13.2.3 Common Isochronous Transmit Packet Header Quadlet 2 (ITXHQ2) – Base Address: 0x028 The contents of this register are copied to the second quadlet of the CIP header and transmitted with each isochronous packet. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FMT FDF SYT SV00281 Reset Value 0x00000000 Bit 29..24: R/W FMT: Value to be inserted in the FMT field in the AV header. Bit 23..0: R/W FDF/SYT: Value to be inserted in the FDF field. When the EN_FS bit in the Transmit Control and Status Register (ITXPKCTL) is set (=1), the lower 16 bits of this register are replaced by an SYT stamp if a rising edge on AVFSYNCIN has been detected or all ‘1’s if no such edge was detected since the previous packet. The upper 8 bits of the register are sent as they appear in the FDF register. When the EN_FS bit in the Transmit Control and Status Register is unset (=0), the full 24 bits can be set to any application specified value. 1997 Oct 21 32 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 13.2.4 Isochronous Transmitter Interrupt Acknowledge (ITXINTACK) – Base Address: 0x02C The AV Transmitter Interrupt Control and Status register is the interrupt register for the AV transmitter. Bits 2, 3, and 4 ”auto repair” themselves, i.e. AVLINK will detect the situation and attempt to recover on its own. The host controller still needs to clear these interrupts to be alerted the next time. SYTTI EOTI DBCEI IDDSCI PLDSCI ITXMFI ITXMEI TRMSYT TRMBP DBCERR INPERR DISCARD ITXFULL ITXEMPTY 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SV00282 Reset Value 0x00000000 Bits 6 .. 0 are interrupt acknowledge bits; and are defined as: Bit 6: R/W TRMSYT: Interrupt on transmission of a SYT in CIP header quadlet 2 Bit 5: R/W TRMBP: Interrupt on payload transmission/discard complete. Bit 4: R/W DBCERR: Acknowledge interrupt on Data Block Count (DBC) synchronization loss. Bit 3: R/W INPERR: Acknowledge interrupt on input error (input data discarded). Bit 2: R/W DISCARD: Interrupt on lost cycle (payload discarded). Bit 1: R/W ITXFULL: Interrupt on isochronous memory bank full. This is a fatal error, the recommended action is to reset and re-initialize the transmitter. Bit 0: R/W ITXEMPTY: Interrupt on isochronous memory bank empty. Other bits will always read ‘0’. EITXFULL 2 1 0 EITXEMPTY 5 4 3 EINPERR EDISCARD 6 ETRMBP EDBCERR ITXMEI ITXMFI IDDSCI PLDSCI SYTTI EOTI DBCEI 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 ETRMSYT 13.2.5 Isochronous Transmitter Interrupt Enable (ITXINTE) – Base Address: 0x030 These are the enabled bits for the AV Transmitter Control. SV00793 Reset Value 0x00000000 Bits 6..0 are interrupt enable bits for the Isochronous Transmitter Interrupt Acknowledge register (ITXINTACK). 13.2.6 Isochronous Transmitter Control Register (ITXCTL) – Base Address: 0x34 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TAG CHANNEL SPD SYNC SV00283 Reset Value 0x00000000 Bit 15..14: R/W Tag: Tag code to insert in isochronous bus packet header. Should be ‘01’ for IEC 61883 International Standard data. Bit 13..8: R/W Channel: Isochronous channel number. Bit 5..4: R/W Speed: Cable transmission speed (S100, S200, S400). 00=100Mbs 01=200Mbs 10=400Mbs 11=reserved Bit 3..0 R/W Sync: Code to insert in SY field of isochronous bus packet header. 1997 Oct 21 33 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 13.2.7 Isochronous Transmitter Memory Status (ITXMEM) – Base Address: 0x038 The AV Transmitter Memory Status register reports on the condition of the internal memory buffer used to store incoming AV data streams before transmission over the 1394 bus. ITXMF ITXMAF ITXM5AV ITXME 3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SV00284 Reset Value 0x00000003 Bit 3: R ITXMF: memory is completely full, no storage available. Bit 2: R ITXMAF: almost full, exactly one quadlet of storage available. Bit 1: R ITXM5AV: at least 5 more quadlets of storage available. Bit 0: R ITXME: memory bank is empty (zero quadlets stored). 13.2.8 Isochronous Receiver Unpacking Control (IRXPKCTL) – Base Address: 0x040 BPAD EN_FS RST_IRX RMVUAP SPAV EN_IRX IRXMFIE IRXMEIE FSYIE SEQEIE CRCEIE TAGEIE RXBPIE SQOVIE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SV00285 Reset Value 0x00000041 AV Receiver Control Bits. Bit 6: R/W RMVUAP: Remove unreliable packets from memory, do not attempt delivery Bit 5: R SPAV: Source packet available for delivery in buffer memory. Bit 4: R/W EN_IRX: Enable receiver operation. Value is only checked whenever a new bus packet arrives, so enable/disable while running is ‘graceful’. Bit 2..3: R/W BPAD: Value indicating the amount of byte padding to be removed from the last data quadlet of each source packet, from 0 to 3 bytes. This is in addition to quadlet padding as defined in IEC 61883 International Standard. Bit 1: R/W EN_FS: Enable processing of SYT stamps. Bit 0: R/W RST_IRX: causes the receiver to be reset when ‘1’. In order for synchronous reset of IRX to work properly, the application must supply an AVCLK and ensure that the reset bit is kept (programmed) HIGH for at least the duration of one AVCLK period. Failure to do so may cause the application interface of this module to be improperly reset (or not reset at all). 13.2.9 Common Isochronous Receiver Packet Header Quadlet 1 (IRXHQ1) – Base Address: 0x044 This quadlet represents the last received header value when AV receiver is operating. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FN QPC SPH DBS E0 F0 SID SV00286 Reset Value 0x00000000 Bit 31..30: R E0: End of Header, F0: Format: Always set to 00 for first AV header quadlet Bit 29..24 R SID: Source ID, contains the node address of the sender of the isochronous data. Bit 23.16: R DBS: Size of the data blocks from which AV payload is constructed. The value 0 represents a length of 256 quadlets. Bit 15..14: R FN (Fraction Number): The encoding for the number of data blocks into which each source packet has been divided (00 = 1, 01 = 2, 10 = 4, 11 = 8) by the transmitter of the packet. Bit 13..11: R QPC: Number of dummy quadlets appended to each source packet before it was divided into data blocks of the specified size. 1997 Oct 21 34 Philips Semiconductors Product specification 1394 AV link layer controller Bit 10: R PDI1394L11 SPH: Indicates that a CYCTM based time stamp is inserted before each application packet (25 bits specified in the IEC 61883 International Standard). 13.2.10 Common Isochronous Receiver Packet Header Quadlet 2 (IRXHQ2) – Base Address: 0x048 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SYT FDF E1 F1 FMT SV00287 Reset Value 0x0000FFFF Bit 31..30: R E1: End of Header, F1: Format: Should be set to 10 for second AV header quadlet. Bit 29..24: R FMT: Value inserted in the Format field. Bit 23..0: R FDF/SYT: If ‘‘EN FS” in Register IRXPKCTL (0x040) is set to ‘1’, then lower 16-bits are interpreted as SYT. 13.2.11 Isochronous Receiver Interrupt Acknowledge (IRXINTACK) – Base Address: 0x04C IRXFULL IRXEMPTY FSYNC SEQERR CRCERR CIPTAGFLT RCVBP SQOV 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SV00288 Reset Value 0x00000000 Bit 7: R/W IRXFULL: Isochronous data memory bank has become full. This is a fatal error, the recommended action is to reset and re-initialize the transmitter. Bit 6: R/W IRXEMPTY: Isochronous data memory bank has become empty. Bit 5: R/W FSYNC: Pulse at fsync output. Bit 4: R/W SEQERR: Sequence error of data blocks. Bit 3: R/W CRCERR: CRC error in bus packet. Bit 2: R/W CIPTAGFLT: Faulty CIP header tag (E,F bits). i.e.: The CIP header did not meet the standard and the whole packet is ignored. Bit 1: R/W RCVBP: Bus packet processing complete. Bit 0: R/W SQOV: Status queue overflow. This is a fatal error, the recommended action is to reset and re-initialize the transmitter. 13.2.12 Isochronous Receiver Interrupt Enable (IRXINTE) – Base Address: 0x050 Interrupt enable bits for AV Receiver. ECIPTAGFLT ERCVBP ESQOV EFSYNC ESEQERR ECRCERR EIRXFULL EIRXEMPTY 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SV00794 Reset Value 0x00000000 Bit 7..0 are interrupt enable bits for the Isochronous Receiver Interrupt Acknowledge (IRXINTACK). 1997 Oct 21 35 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 13.2.13 Isochronous Receiver Control Register (IRXCTL) – Base Address: 0x054 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPD TAG CHANNEL ERR SYNC SV00289 Reset Value 0x00000000 Bit 17..16: R SPD: Speed of last received isochronous packet (S100 .. S400). 00 = 100 Mbps 01 = 200 Mbps 10 = 400 Mbps 11 = Reserved Bit 15..14: R/W TAG: Isochronous tag value (must match) for AV format, ‘01’ for IEC 61883 International Standard data. Bit 13..8: R/W CHAN: Channel number to receive isochronous data. Bit 7..4: R ERR: Error code for last received isochronous AV packet. Table 9. Error Codes Code 0000 Name reserved 0001 ack_complete 0010 through 1100 reserved 1101 ack_data_error 1110 and 1111 reserved Bit 3..0: R Meaning The node has successfully accepted the packet. If the packet was a request subaction, the destination node has successfully completed the transaction and no response subaction shall follow. The node could not accept the block packet because the data field failed the CRC check, or because the length of the data block payload did not match the length contained in the dataLength field. this code shall not be returned for any packet that does not have a data block payload. SYNC: Last received SY code in isochronous bus packet header. 13.2.14 Isochronous Receiver Memory Status (IRXMEM) – Base Address: 0x058 IRXMF IRXMAF IRXM5AV IRXME 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SV00290 Reset Value 0x00000003 Bit 3: R IRXMF: Full: no space available. Bit 2: R IRXMAF: Almost full: exactly one quadlet of storage available. Bit 1: R IRXM5AV: At least 5 more quadlets of storage available. Bit 0: R RXME: Memory bank is empty (no data committed). 1997 Oct 21 36 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 13.3 Asynchronous Control and Status Interface 13.3.1 Asynchronous RX/TX Control (ASYCTL) – Base Address: 0x080 ARXRST ATXRST ARXALL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MAXRC TOS TOF SV00291 Reset Value 0x00300320 Bit 22: R/W ARXRST: Asynchronous receiver reset. This bit will auto clear when the link layer state machine is idle. Bit 21: R/W ATXRST: Asynchronous transmitter reset Bit 20: R/W ARXALL: Receive and filter only RESPONSE packets. When set (1), all responses are stored. When clear (0), only solicited responses are stored. Bit 19..16: R/W MAXRC: Maximum number of asynchronous transmitter single phase retries Bit 15..13: R/W TOS: Time out seconds, integer of 1 second Bit 12..0: R/W TOF: Time out fractions, integer of 1/8000 second 13.3.2 Asynchronous RX/TX Memory Status (ASYMEM) – Base Address: 0x084 CMDRST TRSPQIDLE TREQQIDLE RRSPQF RRSPQAF RRSPQ5AV RRSPQE RREQQF RREQQAF RREQQ5AV RREQQE TRSPQF TRSPQAF TRSPQ5AV TRSPQE TREQQF TREQQAF TREQQ5AV TREQQE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SV00795 Reset Value 0x00000000 Bit 17: Bit 16: Bit 15: Bit 14: Bit 13: Bit 12: Bit 11: Bit 10: Bit 9: Bit 8: Bit 7: Bit 6: Bit 5: Bit 4: Bit 3: Bit 2: Bit 1: Bit 0: 1997 Oct 21 R R R R R R R R R R R R R R R R R R Unused bits read ‘0’. The information in this register is primarily used for diagnostics. TRSPQIDLE: Transmitter response queue idle. Indicates that the transfer register for this queue is empty. TREQQIDLE: Transmitter request queue idle. Indicates that the transfer register for this queue is empty. RRSPQF: Receiver response queue full. RRSPQAF: Receiver response queue almost full (precisely 1 more quadlet available). RRSPQ5AV: Receiver response queue at least 5 quadlets available. RRSPQE: Receiver response queue empty. RREQQF: Receiver request queue full. RREQQAF: Receiver request queue almost full (precisely 1 more quadlet available). RREQQ5AV: Receiver request queue at least 5 quadlets available. RREQQE: Receiver request queue empty. TRSPQF: Transmitter response queue full. TRSPQAF: Transmitter response queue almost full (precisely 1 more quadlet available). TRSPQ5AV: Transmitter response queue at least 5 quadlets available. TRSPQE: Transmitter response queue empty. TREQQF: Transmitter response queue full. TREQQAF: Transmitter request queue almost full (precisely 1 more quadlet available). TREQQ5AV: Transmitter response queue at least 5 quadlets available. TREQQE: Transmitter request queue empty. 37 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 13.3.3 Asynchronous Transmit Request Next (TX_RQ_NEXT) – Base Address: 0x088 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TX_RQ_NEXT SV00293 Bit 31..0: W TX_RQ_NEXT: First/middle quadlet of packet for transmitter request queue (write only). Writing this register will clear the TREQQWR flag until the quadlet has been written to its queue. 13.3.4 Asynchronous Transmit Request Last (TX_RQ_LAST) – Base Address: 0x08C 3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TX_RQ_LAST SV00294 Bit 31..0: W TX_RQ_LAST: Last quadlet of packet for transmitter request queue (write only). Writing this register will clear the TREQQWR flag until the quadlet has been written to its queue. 13.3.5 Asynchronous Transmit Response Next (TX_RP_NEXT) – Base Address: 0x090 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TX_RP_NEXT SV00295 Bit 31..0: W TX_RP_NEXT: First/middle quadlet of packet for transmitter response queue (write only). Writing this register will clear the TRSPQWR flag until the quadlet has been written to its queue. 13.3.6 Asynchronous Transmit Response Last (TX_RP_LAST) – Base Address: 0x094 3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TX_RP_LAST SV00296 Bit 31..0: 1997 Oct 21 W TX_RP_LAST: Last quadlet of packet for transmitter response queue (write only). Writing this register will clear the TRSPQWR flag until the quadlet has been written to its queue. 38 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 13.3.7 Asynchronous Receive Request (RREQ) – Base Address: 0x098 3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RREQ SV00297 Reset Value 0x00000000 Bit 31..0: R RREQ:Quadlet of packet from receiver request queue (transfer register). Reading this register will clear the RREQQQAV flag until the next received quadlet is available for reading. 13.3.8 Asynchronous Receive Response (RRSP) – Base Address: 0x09C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RRSP SV00298 Reset Value 0x00000000 Bit 31..0: R RRSP:Quadlet of packet from receiver response queue (transfer register). Reading this register will clear the RRSPQQAV flag until the next received quadlet is available for reading. 13.3.9 Asynchronous RX/TX Interrupt Acknowledge (ASYINTACK) – Base Address: 0x0A0 1 TRSPQWR 2 0 TREQQWR 3 TREQQWRERR 4 TREQQFULL 5 TRSPQWRERR 6 RCVDRSP 7 TRSPQFULL 8 TIMEOUT RRSPQQAV 9 RREQQQAV RRSPQRDERR RREQQRDERR RRSPQLASTQ RREQQLASTQ SIDQAV RRSPQFULL 22 21 20 19 18 17 16 15 14 13 12 11 10 RREQQFULL 31 30 29 28 27 26 25 24 23 SV00796 Reset Value 0x00000000 Bit 31..17: R/W Unused bits read ‘0’ Bit 16: R/W RRSPQFULL: Receiver response queue did become full. Bit 15: R/W RREQQFULL: Receiver request queue did become full. Bit 14: R/W SIDQAV: Current quadlet in RREQ is selfID data. Bit 13: R/W RRSPQLASTQ: Current quadlet in RRSP is last quadlet of packet. Bit 12: R/W RREQQLASTQ: Current quadlet in RREQ is last quadlet of packet. Bit 11: R/W RRSPQRDERR: Receiver response queue read error (transfer error) or bus reset occurred. When set (1), this queue is blocked for read access. Bit 10: R/W RREQQRDERR: Receiver request queue read error (transfer error) or bus reset occurred. When set (1), this queue is blocked for read access. Bit 9: R/W RRSPQQAV: Receiver response queue quadlet available (in RRSP). Bit 8: R/W RREQQQAV: Receiver request queue quadlet available (in RREQ). Bit 7: R/W TIMEOUT: Split transaction response timeout. Bit 6: R/W RCVDRSP: Solicited response received (within timeout interval). Bit 5: R/W TRSPQFULL: Transmitter response queue did become full. Bit 4: R/W TREQQFULL: Transmitter request queue did become full. Bit 3: R/W TRSPQWRERR: Transmitter response queue write error (transfer error). 1997 Oct 21 39 Philips Semiconductors Product specification 1394 AV link layer controller Bit 2: Bit 1: Bit 0: R/W R/W R/W PDI1394L11 TREQQWRERR: Transmitter request queue write error (transfer error). TRSPQWR: Transmitter response queue written (transfer register emptied). TREQQWR: Transmitter request queue written (transfer register emptied). 13.3.10 Asynchronous RX/TX Interrupt Enable (ASYINTE) – Base Address: 0x0A4 1 0 ETREQQWR 2 ETRSPQWR 3 ETREQQWRERR 4 ETREQQFULL 5 ETRSPQWRERR 6 ETRSPQFULL 7 ETIMEOUT 8 ERCVDRSP ERRSPQQAV 9 ERREQQQAV ERREQQRDERR ERREQQLASTQ ERRSPQRDERR ERRSPQLASTQ ESIDQAV ERRSPQFULL 22 21 20 19 18 17 16 15 14 13 12 11 10 ERREQQFULL 31 30 29 28 27 26 25 24 23 SV00797 Reset Value 0x00000000 Bits16..0 are interrupt enable bits for the Asynchronous RX/TX Interrupt Acknowledge (ASYINTACK). 14.0 DC ELECTRICAL CHARACTERISTICS Table 10. DC Electrical Characteristics NAME DESCRIPTION MIN MAX UNIT NOTE 0.8 V Pin categories 1, 2, 3 V Pin categories 1, 2, 3 VIL LOW input voltage VIH HIGH input voltage 2.0 VIT1+ Input threshold, rising edge VDD/2 + 0.12 VDD/2 + 0.66 V Pin categories 6, 8 LOW to HIGH transition VIT1– Input threshold, falling edge VDD/2 – 0.66 VDD/2 – 0.12 V Pin categories 6, 8 HIGH to LOW transition VOH1 HIGH output voltage 2.4 V Pin category 1 IOH = 8mA IOL = 8mA VOL1 LOW output voltage V Pin category 1 IOH = 8mA IOL = 8mA VOH2 HIGH output voltage V Pin categories 4, 6, 7 IOH = 4mA VOL2 LOW output voltage 0.4 V Pin categories 4, 5, 6, 7 IOL = 4mA ±1 mA Pin categories 1, 2, 3 VI = 5.5V or 0V 100 mA Pin category 8 VI = 5.5V or 0V ±5 mA Pin categories 1, 7 VI = 5.5V or 0V 200 mA Pin category 6 VI = 5.5V or 0V 150 mA Under idle conditions, the average value is 20 mA IL IOZ IDD 1997 Oct 21 0.4 2.4 Input In ut leakage current 3-State output current Active supply current 40 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 14.1 Pin Categories Table 11. Pin Categories Category 1: Input/Output Category 2: Input Category 3: Input Category 4: Output HIF D[7:0] HIF A[8:0] RESET_N CYCLEOUT AVSYNC HIF CS_N CYCLEIN AVERR0 AVVALID HIF WR_N AVCLK AVERR1 AV D[7:0] HIF RD_N ISO_N CLK25 AVFSYNCIN Category 5: Output HIF INT_N Category 6: Input/Output Category 7: PHY D[0:7] LREQ Category 8: SCLK PHY CTL[0:1] AVFSYNCOUT AVENDPCK 15.0 AC CHARACTERISTICS GND = 0V, CL = 50pF LIMITS SYMBOL PARAMETER TEST CONDITIONS WAVEFORMS Tamb = 0°C to +70°C MIN tPERIOD TYP UNIT MAX AV clock period Figure 23 41.67 ns tSU AV clock setup time Figure 23 20 ns tIH AV clock input hold time Figure 23 3 ns 3 20 ns 140 ns tOD AV clock output delay time Figure 23 tWHIGH AV clock pulse width HIGH Figure 23 tWLOW AV clock pulse width LOW Figure 23 tPWFSO AVFSYNCOUT pulse width HIGH Figure 24 100 tPWFSI AVFSYNCIN pulse width HIGH Figure 25 100 ns tSUP PHY-link setup time Figure 26 6.0 ns tHP PHY-link hold time Figure 26 2.5 SCLK period Figure 26 20.347 tSCLKPER Note: CL = 20pF ns 20.345 20.343 ns 14.0 ns tDP PHY-link output delay Figure 27 2.0 tAS Host address setup time Figure 28 0 ns tAH Host address hold time Figure 28 0 ns tCL Host chip select pulse width LOW Figure 28 115 ns tCH Host chip select pulse width HIGH Figure 28 42 ns 115 tRP Host read pulse width Figure 28 tACC Host access time Figure 28 ns tDH Host data hold time Figure 28 0 ns tDS Host data setup time Figure 28 0 ns 115 ns tWRP Host write pulse width Figure 28 115 ns tCWH CYCLEIN HIGH pulse width Figure 29 200 ns tCWL CYCLEIN LOW pulse width Figure 29 200 ns tCP CYCLEIN cycle period Figure 29 125 µs tCD CYCLEOUT cycle delay Figure 30 RESET_N pulse width LOW Figure 31 tRESET 1997 Oct 21 41 20 10 ns µs Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 16.0 TIMING DIAGRAMS 16.1 AV Interface Operation AVCLK MESSAGE AV D[7:0] INVALID DATA MESSAGE INVALID DATA MESSAGE AVSYNC AVVALID AVERR[0] ASSERTED IN THE EVENT OF A BUS PACKET CRC ERROR AVERR[1] ASSERTED IN THE EVENT OF A DATA BLOCK SEQUENCE ERROR SV00240 Figure 22. AV Interface Operation Diagram 16.2 AV Interface Critical Timings AVCLK ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ tWHIGH AV D [7:0], AVVALID, AVSYNC, AVENDPCK VALID tSU AV D [7:0], AVERR[1:0], AVSYNC, AVVALID tIH tWLOW tPERIOD VALID tOD SV00688 Figure 23. AV Interface Timing Diagram AVFSYNCOUT tPWFSO SV00689 Figure 24. AVFSYNCOUT Timing Diagram AVFSYNCIN tPWFSI SV00822 Figure 25. AVFSYNCIN Timing Diagram 1997 Oct 21 42 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 16.3 PHY-Link Interface Critical Timings tSCLKPER SCLK 50% tSUP PHY D[0:7], PHY CTL[0:1] tHP 50% 50% SV00695 Figure 26. PHY D[0:7], PHY CTL[0:1] Input Setup and Hold Timing Waveforms SCLK 50% tDP PHY D[0:7], PHY CTL[0:1], LREQ 50% SV00694 Figure 27. PHY D[0:7], PHY CTL[0:1], and LREQ Output-Delay Timing Waveforms 16.4 Host Interface Critical Timings READ tAS tAH tAS tAH HIF A[8:0] VALID tCL tCH HIF CS_N tRP HIF RD_N ÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉ HIF D[7:0] VALID tACC tDH WRITE tWRP HIF WR_N HIF D[7:0] VALID tDS tDH SV00699 Figure 28. Host Interface Timing Waveforms 1997 Oct 21 43 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 16.5 CYCLEIN/CYCLEOUT Timings CYCLEIN 50% 50% tCWH 50% tCWL tCP SV00696 Figure 29. CYCLEIN Waveform SCLK 50% 50% tCD tCD CYCLEIN CYCLEOUT 50% 50% SV00697 Figure 30. CYCLEOUT Waveforms 16.6 RESET Timings RESET_N 50% 50% tRESET SV00698 Figure 31. RESET_N Waveform 1997 Oct 21 44 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm 1997 Oct 21 45 SOT318-2 Philips Semiconductors Product specification 1394 AV link layer controller PDI1394L11 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 10–97 Document order number: 1997 Oct 21 46 9397 750 02943