MAXIM MAX5898EGK+D

19-3756; Rev 1; 7/07
KIT
ATION
EVALU
E
L
B
A
IL
AVA
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
Features
The MAX5898 programmable interpolating, modulating,
500Msps, dual digital-to-analog converter (DAC) offers
superior dynamic performance and is optimized for highperformance wideband, single- and multicarrier transmit
applications. The device integrates a selectable 2x/4x/8x
interpolating filter, a digital quadrature modulator, and
dual 16-bit, high-speed DACs on a single integrated circuit. At 30MHz output frequency and 500Msps update
rate, the in-band SFDR is 81dBc, while only consuming
1.2W. The device also delivers 71dB ACLR for fourcarrier WCDMA at a 61.44MHz output frequency.
The selectable interpolating filters allow lower input data
rates while taking advantage of the high DAC update
rates. These linear-phase interpolation filters ease reconstruction filter requirements and enhance the passband
dynamic performance. Each channel includes offset and
gain programmability, allowing the user to calibrate out
local oscillator (LO) feedthrough and sideband suppression errors generated by analog quadrature modulators.
The MAX5898 features a fIM / 4 digital image-reject
modulator. This modulator generates a quadrature-modulated IF signal that can be presented to an analog I/Q
modulator to complete the upconversion process. A
second digital modulation mode allows the signal to be
frequency-translated with image pairs at fIM / 2 or fIM / 4.
The MAX5898 features a standard LVDS interface for
low electromagnetic interference (EMI). Interleaved
data is applied through a single 16-bit bus. A 3.3V
SPI™ port is provided for mode configuration. The programmable modes include the selection of 2x/4x/8x
interpolating filters, fIM / 2, fIM / 4 or no digital quadrature modulation with image rejection, individual channel
gain and offset adjustment, and offset binary or two’scomplement data interface.
♦ 71dB ACLR at fOUT = 61.44MHz (Four-Carrier
WCDMA)
♦ Meets Multicarrier UMTS, cdma2000®, GSM
Spectral Masks (fOUT = 122MHz)
♦ Noise Spectral Density = -160dBFS/Hz at
fOUT = 16MHz
♦ 90dBc SFDR at Low-IF Frequency (10MHz)
♦ 88dBc SFDR at High-IF Frequency (50MHz)
♦ Low Power: 831mW (fCLK = 250MHz)
♦ User Programmable
Selectable 2x, 4x, or 8x Interpolating Filters
< 0.01dB Passband Ripple
> 95dB Stopband Rejection
Selectable Real or Complex Modulator Operation
Selectable Modulator LO Frequency: OFF, fIM / 2,
or fIM / 4
Selectable Output Filter: Lowpass or Highpass
Per Channel Gain and Offset Adjustment
♦ EV Kit Available (Order the MAX5898EVKIT)
Compatible versions with CMOS interfaces and 12-, 14-,
and 16-bit resolutions are also available. Refer to the
MAX5893 data sheet for 12-bit CMOS, MAX5894 for 14bit CMOS, and the MAX5895 for 16-bit CMOS versions.
Applications
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
MAX5898EGK+D -40°C to +85°C
68 QFN-EP*
G6800-4
(10mm x 10mm)
MAX5898EGK-D
68 QFN-EP*
G6800-4
(10mm x 10mm)
*EP = Exposed paddle.
Selector Guide
PART
RESOLUTION
(BITS)
DAC UPDATE
RATE (Msps)
INPUT
LOGIC
MAX5893
12
500
CMOS
MAX5894
14
500
CMOS
MAX5895
16
500
CMOS
MAX5898
16
500
LVDS
Simplified Diagram
2x
INTERPOLATING
FILTERS
MODULATOR
1x/2x/4x
INTERPOLATING
FILTERS
DATA SYNCH
AND DEMUX
DATA PORT
DATACLK
SPI is a trademark of Motorola, Inc.
cdma2000 is a registered trademark of Telecommunications
Industry Association.
-40°C to +85°C
+Denotes a lead-free package.
D = Dry pack.
Base Stations: 3G Multicarrier UMTS, CDMA, and GSM
Broadband Wireless Transmitters
Broadband Cable Infrastructure
Instrumentation and Automatic Test Equipment (ATE)
Analog Quadrature Modulation Architectures
PKG
CODE
DAC
DAC
OUTI
OUTQ
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX5898
General Description
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
ABSOLUTE MAXIMUM RATINGS
DOUT, DATACLKP, DATACLKN Continuous Current ..........8mA
Continuous Power Dissipation (TA = +70°C)
68-Pin QFN (derate 41.7mW/°C above +70°C)
(Note 1) ...................................................................3333.3mW
Junction Temperature ......................................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
DVDD1.8, AVDD1.8 to GND, DACREF ..................-0.3V to +2.16V
AVDD3.3, AVCLK, DVDD3.3 to GND, DACREF ........-0.3V to +3.9V
DATACLKP, DATACLKN, D0P–D15P,
D0N–D15N, SELIQP, SELIQN to GND,
DACREF ..........................................-0.3V to (DVDD1.8 + 0.3V)
CS, RESET, SCLK, DIN, DOUT to
GND, DACREF ................................-0.3V to (DVDD3.3 + 0.3V)
CLKP, CLKN to GND, DACREF..............-0.3V to (AVCLK + 0.3V)
REFIO, FSADJ to GND, DACREF ........-0.3V to (AVDD3.3 + 0.3V)
OUTIP, OUTIN, OUTQP,
OUTQN to GND, DACREF...............-0.3V to (AVDD3.3 + 0.3V)
Note 1: Thermal resistance based on a multilayer board with 4 x 4 via array in exposed paddle area.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is
50Ω double-terminated, external reference at 1.25V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C,
unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution
Differential Nonlinearity
DNL
Integral Nonlinearity
INL
Offset Error
OS
±0.003
LSB
+0.02
±0.03
GEFS
(Note 3)
-4
Gain-Error Drift
Full-Scale Output Current
Bits
LSB
±3
-0.02
Offset Drift
Gain Error
16
±1
±0.06
ppm/°C
+4
±110
IOUTFS
(Note 3)
Output Compliance
%FS
%FS
ppm/°C
2
20
-0.5
+1.1
mA
V
Output Resistance
ROUT
1
MΩ
Output Capacitance
COUT
5
pF
DYNAMIC PERFORMANCE
Maximum Clock Frequency
fCLK
500
Minimum Clock Frequency
fCLK
Maximum DAC Update Rate
fDAC
fDAC = fCLK or fDAC = fCLK / 2
Minimum DAC Update Rate
fDAC
fDAC = fCLK or fDAC = fCLK / 2
Maximum Data Clock Frequency
Maximum Input Data Rate
fDATACLK
fDATA
10
500
MHz
Msps
10
Msps
Interleaved data
250
MHz
Per channel
125
MWps
fDATA = 125Mwps,
fOUT = 16MHz, fOFFSET
= 10MHz, -12dBFS
Noise Spectral Density
fDATA = 125Mwps,
fOUT = 16MHz, fOFFSET
= 10MHz, 0dBFS
2
MHz
No interpolation
-156
2x interpolation
-157
4x interpolation
-157
4x interpolation
-154
_______________________________________________________________________________________
dBFS/
Hz
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
(DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is
50Ω double-terminated, external reference at 1.25V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C,
unless otherwise noted.) (Note 2)
PARAMETER
In-Band SFDR
(DC to fDATA / 2)
SYMBOL
SFDR
CONDITIONS
Four-Tone IMD
TTIMD
FTIMD
fDATA = 125Mwps,
interpolation off,
-0.1dBFS
fOUT = 30MHz
84
fDATA = 125Mwps,
2x interpolation,
-0.1dBFS
fOUT = 10MHz
ACLR
fOUT = 50MHz
MAX
UNITS
77
79
89
fOUT = 30MHz
83
fOUT = 50MHz
92
fDATA = 125Mwps,
4x interpolation,
-0.1dBFS
fOUT = 10MHz
89
fOUT = 30MHz
83
fOUT = 50MHz
89
fDATA = 125Mwps,
fOUT1 = 9MHz, fOUT2 =
10MHz, -6.1dBFS
No interpolation
-96
2x interpolation
-99
4x interpolation
-95
2x interpolation,
fIM / 4 complex
modulation
-81
4x interpolation,
fIM / 4 complex
modulation
-71
dBc
dBc
fDATA = 62.5Mwps,
fOUT1 = 9MHz, fOUT2 =
10MHz, -6.1dBFS
8x interpolation
-94
fDATA = 62.5Mwps,
fOUT1 = 69MHz, fOUT2
= 70MHz, -6.1dBFS
8x interpolation,
fIM / 4 complex
modulation
-71
8x, highpass
fDATA = 62.5Mwps,
interpolation,
fOUT1 = 179MHz, fOUT2
fIM / 4 complex
= 180MHz, -6.1dBFS
modulation
-71
fDATA = 125Mwps, fOUT spaced 1MHz
apart from 32MHz, -12dBFS, 2x
interpolation
-89
4x interpolation
79
8x interpolation
79
fDATA = 122.88Mwps,
fOUT = 61.44MHz
2x interpolation,
fIM / 4 complex
modulation
76
fDATA = 122.88Mwps,
fOUT = 122.88MHz
4x interpolation,
fIM / 4 complex
modulation
68
fDATA = 61.44Mwps,
fOUT = baseband
ACLR for WCDMA
(Note 4)
TYP
90
fDATA = 125Mwps,
fOUT1 = 79MHz,
fOUT2 = 80MHz,
-6.1dBFS
Two-Tone IMD
MIN
fOUT = 10MHz
dBc
dB
_______________________________________________________________________________________
3
MAX5898
ELECTRICAL CHARACTERISTICS (continued)
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is
50Ω double-terminated, external reference at 1.25V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C,
unless otherwise noted.) (Note 2)
PARAMETER
Output Propagation Delay
SYMBOL
tPD
CONDITIONS
MIN
TYP
MAX
UNITS
1x interpolation (Note 5)
2.9
ns
Output Rise Time
tRISE
10% to 90% (Note 6)
0.75
ns
Output Fall Time
tFALL
10% to 90% (Note 6)
1
ns
Output Settling Time
To 0.5% (Note 6)
11
ns
Output Bandwidth
-1dB bandwidth (Note 7)
240
MHz
Passband Width
Ripple < -0.01dB
Stopband Rejection
Data Latency
0.4 x
fDATA
0.604 x fDATA, 2x interpolation
100
0.604 x fDATA, 4x interpolation
100
0.604 x fDATA, 8x interpolation
100
1x interpolation
22
2x interpolation
70
4x interpolation
146
8x interpolation
311
dB
Clock
Cycles
DAC INTERCHANNEL MATCHING
Gain Match
Gain-Match Tempco
Phase Match
Phase-Match Tempco
ΔGain
ΔGain/°C
ΔPhase
fOUT = DC - 80MHz, IOUTFS = 20mA
±0.1
dB
IOUTFS = 20mA
±0.02
ppm/°C
fOUT = 60MHz, IOUTFS = 20mA
±0.13
Deg
ΔPhase/°C IOUTFS = 20mA
DC Gain Match
IOUTFS = 20mA (Note 3)
Crosstalk
fOUT = 50MHz, fDAC = 250MHz
±0.006
-0.2
±0.04
Deg/°C
+0.2
-95
dB
dB
REFERENCE
Reference Input Range
0.12
Reference Output Voltage
VREFIO
Reference Input Resistance
RREFIO
Internal reference
1.14
Reference Voltage Drift
1.2
1.32
V
1.28
V
10
kΩ
±50
ppm/°C
CMOS LOGIC INPUTS (SCLK, CS, RESET, DIN)
Input High Voltage
VIH
Input Low Voltage
VIL
Input Current
Input Capacitance
IIN
CIN
0.7 x
DVDD3.3
V
0.3 x
DVDD3.3
-10
±0.1
3
+10
V
µA
pF
CMOS LOGIC OUTPUT (DOUT)
Output High Voltage
VOH
ILOAD = 200µA
Output Low Voltage
VOL
ISINK = 200µA
Output Leakage Current
4
Tri-state
0.8 x
DVDD3.3
V
0.2 x
DVDD3.3
1
_______________________________________________________________________________________
V
µA
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
(DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is
50Ω double-terminated, external reference at 1.25V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C,
unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
Rise/Fall Time
CONDITIONS
MIN
CLOAD = 10pF, 20% to 80%
TYP
MAX
1.5
UNITS
ns
LVDS LOGIC INPUTS (D15P–D0P, D15N–D0N, SELIQP, SELIQN)
Differential Input Logic High
Differential Input Logic Low
Input Common-Mode Voltage
VIH
100
mV
VIL
-100
VICM
1.125
1.25
1.375
mV
V
Differential Input Resistance
RIN
110
Ω
Input Capacitance
CIN
2.5
pF
LVDS CLOCK INPUT/OUTPUT (DATACLKP, DATACLKN)
Differential Input Amplitude High
VIH
250
Differential Input Amplitude Low
VIL
Differential Output Amplitude High
VOH
RLOAD = 100Ω differential (Note 3)
Differential Output Amplitude Low
VOL
RLOAD = 100Ω differential (Note 3)
Output Common-Mode Voltage
250
RLOAD = 100Ω differential, CLOAD = 8pF,
20% to 80%
-250
mV
-250
mV
340
-340
VOCM
Output Rise/Fall Time
mV
mV
1.25
V
0.9
ns
CLOCK INPUTS (CLKP, CLKN) (Note 8)
Differential Input Voltage Swing
VDIFF
Sine-wave input
> 1.5
Square-wave input
> 0.5
Differential Input Slew Rate
Common-Mode Voltage
VCOM
AC-coupled
VP-P
> 100
V/µs
AVCLK /
2
V
Differential Input Resistance
RCLK
5
kΩ
Differential Input Capacitance
CCLK
5
pF
Minimum Clock Duty Cycle
45
%
Maximum Clock Duty Cycle
55
%
1.4
ns
CLKP/CLKN, DATACLK TIMING (Figure 4) (Note 9)
CLK to DATACLK Delay
tD
DATACLK output mode
Data Hold Time
tDH
1.65
ns
Data Setup Time
tDS
-0.65
ns
SERIAL-PORT INTERFACE TIMING (Figure 3) (Note 9)
SCLK Frequency
fSCLK
10
MHz
CS Setup Time
tSS
2.5
ns
Input Hold Time
tSDH
0
ns
Input Setup Time
tSDS
4.5
Data Valid Duration
tSDV
6.5
Digital Supply Voltage
DVDD1.8
1.71
1.8
1.89
V
Digital I/O Supply Voltage
DVDD3.3
3.0
3.3
3.6
V
ns
16.5
ns
POWER SUPPLIES
_______________________________________________________________________________________
5
MAX5898
ELECTRICAL CHARACTERISTICS (continued)
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
ELECTRICAL CHARACTERISTICS (continued)
(DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, modulator off, 2x interpolation, DATACLK output mode, output is
50Ω double-terminated, external reference at 1.25V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C,
unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
Clock Supply Voltage
Analog Supply Voltage
CONDITIONS
MIN
TYP
MAX
UNITS
V
AVCLK
3.135
3.3
3.465
AVDD3.3
3.135
3.3
3.465
AVDD1.8
1.71
1.8
1.89
V
IAVDD3.3
fCLK = 250MHz, 2x interpolation, 0dBFS,
fOUT = 10MHz
111
130
IAVDD1.8
fCLK = 250MHz, 2x interpolation, 0dBFS,
fOUT = 10MHz
27
32
Digital Supply Current
IDVDD1.8
fCLK = 250MHz, 2x interpolation, 0dBFS,
fOUT = 10MHz
229
250
mA
Digital I/O Supply Current
IDVDD3.3
fCLK = 250MHz, 2x interpolation, 0dBFS,
fOUT = 10MHz
9
12
mA
Clock Supply Current
IAVCLK
fCLK = 250MHz, 2x interpolation, 0dBFS,
fOUT = 10MHz
2.3
4
mA
Total Power Dissipation
PTOTAL
fCLK = 250MHz, 2x interpolation, 0dBFS,
fOUT = 10MHz
831
Analog Supply Current
All I/O are static high or
low, bit 2 to bit 4 of
address 00h are set high
Power-Down Current
AVDD3.3
530
AVDD1.8
1
DVDD1.8
26
DVDD3.3
350
AVCLK
AVDD3.3 Power-Supply Rejection
Ratio
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
(Note 10)
PSRRA
mA
µA
2
0.125
%FS/V
All specifications are 100% tested at TA ≥ +25°C. Specifications at TA < +25°C are guaranteed by design and characterization.
Specification is 100% production tested at TA ≥ +25°C.
3.84MHz bandwidth, single carrier.
Excludes data latency.
Measured single-ended into a 50Ω load.
Excludes sin(x)/x rolloff.
Differential voltage swing defined as IVPI + IVNI.
V(CLKN)
VP
VN
V(CLKP)
Note 9: Guaranteed by design and characterization.
Note 10:Parameter defined as the change in midscale output caused by a ±5% variation in the nominal supply voltage.
6
mW
_______________________________________________________________________________________
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
-6dBFS
-0.1dBFS
100
-12dBFS
-0.1dBFS
40
20
20
0
10
20
30
40
50
60
60
-0.1dBFS
50
40
30
20
SPURS MEASURED BETWEEN
0MHz AND 62.5MHz
0
10
20
SPURS MEASURED BETWEEN
62.5MHz AND 125MHz
10
0
30
40
50
0
10
20
30
40
50
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
IN-BAND SFDR vs. OUTPUT FREQUENCY
fDATA = 125Mwps, 2x INTERPOLATION
IN-BAND SFDR vs. OUTPUT FREQUENCY
fDATA = 125Mwps, 4x INTERPOLATION
OUT-OF-BAND SFDR vs. OUTPUT FREQUENCY
fDATA = 125Mwps, 4x INTERPOLATION
70
90
70
80
-0.1dBFS
50
40
30
60
60
-12dBFS
40
20
0
62.5
72.5
82.5
92.5
50
-12dBFS
40
30
20
UPPER SIDEBAND MODULATION
SPURS MEASURED BETWEEN
62.5MHz AND 125MHz
10
-0.1dBFS
-6dBFS
80
SFDR (dBc)
-12dBFS
-6dBFS
100
SFDR (dBc)
60
-0.1dBFS
MAX5898 toc06
80
MAX5898 toc05
-0.1dBFS
-6dBFS
120
MAX5898 toc04
90
20
SPURS MEASURED BETWEEN
0MHz AND 62.5MHz
0
102.5
112.5
0
10
20
SPURS MEASURED BETWEEN
62.5MHz AND 250MHz
10
0
30
40
50
0
10
20
30
40
50
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
IN-BAND SFDR vs. OUTPUT FREQUENCY
fDATA = 125Mwps, 4x INTERPOLATION
IN-BAND SFDR vs. OUTPUT FREQUENCY
fDATA = 125Mwps, 4x INTERPOLATION
TWO-TONE IMD vs. OUTPUT FREQUENCY
fDATA = 125Mwps, NO INTERPOLATION
90
100
MAX5898 toc07
100
-0.1dBFS
-0.1dBFS
90
-12dBFS
80
-6dBFS
70
SFDR (dBc)
-12dBFS
60
50
40
30
60
-6dBFS
50
40
30
20
20
LOWER SIDEBAND MODULATION
SPURS MEASURED BETWEEN
62.5MHz AND 125MHz
10
0
70
80
90
100
LOWER SIDEBAND MODULATION
SPURS MEASURED BETWEEN
125MHz AND 187.5MHz
10
0
110
OUTPUT FREQUENCY (MHz)
120
70
80
90
100
1MHz CARRIER SPACING
-20
TWO-TONE IMD (dBc)
70
0
MAX5898 toc09
OUTPUT FREQUENCY (MHz)
MAX5898 toc08
SFDR (dBc)
-6dBFS
-12dBFS
0
0
SFDR (dBc)
80
70
60
40
-12dBFS
-6dBFS
90
SFDR (dBc)
60
80
100
80
SFDR (dBc)
SFDR (dBc)
80
0UT-OF-BAND SFDR vs. OUTPUT FREQUENCY
fDATA = 125Mwps, 2x INTERPOLATION
MAX5898 toc02
-0.1dBFS
100
120
MAX5898 toc01
120
IN-BAND SFDR vs. OUTPUT FREQUENCY
fDATA = 125Mwps, 2x INTERPOLATION
MAX5898 toc03
SFDR vs. OUTPUT FREQUENCY
fDATA = 125Mwps, NO INTERPOLATION
-40
-60
-6dBFS
-12dBFS
-80
-100
-9dBFS
-120
110
OUTPUT FREQUENCY (MHz)
120
10
15
20
25
30
35
40
CENTER FREQUENCY (MHz)
_______________________________________________________________________________________
7
MAX5898
Typical Operating Characteristics
(DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, DATACLK output mode, external reference, VREFIO = +1.25V,
RLOAD = 50Ω double-terminated, IOUTFS = 20mA, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
-6dBFS
-60
-12dBFS
-80
MAX5898 toc11
0.100
GAIN MISMATCH (dB)
-40
-6dBFS
-60
-12dBFS
-80
-6dBFS
-6dBFS
-120
-120
10
25
40
55
70
85
0
10
35
60
85
110
135
160
-40
-15
10
35
60
CENTER FREQUENCY (MHz)
TEMPERATURE (°C)
EIGHT-TONE POWER RATIO PLOT
fDATA = 125Mwps, 2x INTERPOLATION
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE
2.5
4.0
3.0
2.0
-60
-70
-80
2.0
1.5
INL (LSB)
DNL (LSB)
-50
85
MAX5898 toc15
-40
5.0
MAX5898 toc14
3.0
MAX5898 toc13
-30
1.0
0.5
1.0
0
-1.0
-2.0
-90
0
-100
-110
-0.5
-120
-1.0
SUPPLY CURRENT vs. DAC UPDATE RATE
2x INTERPOLATION, fOUT = 5MHz
300
1.8V TOTAL
250
200
150
3.3V TOTAL
49,152
0
65,536
500
400
1.8V TOTAL
350
300
250
200
150
450
400
3.3V TOTAL
350
250
200
150
50
50
0
0
fDAC (MHz)
300
1.8V TOTAL
300
50
250
65,536
SUPPLY CURRENT vs. DAC UPDATE RATE
8x INTERPOLATION, fOUT = 5MHz
100
200
49,152
SUPPLY CURRENT vs. DAC UPDATE RATE
4x INTERPOLATION, fOUT = 5MHz
100
150
32,768
DIGITAL INPUT CODE
100
100
16,384
DIGITAL INPUT CODE
SUPPLY CURRENT (mA)
350
32,768
450
SUPPLY CURRENT (mA)
400
-5.0
16,384
500
MAX5898 toc16
450
-4.0
0
fCENTER = 35.7MHz, 1MHz TONE SPACING
SPAN = 12.5MHz, AOUT1 THROUGH AOUT8 = -18dBFS
500
-3.0
MAX5898 toc17
OUTPUT POWER (dBm)
100
CENTER FREQUENCY (MHz)
-20
8
0.050
-9dBFS
-100
-9dBFS
0.075
0.025
-12dBFS
-100
fOUT = 22.7MHz
AOUT = -6dBFS
MAX5898 toc18
TWO-TONE IMD (dBc)
-40
1MHz CARRIER SPACING
COMPLEX MODULATION FOR
OUTPUT FREQUENCIES
GREATER THAN 50MHz
-20
TWO-TONE IMD (dBc)
1MHz CARRIER SPACING
COMPLEX MODULATION FOR
OUTPUT FREQUENCIES
GREATER THAN 50MHz
-20
0
MAX5898 toc10
0
MAX5898 toc12
(DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, DATACLK output mode, external reference, VREFIO = +1.25V,
RLOAD = 50Ω double-terminated, IOUTFS = 20mA, TA = +25°C, unless otherwise noted.)
CHANNEL-TO-CHANNEL
TWO-TONE IMD vs. OUTPUT FREQUENCY
TWO-TONE IMD vs. OUTPUT FREQUENCY
GAIN MISMATCH vs. TEMPERATURE
fDATA = 125Mwps, 2x INTERPOLATION
fDATA = 125Mwps, 4x INTERPOLATION
fDATA = 125Mwps, 2x INTERPOLATION
SUPPLY CURRENT (mA)
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
3.3V TOTAL
0
100
200
300
fDAC (MHz)
400
500
100
200
300
fDAC (MHz)
_______________________________________________________________________________________
400
500
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
-120
-140
8x INTERPOLATION
-150
FOUR-CARRIER
ALTERNATE CHANNEL
50
-170
100
200
300
400
500
61.44
92.16
122.88
153.60
0
15.36 30.72 46.08 61.44 76.80 92.16 107.50
fCENTER (MHz)
WCDMA ACLR SPECTRAL PLOT
fDATA = 61.44Mwps, 8x INTERPOLATION
FOUR-CARRIER WCDMA ACLR SPECTRAL PLOT
fDATA = 61.44Mwps, 8x INTERPOLATION
WCDMA ACLR SPECTRAL PLOT
fDATA = 122.88Mwps, 4x INTERPOLATION
MAX5898 toc24
-40
-80
-90
-100
-100
-100
-110
-110
-110
-120
-120
ACLR2 = 70dB
-70
ACLR1 = 68dB
-60
CARRIER = -12dBm
-50
ACLR1 = 68dB
ACLR2 = 71dB
ACLR1 = 71dB
-90
ACLR1 = 72dB
-80
ACLR2 = 74dB
-70
CARRIER = -17dBm
-50
-60
-30
ACLR2 = 70dB
-40
OUTPUT POWER (dBm)
-30
OUTPUT POWER (dBm)
ACLR2 = 77dB
ACLR1 = 76dB
ACLR1 = 77dB
ACLR2 = 78dB
-60
CARRIER = -11dBm
-50
-20
MAX5898 toc23
-20
MAX5898 toc22
-40
-90
30.72
fCENTER (MHz)
-30
-80
40
0
fDAC (MHz)
-20
-70
FOUR-CARRIER
FOUR-CARRIER
ALTERNATE CHANNEL ADJACENT CHANNEL
50
40
-180
70
60
FOUR-CARRIER
ADJACENT CHANNEL
-160
ONE-CARRIER
ADJACENT CHANNEL
80
70
60
ONE-CARRIER
ALTERNATE CHANNEL
90
ACLR (dB)
4x INTERPOLATION
100
ONE-CARRIER
ADJACENT CHANNEL
80
ACLR (dB)
-130
2x INTERPOLATION
-120
fCENTER = 61.44MHz
SPAN = 25.5MHz
fCENTER = 61.44MHz
SPAN = 40.6MHz
fCENTER = 122.88MHz
SPAN = 25.5MHz
FOUR-CARRIER WCDMA ACLR SPECTRAL PLOT
fDATA = 122.88Mwps, 4x INTERPOLATION
MAX5898 toc25
-20
-30
-40
-90
ACLR2 = 63dB
-80
ACLR1 = 63dB
-70
ACLR1 = 64dB
-60
CARRIER = -20dBm
-50
ACLR2 = 65dB
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
ONE-CARRIER
ALTERNATE CHANNEL
90
WCDMA ACLR vs. OUTPUT FREQUENCY
fDATA = 76.8Mwps, 4x INTERPOLATION
MAX5898 toc20
-110
NOISE DENSITY (dBFS/Hz)
100
MAX5898 toc19
-100
WCDMA ACLR vs. OUTPUT FREQUENCY
fDATA = 122.88Mwps, 4x INTERPOLATION
MAX5898 toc21
NOISE DENSITY vs. DAC UPDATE RATE
fOUT = 16MHz, AOUT = -12dBFS, 10MHz OFFSET
-100
-110
-120
fCENTER = 122.88MHz
SPAN = 40.6MHz
_______________________________________________________________________________________
9
MAX5898
Typical Operating Characteristics (continued)
(DVDD1.8 = AVDD1.8 = 1.8V, AVCLK = AVDD3.3 = DVDD3.3 = 3.3V, DATACLK output mode, external reference, VREFIO = +1.25V,
RLOAD = 50Ω double-terminated, IOUTFS = 20mA, TA = +25°C, unless otherwise noted.)
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
MAX5898
Pin Description
PIN
NAME
1
CLKP
2
CLKN
3
N.C.
4
DATACLKP
5
DATACLKN
FUNCTION
Noninverting Differential Clock Input. Internally biased to AVCLK / 2.
Inverting Differential Clock Input. Internally biased to AVCLK / 2.
Internally Connected. Do not connect.
LVDS Data Clock Input/Output. External 100Ω termination to DATACLKN required.
Complementary LVDS Data Clock Input/Output. External 100Ω termination to DATACLKP required.
6, 21, 30, 37
DVDD1.8
Digital Power Supply. Accepts a 1.71V to 1.89V supply range. Bypass each pin to ground with a
0.1µF capacitor as close to the pin as possible.
7
SELIQN
Complementary LVDS Channel Select Input. Set SELIQN low and SELIQP high to direct data to
the channel. Set SELIQP low and SELIQN high to direct data to the channel. Internal 110Ω
termination to SELIQP.
8
SELIQP
LVDS Channel Select Input. Set SELIQN low and SELIQP high to direct data to the channel. Set
SELIQP low and SELIQN high to direct data to the channel. Internal 110Ω termination to SELIQN.
10
9
D15N
Complementary LVDS Data Bit 15 (MSB). Internal 110Ω termination to D15P.
10
D15P
LVDS Data Bit 15 (MSB). Internal 110Ω termination to D15N.
11
D14N
Complementary LVDS Data Bit 14. Internal 110Ω termination to D14P.
12
D14P
LVDS Data Bit 14. Internal 110Ω termination to D14N.
13
D13N
Complementary LVDS Data Bit 13. Internal 110Ω termination to D13P.
14
D13P
LVDS Data Bit 13. Internal 110Ω termination to D13N.
15
D12N
Complementary LVDS Data Bit 12. Internal 110Ω termination to D12P.
16
D12P
LVDS Data Bit 12. Internal 110Ω termination to D12N.
17
D11N
Complementary LVDS Data Bit 11. Internal 110Ω termination to D11P.
18
D11P
LVDS Data Bit 11. Internal 110Ω termination to D11N.
19
D10N
Complementary LVDS Data Bit 10. Internal 110Ω termination to D10P.
20
D10P
LVDS Data Bit 10. Internal 110Ω termination to D10N.
22
D9N
Complementary LVDS Data Bit 9. Internal 110Ω termination to D9P.
23
D9P
LVDS Data Bit 9. Internal 110Ω termination to D9N.
24
D8N
Complementary LVDS Data Bit 8. Internal 110Ω termination to D8P.
25
D8P
LVDS Data Bit 8. Internal 110Ω termination to D8N.
26
D7N
Complementary LVDS Data Bit 7. Internal 110Ω termination to D7P.
27
D7P
LVDS Data Bit 7. Internal 110Ω termination to D7N.
28
D6N
Complementary LVDS Data Bit 6. Internal 110Ω termination to D6P.
29
D6P
LVDS Data Bit 6. Internal 110Ω termination to D6N.
31
D5N
Complementary LVDS Data Bit 5. Internal 110Ω termination to D5P.
32
D5P
LVDS Data Bit 5. Internal 110Ω termination to D5N.
33
D4N
Complementary LVDS Data Bit 4. Internal 110Ω termination to D4P.
34
D4P
LVDS Data Bit 4. Internal 110Ω termination to D4N.
______________________________________________________________________________________
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
PIN
NAME
35
D3N
FUNCTION
Complementary LVDS Data Bit 3. Internal 110Ω termination to D3P.
36
D3P
LVDS Data Bit 3. Internal 110Ω termination to D3N.
38
D2N
Complementary LVDS Data Bit 2. Internal 110Ω termination to D2P.
39
D2P
LVDS Data Bit 2. Internal 110Ω termination to D2N.
40
D1N
Complementary LVDS Data Bit 1. Internal 110Ω termination to D1P.
41
D1P
LVDS Data Bit 1. Internal 110Ω termination to D1N.
42
D0N
Complementary LVDS Data Bit 0 (LSB). Internal 110Ω termination to D0P.
43
D0P
44
DVDD3.3
45
DOUT
LVDS Data Bit 0 (LSB). Internal 110Ω termination to D0N.
I/O Power Supply. Accepts a 3.0V to 3.6V supply range. Bypass with a 0.1µF capacitor as close to
the pin as possible.
Serial-Port Data Output
46
DIN
47
SCLK
Serial-Port Data Input
48
CS
49
RESET
Reset Input. Hold RESET low during power-up.
50
REFIO
Reference Input/Output. Bypass to ground with a 1µF capacitor as close to the pin as possible.
51
DACREF
52
FSADJ
53, 67
AVDD1.8
54, 56, 59, 61,
64, 66
GND
55, 60, 65
AVDD3.3
Analog Power Supply. Accepts a 3.135V to 3.465V supply range. Bypass each pin to GND with a
0.1µF capacitor as close to the pin as possible.
57
OUTQN
Inverting Differential DAC Current Output for Q Channel
58
OUTQP
Noninverting Differential DAC Current Output for Q Channel
62
OUTIN
Inverting Differential DAC Current Output for I Channel
63
OUTIP
Noninverting Differential DAC Current Output for I Channel
68
AVCLK
Clock Power Supply. Accepts a 3.135V to 3.465V supply range. Bypass to ground with a 0.1µF
capacitor as close to the pin as possible.
EP
GND
Serial-Port Clock Input. Data on DIN is latched on the rising edge of SCLK.
Serial-Port Interface Select. Drive CS low to enable serial-port interface.
Current-Set Resistor Return Path. For a 20mA full-scale output current, use a 1.25V external reference
and connect a 2kΩ resistor between FSADJ and DACREF. Internally connected to GND. DO NOT USE
AS AN EXTERNAL GROUND CONNECTION.
Full-Scale Adjust Input. For a 20mA full-scale output current, use a 1.25V external reference and
connect a 2kΩ resistor between FSADJ and DACREF.
Low Analog Power Supply. Accepts a 1.71V to 1.89V supply range. Bypass each pin to GND with
a 0.1µF capacitor as close to the pin as possible.
Ground
Exposed Paddle. Must be connected to GND through a low-impedance path.
______________________________________________________________________________________
11
MAX5898
Pin Description (continued)
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
MAX5898
Functional Diagram
MODULATOR
MUX
MUX
2x
INTERPOLATING
FILTER
MUX
2x
INTERPOLATING
FILTER
2x
INTERPOLATING
FILTER
∑
DIGITAL
OFFSET
ADJUST
DIGITAL
GAIN
ADJUST
OUTIP
∑
IDAC
OUTIN
D0–D15
fDAC
DATA SYNCH
AND DEMUX
DATACLK
I
Q
fIM / 2, fIM / 4
I
Q
DIGITAL
OFFSET
ADJUST
MUX
MUX
MUX
∑
2x
INTERPOLATING
FILTER
2x
INTERPOLATING
FILTER
2x
INTERPOLATING
FILTER
SELIQ
MAX5898
DIGITAL
GAIN
ADJUST
OUTQP
∑
QDAC
OUTQN
fDAC
MUX
MUX
MUX
MUX
/2
/2
/2
/2
CONTROL REGISTERS
fCLK
SERIAL INTERFACE
RESET
DOUT
DIN
CS
SCLK
DACREF
Detailed Description
The MAX5898 dual, 500Msps, high-speed, 16-bit, current-output DAC provides superior performance in communication systems requiring low-distortion analog-signal
reconstruction. The MAX5898 combines two DAC cores
with 8x/4x/2x programmable digital interpolation filters, a
digital quadrature modulator, an SPI-compatible serial
interface for programming the device, and an on-chip
1.2V reference. Individual DAC channel gain and offset
adjustments are available to compensate for downstream
signal-path imbalances. The full-scale output current
range is adjustable from 2mA to 20mA to optimize power
dissipation and gain control.
Each channel contains three selectable interpolating filters making the MAX5898 capable of 2x, 4x, 8x, or no
interpolation, which allows for low input data rates and
high DAC update rates. When operating in 8x interpolation mode, the interpolator increases the DAC conversion
12
CLOCK BUFFERS
AND DIVIDERS
REFERENCE
FSADJ
REFIO
CLKN
CLKP
rate by a factor of eight, providing an eight-fold increase
in separation between the reconstructed waveform spectrum and its first image. The MAX5898 accepts either
two’s complement or offset binary input data format on a
single interleaved LVDS input bus.
The MAX5898 includes modulation modes at fIM / 2 and
fIM / 4, where fIM is the data rate at the input of the modulator. If 2x interpolation is used, this data rate is 2x the
input data rate. If 4x or 8x interpolation is used, this data
rate is 4x the input data rate. Table 1 summarizes the
modulator operating data rates.
The power-down modes can be used to turn off each
DAC’s output current or the entire digital section.
Programming both DACs into power-down simultaneously powers down the digital interpolation filters. Note
that the SPI section is always active.
The analog and digital sections of the MAX5898 have
separate power-supply inputs (AV DD3.3 , AV DD1.8 ,
______________________________________________________________________________________
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
Serial Interface
The SPI-compatible serial interface programs the
MAX5898 registers. The serial interface consists of CS,
DIN, SCLK, and DOUT. Data is shifted into DIN on the
rising edge of SCLK when CS is low. When CS is high,
data presented at DIN is ignored and DOUT is in highimpedance mode. Note: CS must transition high
after each read/write operation. DOUT is the serial
data output for reading registers to facilitate easy
debugging during development. DIN and DOUT can
be connected together to form a 3-wire serial interface
bus or remain separate and form a 4-wire SPI bus.
The serial interface supports two-byte transfer in a
communication cycle. The first byte is a control byte
written to the MAX5898 only. The second byte is a data
byte and can be written to or read from the MAX5898.
When writing to the MAX5898, data is shifted into DIN;
data is shifted out of DOUT in a read operation. Bits 0 to
3 of the control byte are the address bits. These bits set
the address of the register to be written to or read from.
Bits 4 to 6 of the control byte must always be set to 0.
Bit 7 is a read/write bit: 0 for write operation and 1 for
read operation. The most significant bit (MSB) is shifted
in first in default mode. If the serial port is set to LSB-first
mode, both the control byte and data byte are shifted LSB
first. Figures 1 and 2 show the SPI serial-interface operation in the default write and read mode, respectively.
Figure 3 is a timing diagram for the SPI serial interface.
Table 1. Quadrature Modulator Operating Data Rates (fIM is the Data Rate at the Input of
the Modulator)
INTERPOLATION RATE
MODULATION MODE (fLO)
MODULATION FREQUENCY
RELATIVE TO fDAC
MODULATION FREQUENCY
RELATIVE TO fDATA
fIM / 2
fDAC / 2
fDATA / 2
fIM / 4
fDAC / 4
fDATA / 4
fIM / 2
fDAC / 2
fDATA
fIM / 4
fDAC / 4
fDATA / 2
fIM / 2
fDAC / 2
2 x fDATA
1x
2x
4x
8x
fIM / 4
fDAC / 4
fDATA
fIM / 2
fDAC / 4
2 x fDATA
fIM / 4
fDAC / 8
fDATA
CS
SCLK
DIN
0
0
0
0
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
HIGH IMPEDANCE
DOUT
Figure 1. SPI Serial-Interface Write Cycle, MSB-First Mode
______________________________________________________________________________________
13
MAX5898
AVCLK, DVDD3.3, and DVDD1.8), which minimize noise
coupling from one supply to the other. AVDD1.8 and
DVDD1.8 operate from a typical 1.8V supply, and all
other supply inputs operate from a typical 3.3V supply.
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
CS
READ CYCLE N - 1
READ CYCLE N
READ CYCLE N + 1
SCLK
DIN
DOUT
ADDRESS
1 0 0 0 3 2 1 0
HIGH
IMPEDANCE
DATA
IGNORED
ADDRESS
1 0 0 0 3 2 1 0
HIGH
IMPEDANCE
DATA N - 2
DATA
IGNORED
DATA N - 1
ADDRESS
1 0 0 0 3 2 1 0
HIGH
IMPEDANCE
DATA
IGNORED
DATA N
Figure 2. SPI Serial-Interface Read Cycle, MSB-First Mode
tSS
CS
SCLK
tSDH
tSDS
DIN
tSDV
DOUT
Figure 3. SPI Serial-Interface Timing Diagram
14
______________________________________________________________________________________
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
of the registers. The following are descriptions of each
register.
Table 2. MAX5898 Programmable Registers
ADD
BIT 7
BIT 6
0 = MSB first
1 = LSB first
BIT 5
BIT 4
BIT 3
Software Reset
0 = Normal
1 = Reset all
registers
Interpolator
Power-Down
0 = Normal
1 = Power-down
IDAC PowerDown
0 = Normal
1 = Power-down
Third
Interpolation
Filter
Configuration
0 = Lowpass
1 = Highpass
Unused
BIT 2
BIT 1
QDAC PowerDown
0 = Normal
1 = Power-down
Unused
Modulation Mode
(Bit 4, Bit 3)
00 = Modulation off
01 = fIM / 2
10 = fIM / 4
11 = fIM / 4
Mixer Modulation
Mode
0 = Complex
1 = Real
Modulation
Sign
0 = e-jω
1 = e+jω
0 = Input data
latched on
rising clock
edge
1 = Input data
latched on falling
clock edge
Data
Synchronizer
Disable
0 = Enabled
1 = Disabled
Unused
BIT 0
00h
Unused
01h
Interpolation Rate
(Bit 7, Bit 6)
00 = No interpolation
01 = 2x interpolation
10 = 4x interpolation
11 = 8x interpolation
02h
0 = Two’scomplement
input data
1 = Offset
binary input
data
03h
Unused
04h
8-Bit IDAC Fine-Gain Adjustment (see the Gain Adjustment section). Bit 7 is MSB and bit 0 is LSB. Default: 00h
05h
Unused
06h
10-Bit IDAC Offset Adjustment (see the Offset Adjustment section). Bits 7 to 0 of the 06h register are the MSB bits. Bit 1 and bit 0 are the LSB
bits in the 07h register. Default: 000h
Unused
0 = Data clock
output disabled
1 = Data clock
output enabled
Unused
4-Bit IDAC Coarse-Gain Adjustment (see the Gain Adjustment
section). Bit 3 is MSB and bit 0 is LSB. Default: Fh
08h
IDAC IOFFSET
IDAC Offset
Direction
Adjustment
0 = Current on
Unused
Bit 1
OUTIN
(see the 06h
1 = Current on
register)
OUTIP
8-Bit QDAC Fine-Gain Adjustment (see the Gain Adjustment section). Bit 7 is MSB and bit 0 is LSB. Default: 00h
09h
Unused
0Ah
10-Bit QDAC Offset Adjustment (see the Offset Adjustment section). Bits 7 to 0 of the 0Ah register are the MSB bits. Bit 1 and bit 0 are the
LSB bits in the 0Bh register. Default: 000h
0Bh
QDAC
IOFFSET
Direction
0 = Current on
OUTQN
1 = Current on
OUTQP
0Ch
Reserved, do not write to these bits.
07h
IDAC Offset
Adjustment
Bit 0
(see the 06h
register)
4-Bit QDAC Coarse-Gain Adjustment (see the Gain Adjustment
section). Bit 3 is MSB and bit 0 is LSB. Default: Fh
Unused
0Dh
Reserved, do not write to these bits.
0Eh
Reserved, do not write to these bits.
QDAC Offset
Adjustment
Bit 1
(see the 0Ah
register)
QDAC Offset
Adjustment
Bit 0
(see the 0Ah
register)
Conditions in bold are power-up defaults.
______________________________________________________________________________________
15
MAX5898
Programming Registers
Programming its registers with the SPI serial interface
sets the MAX5898 operation modes. Table 2 shows all
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
Address 00h
Bit 6
Logic 0 (default) causes the serial port to use
MSB first address/data format. When set to a
logic 1, the serial port uses LSB first address/
data format.
Bit 5
When set to a logic 1 (default = 0), all registers
reset to their default state (this bit included).
Bit 4
Logic 1 (default = 0) stops the clock to the
digital interpolators. DAC outputs hold last
value prior to interpolator power-down.
Bit 3
IDAC power-down mode. A logic 1 (default = 0)
to this bit shuts down the output current from
the IDAC.
Bit 2
QDAC power-down mode. A logic 1 (default = 0)
to this bit shuts down the output current from
the QDAC.
Note: If both bit 2 and bit 3 are 1, the MAX5898 is in
full-power-down mode, leaving only the serial interface
active.
Address 01h
Bits 7, 6 Configure the interpolation filters according
to the following:
00
1x (no interpolation)
01
2x
10
4x
11
8x (default)
Bit 5
Logic 0 configures FIR3 as a lowpass digital
filter (default). A logic 1 configures FIR3 as a
highpass digital filter.
Bits 4, 3 Configure the modulation frequency according to the following:
00
No modulation
01
10
11
fIM / 2 modulation
fIM / 4 modulation (default)
fIM / 4 modulation
where fIM is the data rate at the input of the
modulator.
16
Bit 2
Configures the modulation mode for either
real or complex (image reject) modulation.
Logic 1 sets the modulator to the real mode
(default). Complex modulation is only available for fIM / 4 modulation.
Bit 1
Quadrature modulator sign inversion. With Ichannel data leading Q-channel data by 90°,
logic 0 sets the complex modulation to be
e-jw (default), cancelling the upper image. A
logic 1 sets the complex modulation to be
e+jw, cancelling the lower image.
Address 02h
Bit 7
Logic 0 (default) configures the data port for
two’s complement. A logic 1 configures the
data ports for offset binary.
Bit 4
Logic 0 (default) sets the internal latches to
latch the data on the rising edge of DATACLK.
A logic 1 sets the internal latches to latch the
data on the falling edge of DATACLK.
Bit 3
Logic 0 (default) configures the DATACLK
pin (pin 4 or pin 5) to be an input. A logic 1
configures the DATACLK pin to be an output.
Bit 2
Logic 0 (default) enables the data synchronizer circuitry. A logic 1 disables the data
synchronizer circuitry.
Address 04h
Bits 7–0 These 8 bits define the binary number for
fine-gain adjustment of the IDAC full-scale
current (see the Gain Adjustment section). Bit
7 is the MSB. Default is all zeros.
Address 05h
Bits 3–0 These four bits define the binary number for
the coarse-gain adjustment of the IDAC fullscale current (see the Gain Adjustment section). Bit 3 is the MSB. Default is all ones.
Address 06h, Bits 7–0; Address 07h, Bit 1 and Bit 0
These 10 bits represent a binary number that
defines the magnitude of the offset added to
the IDAC output (see the Offset Adjustment
section). Default is all zeros.
______________________________________________________________________________________
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
These 10 bits represent a binary number that
defines the magnitude of the offset added to
the QDAC output (see the Offset Adjustment
section). Default is all zeros.
Address 0Bh
Bit 7
Logic 0 (default) adds the 10 bits offset to
OUTQN. A logic 1 adds the 10 bits offset to
OUTQP.
Offset Adjustment
Offset adjustment is achieved by adding a digital code to
the DAC inputs. The code OFFSET (see equation below),
as stored in the relevant control registers, has a range
from 0 to 1023 and a sign bit. The applied DAC offset
is four times the code stored in the register, providing an
offset adjustment range of ±4092 LSB codes. The resolution is 4 LSB.
IOFFSET =
4 × OFFSET
216
× IOUTFS
Gain Trim
Gain adjustment is peformed by varying the full-scale
current according to the following formula:
⎡⎛ 3 × IREF ⎞ ⎛ COARSE + 1⎞ ⎛ 3 × IREF ⎞ ⎛ FINE ⎞ ⎤ ⎛ 1024 ⎞
IOUTFS = ⎢⎜
⎟ −⎜
⎟⎥ ⎜
⎟
⎟⎜
⎟⎜
⎠ ⎝ 32 ⎠ ⎝ 256 ⎠ ⎦ ⎝ 24 ⎠
⎠⎝
4
16
⎣⎝
where IREF is the reference current (see the Reference
Input/Output section). COARSE is the register content
of registers 05h and 09h for the I and Q channel,
respectively. FINE is the register content of register 04h
and 08h for the I and Q channel, respectively. The
range of COARSE is from 0 to 15, with 15 being the
default. The range for FINE is from 0 to 255 with 0
being the default. The gain can be adjusted in steps of
approximately 0.01dB.
Data Input Port
The MAX5898 captures input data on a single LVDS
port (D15P/N–D0P/N). The channel for the input data is
determined through the state of SELIQP/SELIQN. When
SELIQP is set to logic-high and SELIQN is set to logiclow the input data is presented to the I channel. Setting
SELIQP to logic-low and SELIQN to logic-high presents
the input data to the Q channel.
The MAX5898 control registers can be programmed to
allow either signed or unsigned binary format (bit 7,
address 02h) data. Table 3 shows the corresponding DAC
output levels when using signed or unsigned data modes.
Table 3. DAC Output Code Table
DIGITAL INPUT CODE
OFFSET
BINARY
(UNSIGNED)
TWO'S
COMPLEMENT
(SIGNED)
0000 0000 0000 0000 1000 0000 0000 0000
OUT_P
OUT_N
0
IOUTFS
I
/ IOUTFS /
0111 1111 1111 1111 0000 0000 0000 0000 OUTFS
2
2
1111 1111 1111 1111 0111 1111 1111 1111 IOUTFS
0
Data Synchronization Modes
Data synchronization circuitry is provided to allow operation with an input data clock. The data clock must be
frequency locked to the DAC clock (f DAC), but can
have arbitrary phase with respect to the DAC clock.
The synchronization circuitry allows for phase jitter on
the input data clock of up to ±1 data clock cycles.
Synchronization is initially established when the reset
pin is asynchronously deasserted and the input data
clock has been running for at least four clock cycles.
Subsequently, the MAX5898 monitors the phase relationship and detects if the phase drifts more than ±1
data clock cycle. If this occurs, the synchronizer automatically re-establishes synchronization. However, during the resynchronization phase, up to 8 data words
may be lost or repeated.
Bit 2 of register 02h disables or enables (default) the
automatic data clock phase detection. Disabling the
data synchronization circuitry requires the data clock
and the DAC clock phase to be locked.
______________________________________________________________________________________
17
MAX5898
Address 07h
Bit 7
Logic 0 (default) adds the 10 bits offset current to OUTIN. A logic 1 adds the 10 bits offset current to OUTIP.
Address 08h
Bits 7–0 These 8 bits define the binary number for
fine-gain adjustment of the QDAC full-scale
current (see the Gain Adjustment section). Bit
7 is the MSB. Default is all zeros.
Address 09h
Bits 3–0 These four bits define the binary number for
the coarse-gain adjustment of the QDAC fullscale current (see the Gain Adjustment section). Bit 3 is the MSB. Default is all ones.
Address 0Ah, Bits 7–0; Address 0Bh, Bit 1 and Bit 0
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
DATACLK Modes
The MAX5898 employs a differential LVDS DATACLK
located at pins 4 and 5. The DATACLK can be configured as either an input or as an output (bit 3, address
02h). If DATACLK is configured as an output, it is frequency-divided from the CLKP/CLKN input, depending
on the operating mode, see Table 4.
The MAX5898 can be configured to latch the input
data on either the rising edge or falling edge of the
DATACLK signal (bit 4, address 02h). Figure 4 shows
the timing requirements between the DATACLK signal
and the input data bus with latching on the rising edge.
Table 4. Clock Frequency Ratios in
Various Modes
INTERPOLATION
RATE
fDATA:fCLK
fDAC:fCLK
1x
1:1
1:2
2x
1:1
1:1
4x
1:2
1:1
8x
1:4
1:1
CLKP–CLKN
DATACLKP–DATACLKN
tD
tDS
tDH
D0–D15
SELIQ
Figure 4. Data-Input Timing Diagram
18
______________________________________________________________________________________
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
ter is located after the modulator. In the 8x interpolation
mode, the last filter (FIR3) can be configured as lowpass or highpass (bit 5, address 01h) to select the
lower or upper sideband from the modulation output.
The frequency responses of these three filters are plotted in Figures 5–8.
0
0
-20
-20
PASSBAND DETAIL
0
-0.0002
-60
-0.0004
0.3
0.2
0.1
0
0.4
PASSBAND DETAIL
-40
GAIN (dBFS)
GAIN (dBFS)
-40
0
-0.0002
-60
-0.0004
0
-80
-80
-100
-100
0.1
0.2
0.3
2.0
2.5
0.4
-120
-120
0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
0.5
1.0 1.5
3.0 3.5
4.0
fOUT - NORMALIZED TO INPUT DATA RATE
fOUT - NORMALIZED TO INPUT DATA RATE
Figure 5. Interpolation Filter Frequency Response, 2x
Interpolation Mode
Figure 6. Interpolation Filter Frequency Response, 4x
Interpolation Mode
0
0
-20
-20
PASSBAND DETAIL
-40
0
GAIN (dBFS)
GAIN (dBFS)
MAX5898
Interpolating Filter
The MAX5898 features three cascaded FIR half-band
filters. The interpolating filters are enabled or disabled
in combinations to support 1x (no interpolation), 2x, 4x,
or 8x interpolation. Bits 7 and 6 of register 01h set the
interpolation rate (see Table 2). The last interpolation fil-
-0.0002
-60
-0.0004
0.1
0
0.2
0.3
0.4
-40
0
-0.0002
-60
-0.0004
-80
-80
-100
-100
-120
0
PASSBAND DETAIL
-0.0002
3.6
3.8
4.0
4.2
4.4
-0.0004
-120
0
1
2
3
4
5
6
7
8
fOUT - NORMALIZED TO INPUT DATA RATE
Figure 7. Interpolation Filter Frequency Response, 8x
Interpolation Mode (FIR3 Lowpass Mode)
0
1
2
3
4
5
6
7
8
fOUT - NORMALIZED TO INPUT DATA RATE
Figure 8. Interpolation Filter Frequency Response, 8x
Interpolation Mode (FIR3 Highpass Mode)
______________________________________________________________________________________
19
0
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
The programmable interpolation filters multiply the
MAX5898 input data rate by a factor of 2x, 4x, or 8x to
separate the reconstructed waveform spectrum and the
DAC image. The original spectral images, appearing at
around multiples of the input data rate, are attenuated
by the internal digital filters. This feature provides three
benefits:
1) Image separation reduces complexity of analog
reconstruction filters.
INPUT
SPECTRUM
AND FIRST
FILTER
RESPONSE
SIGNAL
OUTPUT
SPECTRUM
OF THE
FIRST
FILTER
4fS
5fS
6fS
7fS
8fS
2x INTERPOLATION
3fS
4fS
5fS
2fS
6fS
7fS
8fS
6fS
7fS
8fS
FILTER
RESPONSE
IMAGE
3fS
4fS
5fS
SIGNAL
4x INTERPOLATION
IMAGE
2fS
3fS
4fS
SIGNAL
2fS
3fS
5fS
6fS
7fS
8fS
5fS
6fS
7fS
8fS
IMAGE
FILTER
RESPONSE
fS
OUTPUT
SPECTRUM
OF THE
THIRD
FILTER
2fS
SIGNAL
fS
INPUT
SPECTRUM
AND THIRD
FILTER
RESPONSE
3fS
NO INTERPOLATION
IMAGE
fS
OUTPUT
SPECTRUM
OF THE
SECOND
FILTER
2fS
SIGNAL
fS
INPUT
SPECTRUM
AND
SECOND
FILTER
RESPONSE
Figure 9 illustrates a practical example of the benefits
when using the MAX5898 in 2x, 4x, and 8x interpolation
modes with the third filter configured as a lowpass filter.
With no interpolation filter, the first image signal appears
in the second Nyquist zone between fS / 2 and fS. The first
interpolating filter removes this image. In fact, all of the
FILTER
RESPONSE
IMAGE
fS
2) Lower input data rates eliminate board-level highspeed data transmission.
3) Sin(x)/x rolloff is reduced over the effective bandwidth.
4fS
SIGNAL
8x INTERPOLATION
IMAGE
fS
2fS
3fS
4fS
5fS
6fS
7fS
8fS
Figure 9. Spectral Representation of Interpolating Filter Responses (Output Frequencies are Relative to the Data Input Frequency, fS)
20
______________________________________________________________________________________
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
INPUT
SPECTRUM
AND FIRST
FILTER
RESPONSE
SIGNAL
FILTER
RESPONSE
IMAGE
fS
OUTPUT
SPECTRUM
OF THE
FIRST
FILTER
2fS
SIGNAL
SIGNAL
FILTER
RESPONSE
4fS
2x INTERPOLATION
3fS
4fS
3fS
4fS
IMAGE
2fS
SIGNAL
4x INTERPOLATION
IMAGE
fS
OUTPUT
SPECTRUM
OF THE
MODULATOR
3fS
2fS
fS
OUTPUT
SPECTRUM
OF THE
SECOND
FILTER
NO INTERPOLATION
IMAGE
fS
INPUT
SPECTRUM
AND
SECOND
FILTER
RESPONSE
10fS, etc. Finally, the third filter removes images at 4fS,
12fS, 20fS, etc. Figures 10, 11, and 12 similarly illustrate
the spectral responses when using the interpolating filters
combined with the digital modulator.
LOWER
SIDEBAND
SIGNAL
fS
2fS
3fS
UPPER
SIDEBAND
4fS
IMAGE
2fS
3fS
4fS
FOR COMPLEX MODULATION THE MODULATION SIGN (BIT 1, ADDRESS 01h) SELECTS UPPER OR LOWER SIDEBAND
Figure 10. Spectral Representation of 4x Interpolation Filter with fIM / 4 Modulation (Output Frequencies are Relative to the Data Input
Frequency, fS)
______________________________________________________________________________________
21
MAX5898
images at odd numbers of fS are filtered. At the output of
the first filter, the images are at 2fS, 4fS, etc. This signal is
then passed to the second interpolating filter, which is
similar to the first filter and removes the images at 2fS, 6fS,
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
INPUT
SPECTRUM
AND FIRST
FILTER
RESPONSE
SIGNAL
fS
OUTPUT
SPECTRUM
OF THE
FIRST
FILTER
2fS
SIGNAL
SIGNAL
4fS
5fS
6fS
7fS
8fS
2x INTERPOLATION
3fS
4fS
2fS
5fS
6fS
7fS
8fS
5fS
6fS
7fS
8fS
FILTER
RESPONSE
IMAGE
3fS
4fS
SIGNAL
4x INTERPOLATION
IMAGE
fS
OUTPUT
SPECTRUM
OF THE
MODULATOR
3fS
2fS
fS
OUTPUT
SPECTRUM
OF THE
SECOND
FILTER
NO INTERPOLATION
IMAGE
fS
INPUT
SPECTRUM
AND
SECOND
FILTER
RESPONSE
FILTER
RESPONSE
IMAGE
LOWER
SIDEBAND
2fS
3fS
SIGNAL
UPPER
SIDEBAND
4fS
5fS
6fS
fS
8fS
7fS
8fS
IMAGE
2fS
3fS
4fS
5fS
6fS
SIGNAL
OUTPUT
SPECTRUM
OF THE
THIRD
FILTER
7fS
FILTER RESPONSE
SIGNAL
fS
8fS
IMAGE
fS
2fS
3fS
4fS
5fS
6fS
FOR COMPLEX MODULATION THE MODULATION SIGN (BIT 1, ADDRESS 01h) SELECTS UPPER OR LOWER SIDEBAND
INPUT
SPECTRUM
AND THIRD
FILTER
RESPONSE
7fS
8x INTERPOLATION
IMAGE
2fS
3fS
4fS
5fS
6fS
7fS
8fS
Figure 11. Spectral Representation of 8x Interpolation Filter with fIM / 4 Modulation and Lowpass Mode Enabled (Output Frequencies
are Relative to the Data Input Frequency, fS)
22
______________________________________________________________________________________
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
IMAGE
fS
OUTPUT
SPECTRUM
OF THE
FIRST
FILTER
2fS
SIGNAL
2fS
SIGNAL
2fS
5fS
6fS
7fS
8fS
2x INTERPOLATION
3fS
4fS
5fS
6fS
7fS
8fS
6fS
7fS
8fS
FILTER
RESPONSE
3fS
4fS
5fS
SIGNAL
4x INTERPOLATION
IMAGE
fS
OUTPUT
SPECTRUM
OF THE
MODULATOR
4fS
IMAGE
fS
OUTPUT
SPECTRUM
OF THE
SECOND
FILTER
3fS
NO INTERPOLATION
IMAGE
fS
INPUT
SPECTRUM
AND
SECOND
FILTER
RESPONSE
FILTER
RESPONSE
LOWER
SIDEBAND
2fS
3fS
SIGNAL
UPPER
SIDEBAND
4fS
SIGNAL
fS
5fS
6fS
7fS
8fS
5fS
6fS
7fS
8fS
7fS
8fS
IMAGE
fS
2fS
3fS
4fS
MODULATION SIGN (BIT 1, ADDRESS 01h) SELECTS UPPER OR LOWER SIDEBAND
INPUT
SPECTRUM
AND THIRD
FILTER
RESPONSE
FILTER
RESPONSE
IMAGE
2fS
3fS
4fS
5fS
SIGNAL
OUTPUT
SPECTRUM
OF THE
THIRD
FILTER
fS
MAX5898
INPUT
SPECTRUM
AND FIRST
FILTER
RESPONSE
SIGNAL
2fS
3fS
6fS
8x INTERPOLATION
IMAGE
4fS
5fS
6fS
7fS
8fS
Figure 12. Spectral Representation of 8x Interpolation Filter with fIM / 4 Modulation and Highpass Mode Enabled (Output Frequencies
are Relative to the Data Input Frequency, fS)
______________________________________________________________________________________
23
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
Digital Modulator
The MAX5898 features digital modulation at frequencies
of fIM / 2 and fIM / 4, where fIM is the data rate at the
input to the modulator. fIM equals fDAC in 1x, 2x, and 4x
interpolation modes. In 8x interpolation mode, fIM equals
fDAC / 2. The output rate of the modulator is always the
same as the input data rate to the modulator, fIM.
In complex modulation mode, data from the second
interpolation filter is frequency-mixed with the on-chip
in-phase and quadrature (I/Q) local oscillator (LO).
Complex modulation provides the benefit of image
sideband rejection.
In the fLO = fIM / 4 mode, real or complex modulation
can be used. The modulator multiplies successive input
data samples by the sequence [1, 0, -1, 0] for a cos(ωt).
The modulator modulates the input signal up to fIM / 4,
creating upper and lower images around fIM / 4. The
quadrature LO sin(ωt) is realized by delaying the cos(ωt)
sequence by one clock cycle. Using complex modulation, complex IF is generated. The complex IF combined
with an external quadrature modulator provides image
rejection. The sign of the LO can be changed to allow
the user to select whether the upper or the lower image
should be rejected (bit 1 of register 01h).
When fIM / 2 is chosen as the LO frequency, the input
signal is multiplied by [-1, 1] on both channels. This produces images around fIM / 2. The complex image-reject
modulation mode is not available for this LO frequency.
I-CHANNEL
INPUT DATA
The outputs of the modulator can be expressed as:
IOD (t) = IID (t) × cos(ωt) − QID (t) × sin(ωt)
QOD (t) = IID (t) × sin(ωt) + QID (t) × cos(ωt)
in complex modulation, e+jwt
IOD (t) = IID (t) × cos(ωt) + QID (t) × sin(ωt)
QOD (t) = IID (t) × sin(ωt) + QID (t) × cos(ωt)
in complex modulation, e-jwt
For real modulation, the outputs of the modulator can
be expressed as:
IOD (t) = IID (t) × cos(ωt)
QOD (t) = QID (t) × cos(ωt)
where ω = 2 x π x fLO.
If more than one MAX5898 is used, their LO phases
can be synchronized by simultaneously releasing
RESET. This sets the MAX5898 to its predefined initial
phase.
Device Reset
The MAX5898 can be reset by holding the RESET pin
low for 10ns. This will program the control registers to
their default values in Table 2. During power-on, RESET
must be held low until all power supplies have stabilized. Alternately, programming bit 5 of address 00h to
a logic-high also resets the MAX5898.
I-CHANNEL
INPUT DATA
∑
cos(ωt)
sin(ωt)
I-CHANNEL
OUTPUT DATA
cos(ωt)
TO
FIR3
sin(ωt)
sin(ωt)
∑
I-CHANNEL
OUTPUT DATA
TO
FIR3
sin(ωt)
∑
Q-CHANNEL
INPUT DATA
∑
Q-CHANNEL
OUTPUT DATA
Q-CHANNEL
OUTPUT DATA
Q-CHANNEL
INPUT DATA
cos(ωt)
cos(ωt)
(a)
(b)
Figure 13. (a) Modulator in Complex Modulation Mode; (b) Modulator in Real Modulation Mode
24
______________________________________________________________________________________
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
Data Clock
The MAX5898 features synchronizers that allow for arbitrary phase alignment between DATACLK and
CLKP/CLKN. The DATACLK causes internal switching in
the MAX5898 and the phase between DATACLK (input
mode) to CLKP/CLKN influences the images at DATACLK.
Figure 14 shows the image level near DATACLK as a
function of the DATACLK (input mode) to CLKP/CLKN
phase at 500Msps, 4x interpolation for a 10MHz, -6dBFS
output signal.
Applications Information
Frequency Planning
Harmonics are often folded down into the band of interest. Specifically, if the DAC outputs a frequency close
to fS / N, the Mth harmonic of the output signal will be
aliased down to:
⎡N − M ⎤
f = fS − M × fOUT = fS ⎢
⎥
⎣ N ⎦
Thus, if N ≈ (M + 1), the Mth harmonic will be close to
the output frequency. SFDR performance of a currentsteering DAC is often dominated by 3rd-order harmonic
distortion. If this is a concern, placing the output signal
at a frequency other than fS / 4 should be considered.
Common to interpolating DACs are images near the
divided clocks. In a DAC configured for 4x interpolation,
this applies to images around fS / 4 and fS / 2. In a DAC
configured for 8x interpolation, this applies to images
around fS / 8, fS / 4, and fS / 2. Most of these images
are not part of the in-band (0 to fDATA / 2) SFDR specification, though they are a consideration for out-of-band
(fDATA / 2 to fDAC / 2) SFDR and may depend on the
relationship of the DATACLK to DAC update clock (see
the Data Clock section). When specifying the output
reconstruction filter for other than baseband signals,
these images should not be ignored.
fS / 4 IMAGES vs. CLKP/CLKN to DATACLK DELAY
fDATA = 125Mwps, 4x INTERPOLATION
-70
fOUT = 10MHz
AOUT = -6dBFS
-75
IMAGE LEVEL (dBc)
System designers need to take the DAC into account
during frequency-planning for high-performance applications. Proper frequency planning can ensure that
optimal system performance is achieved. The
MAX5898 is designed to deliver excellent dynamic performance across wide bandwidths, as required for
communication systems. As with all DACs, some combinations of output frequency and update rate produce
better performance than others.
-80
fS / 4 - fOUT
fS / 4 + fOUT
-85
-90
fS / 4 - fOUT
fS / 4 + fOUT
-95
-100
0
2
4
6
8
CLKP/CLKN DELAY (s)
Figure 14. Effect of CLKP/CLKN to DATACLK Phase on fS / 4
Images
Clock Interface
The MAX5898 features a flexible differential clock input
(CLKP, CLKN) with a separate supply (AV CLK ) to
achieve optimum jitter performance. Use an ultra-low
jitter clock to achieve the required noise density. Clock
jitter must be less than 0.5psRMS to meet the specified
noise density. For that reason, the CLKP/CLKN input
source must be designed carefully. The differential
clock (CLKN and CLKP) input can be driven from a single-ended or a differential clock source. Differential
clock drive is required to achieve the best dynamic
performance from the DAC. For single-ended operation, drive CLKP with a low noise source and bypass
CLKN to GND with a 0.1µF capacitor.
The CLKP and CLKN pins are internally biased to
AVCLK / 2. This allows the user to AC-couple clock
______________________________________________________________________________________
25
MAX5898
Power-Down Mode
The MAX5898 features three power-saving modes.
Each DAC can be individually powered down through
bits 2 and 3 of address 00h. The interpolation filters can
also be powered down through bit 4 of address 00h,
preserving the output level of each DAC (the DACs
remain powered). Powering down both DACs automatically puts the MAX5898 into full power-down, including
the interpolation filters.
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
sources directly to the device without external resistors
to define the DC level. The input resistance of CLKP
and CLKN is 5kΩ.
A convenient way to apply a differential signal is with a
balun transformer as shown in Figure 15. Alternatively,
these inputs may be driven from a CMOS-compatible
clock source, however it is recommended to use sine-
wave or AC-coupled differential ECL/PECL drive for best
dynamic performance.
Output Interface (OUTI, OUTQ)
The MAX5898 outputs complementary currents (OUTIP,
OUTIN, OUTQP, and OUTQN) that can be utilized in a
differential configuration. Load resistors convert these
two output currents into a differential output voltage.
The differential output between OUTIP (OUTQP) and
OUTIN (OUTQN) can be converted to a single-ended
output using a transformer or a differential amplifier.
Figure 16 shows a typical transformer-based application circuit for generation of IF output signals. In this
configuration, the MAX5898 operates in differential
mode, which reduces even-order harmonics, and
increases the available output power. Pay close attention to the transformer core saturation characteristics
when selecting a transformer. Transformer core saturation can introduce strong second harmonic distortion,
especially at low output frequencies and high signal
amplitudes. It is recommended to connect the transformer center tap to ground.
100nF
CLKP
SINGLE-ENDED
IINPUT
MINI-CIRCUITS
ADTL1-12
24.9Ω
MAX5898
1:1 RATIO
24.9Ω
100nF
CLKN
Figure 15. Single-Ended-to-Differential Clock Conversion Using
a Balun Transformer
50Ω
1:1
OUTIP
IDAC
VIOUT, SINGLE-ENDED
100Ω
16
1:1
OUTIN
50Ω
MAX5898
50Ω
1:1
OUTQP
QDAC
VQOUT, SINGLE-ENDED
100Ω
16
1:1
OUTQN
50Ω
Figure 16. Differential-to-Single-Ended Conversion Using Wideband RF Transformers
26
______________________________________________________________________________________
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
25Ω
OUTIP
IDAC
50Ω
16
OUTIN
25Ω
MAX5898
25Ω
OUTQP
QDAC
50Ω
16
OUTQN
25Ω
Reference Input/Output
The MAX5898 supports operation with the on-chip 1.2V
bandgap reference or an external reference voltage
source. REFIO serves as the input for an external, lowimpedance reference source, and as the output if the
DAC is operating with the internal reference.
For stable operation with the internal reference, REFIO
should be decoupled to GND with a 1µF capacitor.
REFIO must be buffered with an external amplifier,
if heavy loading is required, due to its 10kΩ output
resistance.
Alternatively, apply a temperature-stable external reference to REFIO (Figure 18). The internal reference is overdriven by the external reference. For improved accuracy
and drift performance, choose a fixed output voltage reference such as the MAX6520 bandgap reference.
The MAX5898’s reference circuit (Figure 19) employs a
control amplifier, designed to regulate the full-scale
current IOUT for the differential current outputs of the
DAC. The output current can be calculated as:
IOUTFS = 32 x IREF x 65,535 / 65,536
where IREF is the reference output current (IREF = VREFIO /
RSET) and IOUTFS is the full-scale output current of the
DAC. Located between FSADJ and DACREF, RSET is the
reference resistor, which determines the amplifier’s output
current for the DAC. See Table 5 for a matrix of different
IOUTFS and RSET selections.
Power Supplies, Bypassing,
Decoupling, and Layout
Grounding and power-supply decoupling strongly influence the MAX5898 performance. Unwanted digital
crosstalk can couple through the input, reference,
power-supply, and ground connections, which can
affect dynamic specifications like signal-to-noise ratio
or spurious-free dynamic range. In addition, electromagnetic interference (EMI) can either couple into or
be generated by the MAX5898. Observe the grounding
and power-supply decoupling guidelines for highspeed, high-frequency applications. Follow the powersupply and filter configuration guidelines to achieve
optimum dynamic performance.
Using a multilayer printed-circuit board (PCB) with separate ground and power-supply planes, run high-speed
signals on lines directly above the ground plane. Since
the MAX5898 has separate analog and digital sections,
the PCB should include separate analog and digital
Figure 17. DC-Coupled Differential Output Configuration
______________________________________________________________________________________
27
MAX5898
If a transformer is not used, the outputs must have a
resistive termination to ground. Figure 17 shows the
MAX5898 output configured for differential DC-coupled
mode. The DC-coupled configuration can be used to
eliminate waveform distortion due to highpass filter
effects. Applications include communication systems
employing analog quadrature upconverters and requiring a high-speed DAC for baseband I/Q synthesis.
If a single-ended DC-coupled unipolar output is desirable, OUTIP (OUTQP) should be selected as the output, and connect OUTIN (OUTQN) to ground. Using
the MAX5898 output single-ended is not recommended
because it introduces additional noise and distortion.
The distortion performance of the DAC also depends
on the load impedance. The MAX5898 is optimized for
a 50Ω double termination. It can be used with a transformer output as shown in Figure 16 or just one 25Ω
resistor from each output to ground and one 50Ω resistor between the outputs (Figure 17). Higher output termination resistors can be used, as long as each output
voltage does not exceed +1V with respect to GND, but
at the cost of degraded distortion performance and
increased output noise voltage.
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
1.2V
REFERENCE
1.2V
REFERENCE
MAX5898
MAX5898
10kΩ
10kΩ
EXTERNAL
1.25V
REFERENCE
REFIO
REFIO
1μF
1μF
FSADJ
FSADJ
CURRENTSOURCE
ARRAY DAC
IREF
RSET
CURRENTSOURCE
ARRAY DAC
IREF
RSET
DACREF
DACREF
Figure 18. Typical External Reference Circuit
Figure 19. Internal Reference Architecture
Table 5. IOUTFS and RSET Selection Matrix Based on a Typical 1.20V Reference Voltage
FULL-SCALE
CURRENT
IOUTFS (mA)
REFERENCE
CURRENT
IREF (µA)
CALCULATED
1% EIA STD
2
62.50
19.2
19.1
100
5
156.26
7.68
7.5
250
10
312.50
3.84
3.83
500
15
468.75
2.56
2.55
750
20
625.00
1.92
1.91
1000
RSET (kΩ)
OUTPUT VOLTAGE
VIOUTP/N* (mVP-P)
*Terminated into a 50Ω load.
ground sections with only one point connecting the
three planes at the exposed paddle under the
MAX5898. Run digital signals above the digital ground
plane and analog/clock signals above the analog/clock
ground plane. Keep digital signals as far away from
sensitive analog inputs, reference lines, and clock
inputs as practical. Use a symmetric design of clock
input and the analog output lines to minimize 2nd-order
harmonic distortion components, thus optimizing the
dynamic performance of the DAC. Keep digital signal
paths short and run lengths matched to avoid propagation delay and data skew mismatches.
The MAX5898 requires five separate power-supply
inputs for the analog (AVDD1.8 and AVDD3.3), digital
(DVDD1.8 and DVDD3.3), and clock (AVCLK) circuitry.
28
Decouple each voltage supply pin with a separate
0.1µF capacitor as close to the device as possible and
with the shortest possible connection to the appropriate
ground plane. Minimize the analog and digital load
capacitances for optimized operation. Decouple all
power-supply voltages at the point they enter the PCB
with tantalum or electrolytic capacitors. Ferrite beads
with additional decoupling capacitors forming a pi-network could also improve performance.
The exposed paddle MUST be soldered to the ground.
Use multiple vias, an array of at least 4 x 4 vias, directly
under the EP to provide a low thermal and electrical
impedance path for the IC.
______________________________________________________________________________________
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from either a best-straight-line
fit (closest approximation to the actual transfer curve)
or a line drawn between the end points of the transfer
function, once offset and gain errors have been nullified. For a DAC, the deviations are measured at every
individual step.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step height and the ideal value of 1 LSB. A DNL
error specification greater than -1 LSB guarantees a
monotonic transfer function.
Offset Error
The offset error is the difference between the ideal and
the actual offset current. For a DAC, the offset point is
the average value at the output for the two midscale
digital input codes with respect to the full scale of the
DAC. This error affects all codes by the same amount.
Gain Error
A gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
Dynamic Performance
Parameter Definitions
Settling Time
The settling time is the amount of time required from the
start of a transition until the DAC output settles its new
output value to within the specified accuracy.
Noise Spectral Density
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog output (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
maximum SNR can be derived from the DAC’s resolution (N bits):
SNRdB = 6.02dB x N + 1.76dB
However, noise sources such as thermal noise, reference noise, clock jitter, etc., affect the ideal reading.
Therefore, SNR is computed by taking the ratio of the
RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first four
harmonics, and the DC offset.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the RMS amplitude of the carrier
frequency (maximum signal components) to the RMS
value of their next largest distortion component. SFDR
is usually measured in dBc with respect to the carrier
frequency amplitude or in dBFS with respect to the
DAC’s full-scale range. Depending on its test condition,
SFDR is observed within a predefined window or
to Nyquist.
Two-/Four-Tone Intermodulation
Distortion (IMD)
The two-/four-tone IMD is the ratio expressed in dBc (or
dBFS) of the worst 3rd-order (or higher) IMD products to
any output tone.
Adjacent Channel Leakage
Power Ratio (ACLR)
Commonly used in combination with WCDMA, ACLR
reflects the leakage power ratio in dB between the
measured powers within a channel relative to its adjacent channel. ACLR provides a quantifiable method of
determining out-of-band spectral energy and its influence on an adjacent channel when a bandwidth-limited
RF signal passes through a nonlinear device.
The DAC output noise is the sum of the quantization
noise and thermal noise. Noise spectral density is the
noise power in a 1Hz bandwidth, specified in dBFS/Hz.
______________________________________________________________________________________
29
MAX5898
Static Performance Parameter
Definitions
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
Pin Configuration
63 62 61 60 59 58
AVDD1.8
FSADJ
GND
AVDD3.3
GND
OUTQN
OUTQP
GND
AVDD3.3
GND
OUTIN
GND
67 66 65 64
OUTIP
AVDD3.3
AVDD1.8
68
GND
AVCLK
TOP VIEW
57 56 55 54 53 52
EXPOSED PADDLE
CLKP
1
CLKN
2
50 REFIO
N.C.
3
49 RESET
DATACLKP
4
48 CS
DATACLKN
DVDD1.8
5
47 SCLK
6
46 DIN
SELIQN
7
45 DOUT
SELIQP
8
D15N
9
51 DACREF
44 DVDD3.3
MAX5898
43 D0P
D15P 10
42 D0N
D14N 11
41 D1P
D14P 12
D13N 13
40 D1N
D13P 14
38 D2N
D12N 15
37 DVDD1.8
D12P 16
36 D3P
D11N 17
35 D3N
39 D2P
D4P
D4N
D5P
D5N
DVDD1.8
D6P
D6N
D7P
D7N
D8P
D8N
D9P
D9N
DVDD1.8
D10P
D11P
D10N
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
QFN
30
______________________________________________________________________________________
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
68L QFN.EPS
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
1
C
21-0122
2
______________________________________________________________________________________
31
MAX5898
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX5898
16-Bit, 500Msps, Interpolating and Modulating
Dual DAC with Interleaved LVDS Inputs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, 68L QFN, 10x10x0.9 MM
1
C
21-0122
2
____________________Revision History
Pages changed at Rev 1: 1, 2, 4, 5, 27, 28, 31
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
32 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.