TDA4865J; TDA4865AJ Vertical deflection booster Rev. 02 — 3 November 2006 Product data sheet 1. General description The TDA4865J and TDA4865AJ are deflection boosters for use in vertical deflection systems for frame frequencies up to 200 Hz. The TDA4865J needs a separate flyback supply voltage, so the supply voltages are independently adjustable to optimize power consumption and flyback time. For the TDA4865AJ the flyback supply voltage will be generated internally by doubling the supply voltage and therefore a separate flyback supply voltage is not needed. Both circuits provide differential input stages. 2. Features n n n n n Power amplifier with differential inputs Output current up to 3.8 A (p-p) High vertical deflection frequency up to 200 Hz High linear sawtooth signal amplification Flyback generator: u TDA4865J: separate adjustable flyback supply voltage up to 70 V u TDA4865AJ: internally doubled supply voltage (two supply voltages only for DC-coupled outputs) 3. Quick reference data Table 1. Quick reference data Symbol Parameter Min Typ Max Unit VP1 supply voltage 1 Conditions 9 - 35 V VP2 supply voltage 2 VP1 − 1 - 70 V VFB flyback supply voltage of TDA4865J VP1 − 1 - 70 V VP3 flyback generator output voltage of TDA4865AJ 0 - VP1 + 2.2 V Vi(INN) input voltage on pin INN 1.6 - VP1 − 0.5 V Vi(INP) input voltage on pin INP IP1 supply current 1 IVOUT = −1.9 A during scan 1.6 - VP1 − 0.5 V - 6 10 mA TDA4865J; TDA4865AJ NXP Semiconductors Vertical deflection booster Table 1. Quick reference data …continued Symbol Parameter Conditions Min Typ Max Unit IP2 quiescent supply current 2 IVOUT = 0 - 25 60 mA IVOUT(p-p) vertical deflection output current (peak-to-peak value) - - 3.8 A Tamb ambient temperature −20 - +75 °C 4. Ordering information Table 2. Ordering information Type number Package Name Description Version TDA4865J DBS7P plastic DIL-bent-SIL power package; 7 leads (lead length 12/11 mm); exposed die pad SOT524-1 TDA4865AJ 5. Block diagram TDA4865J THERMAL PROTECTION DIFFERENTIAL INPUT STAGE VERTICAL OUTPUT FLYBACK GENERATOR REFERENCE CIRCUIT 7 6 5 4 3 2 1 INP INN VOUT GND VP2 VFB VP1 D1 RS1 CS1 C1 RP R3 C4 C2 deflection coil R4 from deflection controller R2 R1 VN VF VP 001aad296 Fig 1. Block diagram of TDA4865J TDA4865J_TDA4865AJ_2 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 02 — 3 November 2006 2 of 18 TDA4865J; TDA4865AJ NXP Semiconductors Vertical deflection booster TDA4865AJ THERMAL PROTECTION DIFFERENTIAL INPUT STAGE VERTICAL OUTPUT FLYBACK GENERATOR REFERENCE CIRCUIT 7 6 5 4 3 2 1 INP INN VOUT GND VP2 VP3 VP1 RS1 CS1 CF D1 RP R3 C2 deflection coil R5 C1 from deflection controller R2 R6 R1 VN VP 001aad297 Fig 2. Block diagram of TDA4865AJ 6. Pinning information 6.1 Pinning VP1 1 VP1 1 VFB 2 VP3 2 VP2 3 VP2 3 GND 4 GND 4 VOUT 5 VOUT 5 INN 6 INN 6 INP 7 INP 7 TDA4865J 001aad298 Fig 3. Pin configuration for DBS7P (TDA4865J) TDA4865J_TDA4865AJ_2 Product data sheet TDA4865AJ 001aad299 Fig 4. Pin configuration for DBS7P (TDA4865AJ) © NXP B.V. 2006. All rights reserved. Rev. 02 — 3 November 2006 3 of 18 TDA4865J; TDA4865AJ NXP Semiconductors Vertical deflection booster 6.2 Pin description Table 3. Symbol Pin description Pin Description TDA4865J TDA4865AJ VP1 1 1 positive supply voltage 1 VFB 2 - flyback supply voltage VP3 - 2 flyback generator output VP2 3 3 supply voltage 2 for vertical output GND 4 4 ground or negative supply voltage VOUT 5 5 vertical output INN 6 6 inverted input of differential input stage INP 7 7 non-inverted input of differential input stage 7. Functional description Both the TDA4865J and TDA4865AJ consist of a differential input stage, a vertical output stage, a flyback generator, a reference circuit and a thermal protection circuit. The TDA4865J operates with a separate flyback supply voltage (see Figure 1) while the TDA4865AJ generates the flyback voltage internally by doubling the supply voltage (see Figure 2). 7.1 Differential input stage The differential sawtooth input current signal (from the deflection controller) is connected to the inputs (inverted signal to pin INN and non-inverted signal to pin INP). The vertical feedback signal is superimposed on the inverted signal on pin INN. 7.2 Vertical output and thermal protection The vertical output stage is a quasi-complementary class-B amplifier with a high linearity. The output stage is protected against thermal overshoots. For a junction temperature of Tj > 150 °C the protection will be activated and will reduce the deflection current (IVOUT). 7.3 Flyback generator The flyback generator supplies the vertical output stage during flyback. The TDA4865J is used with a separate flyback supply voltage to achieve a short flyback time with minimized power dissipation. The TDA4865AJ needs a capacitor (CF) connected between pins VP3 and VP2 (see Figure 2). Capacitor CF is charged during scan, using the external diode D1 and resistor R5. During flyback the cathode of capacitor CF is connected to the positive supply voltage and the flyback voltage is then twice the supply voltage. For the TDA4865AJ the resistor R6 in the positive supply line can be used to reduce the power consumption. TDA4865J_TDA4865AJ_2 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 02 — 3 November 2006 4 of 18 TDA4865J; TDA4865AJ NXP Semiconductors Vertical deflection booster In parallel with the deflection coil a damping resistor RP and an RC combination (RS1 = 5.6 Ω and CS1 = 100 nF) are needed. Furthermore, another additional RC combination (RS2 = 5.6 Ω and CS2 = 47 nF to 150 nF) can be used to minimize the noise effect and the flyback time (see Figure 7 and Figure 8). 8. Internal circuitry Table 4. Internal circuits Symbol Pin Equivalent circuit TDA4865J VP1 1 VFB 2 VP2 3 GND 4 VOUT 5 INN 6 INP 7 INP INN 7 6 VOUT 5 GND VP2 VFB VP1 4 3 2 1 TDA4865J 001aad300 TDA4865AJ VP1 1 VP3 2 VP2 3 GND 4 VOUT 5 INN 6 INP 7 INP INN 7 6 VOUT 5 GND VP2 VP3 VP1 4 3 2 1 TDA4865AJ 001aad301 TDA4865J_TDA4865AJ_2 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 02 — 3 November 2006 5 of 18 TDA4865J; TDA4865AJ NXP Semiconductors Vertical deflection booster 9. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages referenced to pin GND; unless otherwise specified. Symbol Parameter Conditions Min Max Unit VP1 supply voltage 1 - 40 V VP2 supply voltage 2 - 70 V VFB flyback supply voltage of TDA4865J - 70 V VP3 flyback generator output voltage of TDA4865AJ 0 VP1 + 3 V Vi(INN) input voltage on pin INN - VP1 V Vi(INP) input voltage on pin INP - VP1 V Vo(VOUT) output voltage on pin VOUT - 72 V IP2 supply current 2 - ±2.0 A Io(VOUT) output current on pin VOUT - ±2.0 A IVFB current during flyback of TDA4865J - ±2.0 A IVP3 current during flyback of TDA4865AJ - ±2.0 A Tstg storage temperature −25 +150 °C Tamb ambient temperature Tj junction temperature Vesd electrostatic discharge voltage [1] [1] Internally limited by thermal protection; will be activated for Tj ≥ 150 °C. [2] Class C according to EIA/JESD22-A115-A. [3] Class 3A according to JESD22-A114C.01. −20 +75 °C [1] - 150 °C machine model [2] −400 +400 V human body model [3] −4000 +4000 V 10. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter [1] thermal resistance from junction to mounting base Rth(j-mb) [1] Conditions Typ Unit 4 K/W To minimize the thermal resistance from mounting base to heat sink [Rth(mb-h)] follow the recommended mounting instruction: screw mounting preferred; torque = 40 Ncm; use heat sink compound; isolation plate increases Rth(mb-h). 11. Characteristics Table 7. Characteristics VP1 = 25 V; Tamb = 25 °C; voltages referenced to pin GND; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies VP1 supply voltage 1 9 - 35 V VP2 supply voltage 2 VP1 − 1 - 70 V VFB flyback supply voltage of TDA4865J VP1 − 1 - 70 V TDA4865J_TDA4865AJ_2 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 02 — 3 November 2006 6 of 18 TDA4865J; TDA4865AJ NXP Semiconductors Vertical deflection booster Table 7. Characteristics …continued VP1 = 25 V; Tamb = 25 °C; voltages referenced to pin GND; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VP3 flyback generator output voltage of IVOUT = −1.9 A TDA4865AJ 0 - VP1 + 2.2 V IP1 supply current 1 during scan - 6 10 mA IP2 quiescent supply current 2 IVOUT = 0 - 25 60 mA - VP1 − 0.5 V Differential input stage Vi(INN) input voltage on pin INN 1.6 Vi(INP) input voltage on pin INP 1.6 - VP1 − 0.5 V Iq(INN) input quiescent current on pin INN - −100 −500 nA Iq(INP) input quiescent current on pin INP - −100 −500 nA Flyback generator IVFB current during flyback of TDA4865J - - ±1.9 A IVP3 current during flyback of TDA4865AJ - - ±1.9 A VVP2-VFB(r) reverse voltage drop during flyback IVOUT = −1 A of TDA4865J IVOUT = −1.25 A - −2 - V - −2.2 - V IVOUT = −1.9 A - −2.7 - V forward voltage drop during flyback IVOUT = 1 A of TDA4865J IVOUT = 1.25 A - 1.5 - V - 1.7 - V - 2.1 - V - −2 - V - −2.2 - V VVP2-VFB(f) IVOUT = 1.9 A VVP3-VP1(r) VVP3-VP1(f) reverse voltage drop during flyback IVOUT = −1 A of TDA4865AJ IVOUT = −1.25 A IVOUT = −1.9 A - −2.7 - V forward voltage drop during flyback IVOUT = 1 A of TDA4865AJ IVOUT = 1.25 A - 1.5 - V - 1.7 - V - 2.1 - V IVOUT = 1.9 A Vertical output stage; see Figure 5 IVOUT vertical deflection output current - - ±1.9 A IVOUT(p-p) vertical deflection output current (peak-to-peak value) - - 3.8 A Vo(sat)n output saturation voltage to ground IVOUT = 1 A Vo(sat)p LIN [1] output saturation voltage to VP2 - 1.3 1.7 V IVOUT = 1.25 A - 1.5 2.3 V IVOUT = 1.9 A - 2.6 3.0 V IVOUT = 1 A −2.3 −2.0 - V IVOUT = 1.25 A −2.8 −2.2 - V IVOUT = 1.9 A −3.5 −2.6 - V - - 1 % [1] non-linearity of output signal Deviation of the output slope at a constant input slope. TDA4865J_TDA4865AJ_2 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 02 — 3 November 2006 7 of 18 TDA4865J; TDA4865AJ NXP Semiconductors Vertical deflection booster input signal on pin INN t input signal on pin INP t VFB(1) output voltage on pin VOUT V P1 GND t deflection current through the coil t 001aab327 (1) VFB for TDA4865J; 2VP1 for TDA4865AJ. Fig 5. Timing diagram 12. Application information VF TDA4865J VP 1N4448 VFB VOUT > 1 kΩ 2.2 Ω guard output HIGH = error 3.3 kΩ BC548 BC556 22 µF vertical output signal 220 kΩ 001aad302 Fig 6. Application diagram with TDA4865J for external guard signal generation TDA4865J_TDA4865AJ_2 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 02 — 3 November 2006 8 of 18 TDA4865J; TDA4865AJ NXP Semiconductors Vertical deflection booster TDA4865J THERMAL PROTECTION DIFFERENTIAL INPUT STAGE VERTICAL OUTPUT FLYBACK GENERATOR REFERENCE CIRCUIT 7 6 5 4 3 2 1 INP INN VOUT GND VP2 VFB VP1 D1 RS1 CS1 5.6 Ω 100 nF CS2(1) R3 from deflection controller RS2 5.6 Ω RP 270 Ω deflection coil 1.8 kΩ R2 R1 0.5 Ω (1 W) BYV27 470 µF 470 µF 470 µF 4.3 Ω VN −8 V 1.8 kΩ VF +50 V VP +9 V 001aad303 Remark: the heat sink of the IC must be isolated against ground of the application (it is connected to pin GND). (1) With CS2 (typical value between 47 nF and 150 nF) the flyback time and the noise behavior can be optimized. Fig 7. Application diagram with TDA4865J TDA4865J_TDA4865AJ_2 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 02 — 3 November 2006 9 of 18 TDA4865J; TDA4865AJ NXP Semiconductors Vertical deflection booster TDA4865AJ THERMAL PROTECTION DIFFERENTIAL INPUT STAGE VERTICAL OUTPUT REFERENCE CIRCUIT 7 6 5 4 3 2 1 INP INN VOUT GND VP2 VP3 VP1 CS2(1) RP 270 Ω RS2 5.6 Ω R3 from deflection controller FLYBACK GENERATOR RS1 CS1 CF 5.6 Ω 100 nF 100 µF D1 470 µF R5 (2) deflection coil BYV27 240 Ω (2 W) 3.9 Ω (2 W) R6 (3) 470 µF 1.8 kΩ R1 R2 0.5 Ω (1 W) 1.8 kΩ VN VP −12.5 V +12.5 V 001aad304 Remark: the heat sink of the IC must be isolated against ground of the application (it is connected to pin GND). (1) With CS2 (typical value between 47 nF and 150 nF) the flyback time and the noise behavior can be optimized. (2) With R5 capacitor CF will be charged during scan and the value (typical value between 150 Ω and 270 Ω) depends on Idefl, tflb and CF. (3) R6 reduces the power dissipation of the IC. The maximum possible value depends on the application. Fig 8. Application diagram with TDA4865AJ 12.1 Example for both TDA4865J and TDA4865AJ Table 8. Values given from application Symbol Value Unit Idefl(max)(M) 1.6 (peak value) A Ldeflcoil 10 mH Rdeflcoil 4 Ω RP 270 Ω R1 0.5 Ω R2 1.8 kΩ R3 1.8 kΩ VF[1] 50 V Tamb 50 °C Tdeflcoil 75 °C Rth(j-mb) 4 K/W Rth(mb-h) 0.5 K/W Rth(h-a) 2 K/W [1] Flyback voltage measured against 0 V; for TDA4865J only. TDA4865J_TDA4865AJ_2 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 02 — 3 November 2006 10 of 18 TDA4865J; TDA4865AJ NXP Semiconductors Vertical deflection booster Table 9. Calculated values Symbol Value Unit TDA4865J TDA4865AJ VP1 8 15 V VN −13 −15 V Ptot 8.5 12.1 W Pdefl 3.85 3.85 W PIC 4.65 8.25 W Rth(tot)(max) 12.9 7.27 K/W Tj(max)[1] 93 103.6 °C tflb 650 720 µs [1] With a heat sink of 2 K/W. VP1, VN and VFB are referenced to ground of application; voltages are calculated with +10 % tolerances. The calculation formulae for supply voltages are as follows: V P1 = – V o ( sat ) p + ( R1 + R deflcoil ) × I defl ( max ) – U' L + U D1 (1) V N = V o ( sat )n + ( R1 + R deflcoil ) × I defl ( max ) + U' L (2) where: U’L = Ldeflcoil × 2Idefl(max) × fv fv = vertical deflection frequency UD1 = forward voltage drop across D1 The calculation formulae for power consumption is: P IC = P tot – P defl (3) I defl ( max ) I defl ( max ) P tot = ( V P1 – U D1 ) × --------------------- + V N × ---------------------- + ( V P1 + V N ) × 0.01 + 0.2 4 4 (4) R deflcoil + R1 2 P defl = --------------------------------- × I defl ( max ) 3 (5) where: PIC = power dissipation of the IC Ptot = total power dissipation Pdefl = power dissipation of the deflection coil Calculation formulae for maximum required thermal resistance for the heat sink at Tj(max) = 110 °C: R th ( tot ) = R th ( j-mb ) + R th ( mb-h ) + R th ( h-a ) (6) T j ( max ) – T amb R th ( h-a ) = ----------------------------------- – R th ( j-mb ) – R th ( mb-h ) P IC (7) TDA4865J_TDA4865AJ_2 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 02 — 3 November 2006 11 of 18 TDA4865J; TDA4865AJ NXP Semiconductors Vertical deflection booster Calculation formulae for flyback time (for TDA4865J only): L deflcoil V F + ( R deflcoil + R1 ) × I defl ( max ) t flb = --------------------------------- × ln -------------------------------------------------------------------------------- R deflcoil + R1 V F – ( R deflcoil + R1 ) × I defl ( max ) (8) where: VF measured against 0 V 12.2 Application example for different driver circuits TDA4865J or TDA4865AJ 7 6 5 4 INP INN VOUT GND R2a Vref RS1 CS1 5.6 Ω 100 nF R2b Idefl(max)(P) CS2 Iv(drv) Iv(drv)(max) R3 RS2 5.6 Ω RP 270 Ω deflection coil t Idefl Idefl(max)(N) Iv(drv) Iv(drv)(min) Idefl R1 1Ω t 001aad305 Fig 9. Application for single-ended driver currents with inverting amplifier TDA4865J or TDA4865AJ Iv(drv) Iv(drv)(max) Iv(drv) 7 6 5 4 INP INN VOUT GND RS1 CS1 Iv(drv)(min) 5.6 Ω 100 nF R2 t Idefl Idefl(max)(P) CS2 R3a R3b RS2 5.6 Ω RP 270 Ω deflection coil Idefl t Idefl(max)(N) Vref R1 1Ω 001aad306 Fig 10. Application for single-ended driver currents with non-inverting amplifier TDA4865J_TDA4865AJ_2 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 02 — 3 November 2006 12 of 18 TDA4865J; TDA4865AJ NXP Semiconductors Vertical deflection booster TDA4865J or TDA4865AJ Vdrv Vdrv(max) 7 6 5 4 INP INN VOUT GND RS1 CS1 Vdrv Vdrv(min) 5.6 Ω 100 nF t Idefl Idefl(max)(P) CS2 R3a R3b RS2 5.6 Ω RP 270 Ω deflection coil t Idefl Idefl(max)(N) Vref R1 1Ω 001aad307 Fig 11. Application for single-ended driver voltage output with non-inverting amplifier TDA4865J_TDA4865AJ_2 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 02 — 3 November 2006 13 of 18 TDA4865J; TDA4865AJ NXP Semiconductors Vertical deflection booster 13. Package outline DBS7P: plastic DIL-bent-SIL power package; 7 leads (lead length 12/11 mm); exposed die pad SOT524-1 q1 non-concave x Eh Dh D D1 view B: mounting base side P A2 k q2 B E q L2 L3 L1 L 1 7 Z e1 e Q w M bp 0 5 scale DIMENSIONS (mm are the original dimensions) UNIT A2(2) bp mm c D(1) D1(2) Dh E(1) Eh 2.7 0.80 0.58 13.2 6.2 2.3 0.65 0.48 12.8 5.8 3.5 10 mm v M c e2 m e e1 e2 14.7 3.5 2.54 1.27 5.08 14.3 L k 3 2 L1 L2 L3 m 12.4 11.4 6.7 11.0 10.0 5.5 4.5 3.7 2.8 P Q q q1 q2 3.4 1.15 17.5 4.85 3.8 3.1 0.85 16.3 3.6 v w x 0.8 0.3 0.02 Z(1) 2.92 2.37 Notes 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 2. Plastic surface within circle area D1 may protrude 0.04 mm maximum. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 00-07-03 03-03-12 SOT524-1 Fig 12. Package outline SOT524-1 (DBS7P) TDA4865J_TDA4865AJ_2 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 02 — 3 November 2006 14 of 18 TDA4865J; TDA4865AJ NXP Semiconductors Vertical deflection booster 14. Soldering 14.1 Introduction to soldering through-hole mount packages This text gives a brief insight to wave, dip and manual soldering. Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. 14.2 Soldering by dipping or by solder wave Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 14.3 Manual soldering Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 °C and 400 °C, contact may be up to 5 seconds. 14.4 Package related soldering information Table 10. Suitability of through-hole mount IC packages for dipping and wave soldering Package Soldering method Dipping Wave CPGA, HCPGA - suitable DBS, DIP, HDIP, RDBS, SDIP, SIL suitable suitable[1] PMFP[2] - not suitable [1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. [2] For PMFP packages hot bar soldering or manual soldering is suitable. TDA4865J_TDA4865AJ_2 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 02 — 3 November 2006 15 of 18 TDA4865J; TDA4865AJ NXP Semiconductors Vertical deflection booster 15. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes TDA4865J_TDA4865AJ_2 20061103 Product data sheet - TDA4865_1 Modifications: TDA4865_1 • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors • Legal texts have been adapted to the new company name where appropriate 19921208 Preliminary specification TDA4865J_TDA4865AJ_2 Product data sheet - - © NXP B.V. 2006. All rights reserved. Rev. 02 — 3 November 2006 16 of 18 TDA4865J; TDA4865AJ NXP Semiconductors Vertical deflection booster 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] TDA4865J_TDA4865AJ_2 Product data sheet © NXP B.V. 2006. All rights reserved. Rev. 02 — 3 November 2006 17 of 18 NXP Semiconductors TDA4865J; TDA4865AJ Vertical deflection booster 18. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 8 9 10 11 12 12.1 12.2 13 14 14.1 14.2 14.3 14.4 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Differential input stage . . . . . . . . . . . . . . . . . . . 4 Vertical output and thermal protection . . . . . . . 4 Flyback generator . . . . . . . . . . . . . . . . . . . . . . . 4 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal characteristics. . . . . . . . . . . . . . . . . . . 6 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Application information. . . . . . . . . . . . . . . . . . . 8 Example for both TDA4865J and TDA4865AJ 10 Application example for different driver circuits 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Introduction to soldering through-hole mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Soldering by dipping or by solder wave . . . . . 15 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 15 Package related soldering information . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2006. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 3 November 2006 Document identifier: TDA4865J_TDA4865AJ_2