PHILIPS TDA8351AQ

INTEGRATED CIRCUITS
DATA SHEET
TDA8351AQ
DC-coupled vertical deflection
output circuit
Product specification
Supersedes data of January 1995
File under Integrated Circuits, IC02
1999 Sep 27
Philips Semiconductors
Product specification
DC-coupled vertical deflection output
circuit
TDA8351AQ
FEATURES
GENERAL DESCRIPTION
• Few external components
The TDA8351A is a power circuit for use in 90° and 110°
colour deflection systems for field frequencies of 50 to
120 Hz. The circuit provides a DC driven vertical
deflection output circuit, operating as a highly efficient
class G system.
• Highly efficient fully DC-coupled vertical output bridge
circuit
• Vertical flyback switch
• Guard circuit
• Protection against:
– short-circuit of the output pins (9 and 5)
– short-circuit of the output pins to VP
• Temperature protection
• High EMC immunity because of common mode inputs
• A guard signal in zoom mode.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
DC supply
VP
supply voltage
9
16
25
V
Iq
quiescent supply current
−
30
−
mA
IO(p-p)
output current
(peak-to-peak value)
−
−
3
A
Idiff(p-p)
differential input current
(peak-to-peak value)
−
600
−
µA
Vdiff(p-p)
differential input voltage
(peak-to-peak value)
−
1.8
−
V
−
−
±1.5
A
−
−
50
V
−
−
60
V
Vertical circuit
Flyback switch
IM
peak output current
VFB
flyback supply voltage
t ≤ 1.5 ms
note 1
Thermal data (in accordance with IEC 747-1)
Tstg
storage temperature
−55
−
+150
°C
Tamb
operating ambient temperature
−25
−
+75
°C
Tvj
virtual junction
−
−
150
°C
Note
1. A flyback supply voltage of >50 V up to 60 V is allowed in application. A 220 nF capacitor in series with a 22 Ω resistor
(depending on IO and the inductance of the coil) has to be connected between pin 9 and ground. The decoupling
capacitor of VFB has to be connected between pin 8 and pin 4. This supply voltage line must have a resistance of
33 Ω (see application circuit Fig.5).
1999 Sep 27
2
Philips Semiconductors
Product specification
DC-coupled vertical deflection output
circuit
TDA8351AQ
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TDA8351A
NAME
DESCRIPTION
VERSION
DBS13P
plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm)
SOT141-6
BLOCK DIAGRAM
VP
handbook, full pagewidth
VO(guard)
4
VFB
8
10
VP
CURRENT
SOURCE
VP
TDA8351A
9
VO(A)
I drive(pos)
IS
1
IT
3
IT
I drive(neg)
2
V I(fb)
VP
V
IS
5
VO(B)
7
GND
MGC055
Fig.1 Block diagram.
1999 Sep 27
VO(A)
3
VO(B)
Philips Semiconductors
Product specification
DC-coupled vertical deflection output
circuit
TDA8351AQ
PINNING
SYMBOL
FUNCTIONAL DESCRIPTION
PIN
The vertical driver circuit is a bridge configuration. The
deflection coil is connected between the output amplifiers,
which are driven in opposite phase. An external resistor
(RM) connected in series with the deflection coil provides
internal feedback information. The differential input circuit
is voltage driven. The input circuit has been adapted to
enable it to be used with the TDA9150, TDA9151B,
TDA9160A, TDA9162, TDA8366 and TDA8367 which
deliver symmetrical current signals. An external resistor
(RCON) connected between the differential input
determines the output current through the deflection coil.
The relationship between the differential input current and
the output current is defined by: Idiff × RCON = Icoil × RM.
The output current is adjustable from 0.5 A (p-p) to 3 A
(p-p) by varying RM. The maximum input differential
voltage is 1.8 V. In the application it is recommended that
Vdiff = 1.5 V (typ). This is recommended because of the
spread of input current and the spread in the value of
RCON.
DESCRIPTION
Idrive(pos)
1
input power-stage (positive);
includes II(sb) signal bias
Idrive(neg)
2
input power-stage (negative);
includes II(sb) signal bias
VI(fb)
3
input feedback voltage
VP
4
supply voltage
VO(B)
5
output voltage B
n.c.
6
not connected
GND
7
ground
VFB
8
input flyback supply voltage
VO(A)
9
output voltage A
VO(guard)
10
guard output voltage
n.c.
11
not connected
n.c.
12
not connected
n.c.
13
not connected
The flyback voltage is determined by an additional supply
voltage VFB. The principle of operating with two supply
voltages (class G) makes it possible to fix the supply
voltage VP optimum for the scan voltage and the second
supply voltage VFB optimum for the flyback voltage. Using
this method, very high efficiency is achieved.
handbook, halfpage
I drive(pos)
1
I drive(neg)
2
V I(fb)
3
Vp
4
VO(B)
5
The supply voltage VFB is almost totally available as
flyback voltage across the coil, this being possible due to
the absence of a decoupling capacitor (not necessary,
due to the bridge configuration). Built-in protections are:
n.c.
6
• thermal protection
GND
7
V FB
8
VO(A)
9
• short-circuit protection of the output pins (pins 5 and 9)
TDA8351A
• short-circuit protection of the output pins to VP.
A guard circuit VO(guard) is provided. The guard circuit is
activated at the following conditions:
VO(guard) 10
• during flyback
n.c. 11
n.c. 12
• during short-circuit of the coil and during short-circuit of
the output pins (pins 5 and 9) to VP or ground
n.c. 13
• during open loop
• when the thermal protection is activated.
MGC056
This signal can be used for blanking the picture tube
screen.
The die has been glued to the metal block of the package. If the metal
block is not insulated from the heat sink, the heat sink may only be
connected directly to pin 7.
Fig.2 Pin configuration.
1999 Sep 27
4
Philips Semiconductors
Product specification
DC-coupled vertical deflection output
circuit
TDA8351AQ
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
DC supply
VP
supply voltage
VFB
flyback supply voltage
−
40
V
−
25
V
−
50
V
note 1
−
60
V
note 2
−
3
A
−
52
V
note 1
−
62
V
−
±1.5
A
+150
°C
non-operating
Vertical circuit
IO(p-p)
output current (peak-to-peak value)
VO(A)
output voltage (pin 7)
Flyback switch
IM
peak output current
Thermal data (in accordance with IEC 747-1)
Tstg
storage temperature
−55
Tamb
operating ambient temperature
−25
+75
°C
Tvj
virtual junction temperature
−
150
°C
Rth vj-c
resistance vj-case
−
4
K/W
Rth vj-a
resistance vj-ambient in free air
tsc
short-circuiting time
note 3
−
40
K/W
−
1
hr
Notes
1. A flyback supply voltage of >50 V up to 60 V is allowed in application. A 220 nF capacitor in series with a 22 Ω resistor
(depending on IO and the inductance of the coil) has to be connected between pin 9 and ground. The decoupling
capacitor of VFB has to be connected between pin 8 and pin 4. This supply voltage line must have a resistance of
33 Ω (see application circuit Fig.5).
2. IO maximum determined by current protection.
3. Up to VP = 18 V.
1999 Sep 27
5
Philips Semiconductors
Product specification
DC-coupled vertical deflection output
circuit
TDA8351AQ
CHARACTERISTICS
VP = 17.5 V; VFB = 45 V; fi = 50 Hz; II(sb) = 400 µA; Tamb = 25 °C; measured in test circuit of Fig.3; unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
DC supply
VP
operating supply voltage
VFB
flyback supply voltage
IP
supply current
9.0
−
25
V
VP
−
50
V
note 1
VP
−
60
V
no signal; no load
−
30
55
mA
Idiff = 0.6 mA (p-p);
Vdiff = 1.8 V (p-p);
IO = 3 A (p-p)
19.8
−
−
V
Vertical circuit
VO
output voltage swing (scan)
LE
linearity error
IO = 3 A (p-p); note 2
−
1
3
%
IO = 50 mA (p-p); note 2
−
1
3
%
VO
output voltage swing (flyback)
VO(A) − VO(B)
Idiff = 0.3 mA;
IO = 1.5 A
−
39
−
V
VDF
forward voltage of the internal
efficiency diode (VO(A) − VFB)
IO = −1.5 A;
Idiff = 0.3 mA
−
−
1.5
V
|Ios|
output offset current
Idiff = 0;
II(sb) = 50 to 500 µA
−
−
30
mA
|Vos|
offset voltage at the input of the
feedback amplifier (VI(fb) − VO(B))
Idiff = 0;
II(sb) = 50 to 500 µA
−
−
18
mV
∆VosT
output offset voltage as a function Idiff = 0
of temperature
−
−
72
µV/K
VO(A)
DC output voltage
Idiff = 0; note 3
−
8.0
−
V
Gvo
open-loop voltage gain (V9-5/V1-2) notes 4 and 5
−
80
−
dB
−
80
−
dB
−
0
−
dB
−
40
−
Hz
open loop voltage gain
(V9-5/V3-5; V1-2 = 0)
VR
voltage ratio V1-2/V3-5
fres
frequency response (−3 dB)
note 4
open loop; note 6
GI
current gain (IO/Idiff)
−
5000
−
∆GcT
current gain drift as a function of
temperature
−
−
10−4
K
II(sb)
signal bias current
50
400
500
µA
IFB
flyback supply current
during scan
−
−
100
µA
PSRR
power supply ripple rejection
note 7
−
80
−
dB
VI(DC)
DC input voltage
−
2.7
−
V
VI(CM)
common mode input voltage
II(sb) = 0
0
−
1.6
V
Ibias
input bias current
II(sb) = 0
−
0.1
0.5
µA
IO(CM)
common mode output current
∆II(sb) = 300 µA (p-p);
fi = 50 Hz; Idiff = 0
−
0.2
−
mA
1999 Sep 27
6
Philips Semiconductors
Product specification
DC-coupled vertical deflection output
circuit
SYMBOL
PARAMETER
TDA8351AQ
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Guard circuit
not active;
VO(guard) = 0 V
−
−
50
µA
active; VO(guard) = 3.6 V
1
−
2.5
mA
output voltage on pin 8
IO = 100 µA
4.6
−
5.5
V
allowable voltage on pin 8
maximum leakage
current = 10 µA;
−
−
40
V
output current
IO
VO(guard)
Notes
1. A flyback supply voltage of >50 V up to 60 V is allowed in application. A 220 nF capacitor in series with a 22 Ω resistor
(depending on IO and the inductance of the coil) has to be connected between pin 9 and ground. The decoupling
capacitor of VFB has to be connected between pin 8 and pin 4. This supply voltage line must have a resistance of
33 Ω (see application circuit Fig.5).
2. The linearity error is measured without S-correction and based on the same measurement principle as performed on
the screen. The measuring method is as follows:
Divide the output signal I5 - I9 (VRM) into 22 equal parts ranging from 1 to 22 inclusive. Measure the value of two
succeeding parts called one block starting with part 2 and 3 (block 1) and ending with part 20 and 21 (block 10). Thus
part 1 and 22 are unused. The equations for linearity error for adjacent blocks (LEAB) and linearity error for not
adjacent blocks (LENAB) are given below:
a max – a min
ak – a( k + 1 )
LEAB = --------------------------- ; LENAB = -----------------------------a avg
a avg
3. Referenced to VP.
4. The V values within formulae relate to voltages at or across relative pin numbers, i.e. V9-5/V1-2 = voltage value across
pins 9 and 5 divided by voltage value across pins 1 and 2.
5. V9-4 AC short-circuited.
6. Frequency response V9-5/V3-5 is equal to frequency response V9-5/V1-2.
7. At V(ripple) = 500 mV eff; measured across RM; fi = 50 Hz.
1999 Sep 27
7
Philips Semiconductors
Product specification
DC-coupled vertical deflection output
circuit
TDA8351AQ
handbook, full pagewidth
2.2 kΩ
VFB
VO(guard)
10
8
4
I I(sb)
TDA8351A
signal
bias
9
1
I drive(pos)
R CON
3 kΩ
I drive(neg)
signal
bias
R = 6.0 Ω
FEEDBACK 3
INPUT
I diff
2
R M = 0.7 Ω
5
V
I I(sb)
7
GND
MGC057
Fig.3 Test diagram.
1999 Sep 27
VP
8
Philips Semiconductors
Product specification
DC-coupled vertical deflection output
circuit
TDA8351AQ
APPLICATION INFORMATION
VFB
handbook, full pagewidth
VO(guard)
100
nF
10
8
4
II(sb)
9 VO(A)
1
Idrive(pos)
RCON
3 kΩ
Idrive(neg)
signal
bias
VP
FEEDBACK 3
INPUT
Idiff
VI(fB)
2
5 VO(B)
V
II(sb)
7
GND
VP = 14 V; IO(p-p) = 2.14 A; II(sb) = 400 µA; Idiff(p-p) = 500 µA; VFB = 42 V; tFB = 0.6 ms.
Fig.4 Application diagram.
1999 Sep 27
100
µF
100
nF
TDA8351A
signal
bias
10
µF
10
nF
9
MGL860
I(coil)
deflection coil
AT6005/31
L = 8.63 mH
R = 5.0 Ω
RM = 0.7 Ω
Philips Semiconductors
Product specification
DC-coupled vertical deflection output
circuit
TDA8351AQ
30
handbook, full pagewidth
VFB
VO(guard)
10
8
II(sb)
1
RCON
3 kΩ
signal
bias
4
VP
I(coil)
V
FEEDBACK 3 I(fB)
INPUT
RM = 0.7 Ω
5 VO(B)
Idiff
2
V
II(sb)
7
MGC861
GND
VP = 14 V; IO(p-p) = 2.14 A; II(sb) = 400 µA; Idiff(p-p) = 500 µA; VFB = 60 V; tFB = 0.4 ms.
Fig.5 Application circuit; 50 V ≤ VFB ≤ 60 V.
1999 Sep 27
100
µF
9 VO(A)
Idrive(pos)
Idrive(neg)
10
µF
10
nF
100
nF
TDA8351A
signal
bias
100
nF
10
470 nF
20 Ω
deflection coil
AT6005/31
L = 8.63 mH
R = 5.0 Ω
Philips Semiconductors
Product specification
DC-coupled vertical deflection output
circuit
TDA8351AQ
PACKAGE OUTLINE
DBS13P: plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm)
SOT141-6
non-concave
Dh
x
D
Eh
view B: mounting base side
d
A2
B
j
E
A
L3
L
Q
c
1
v M
13
e1
Z
e
e2
m
w M
bp
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A2
bp
c
D (1)
d
Dh
E (1)
e
e1
e2
Eh
j
L
L3
m
Q
v
w
x
Z (1)
mm
17.0
15.5
4.6
4.2
0.75
0.60
0.48
0.38
24.0
23.6
20.0
19.6
10
12.2
11.8
3.4
1.7
5.08
6
3.4
3.1
12.4
11.0
2.4
1.6
4.3
2.1
1.8
0.8
0.25
0.03
2.00
1.45
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
95-03-11
97-12-16
SOT141-6
1999 Sep 27
EUROPEAN
PROJECTION
11
Philips Semiconductors
Product specification
DC-coupled vertical deflection output
circuit
TDA8351AQ
The total contact time of successive solder waves must
not exceed 5 seconds.
SOLDERING
Introduction to soldering through-hole mount
packages
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (Tstg(max)). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
This text gives a brief insight to wave, dip and manual
soldering. A more in-depth account of soldering ICs can
be found in our “Data Handbook IC26; Integrated Circuit
Packages” (document order number 9398 652 90011).
Wave soldering is the preferred method for mounting of
through-hole mount IC packages on a printed-circuit
board.
Manual soldering
Apply the soldering iron (24 V or less) to the lead(s) of the
package, either below the seating plane or not more than
2 mm above it. If the temperature of the soldering iron bit
is less than 300 °C it may remain in contact for up to
10 seconds. If the bit temperature is between
300 and 400 °C, contact may be up to 5 seconds.
Soldering by dipping or by solder wave
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joints for more than 5 seconds.
Suitability of through-hole mount IC packages for dipping and wave soldering methods
SOLDERING METHOD
PACKAGE
DIPPING
DBS, DIP, HDIP, SDIP, SIL
WAVE
suitable(1)
suitable
Note
1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board.
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of this specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Sep 27
12
Philips Semiconductors
Product specification
DC-coupled vertical deflection output
circuit
TDA8351AQ
NOTES
1999 Sep 27
13
Philips Semiconductors
Product specification
DC-coupled vertical deflection output
circuit
TDA8351AQ
NOTES
1999 Sep 27
14
Philips Semiconductors
Product specification
DC-coupled vertical deflection output
circuit
TDA8351AQ
NOTES
1999 Sep 27
15
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209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
SCA 68
© Philips Electronics N.V. 1999
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
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Printed in The Netherlands
545004/02/pp16
Date of release: 1999
Sep 27
Document order number:
9397 750 06204