PHILIPS 74AUP2G06GN

74AUP2G06
Low-power dual inverter with open-drain output
Rev. 4 — 6 December 2011
Product data sheet
1. General description
The 74AUP2G06 provides two inverting buffers with open-drain output. The output of the
device is an open drain and can be connected to other open-drain outputs to implement
active-LOW wired-OR or active-HIGH wired-AND functions.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features and benefits
 Wide supply voltage range from 0.8 V to 3.6 V
 High noise immunity
 Complies with JEDEC standards:
 JESD8-12 (0.8 V to 1.3 V)
 JESD8-11 (0.9 V to 1.65 V)
 JESD8-7 (1.2 V to 1.95 V)
 JESD8-5 (1.8 V to 2.7 V)
 JESD8-B (2.7 V to 3.6 V)
 ESD protection:
 HBM JESD22-A114F Class 3A. Exceeds 5000 V
 MM JESD22-A115-A exceeds 200 V
 CDM JESD22-C101E exceeds 1000 V
 Low static power consumption; ICC = 0.9 A (maximum)
 Latch-up performance exceeds 100 mA per JESD 78B Class II
 Inputs accept voltages up to 3.6 V
 Low noise overshoot and undershoot < 10 % of VCC
 IOFF circuitry provides partial Power-down mode operation
 Multiple package options
 Specified from 40 C to +85 C and 40 C to +125 C
74AUP2G06
NXP Semiconductors
Low-power dual inverter with open-drain output
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74AUP2G06GW
40 C to +125 C
SC-88
plastic surface-mounted package; 6 leads
SOT363
74AUP2G06GM
40 C to +125 C
XSON6
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1  1.45  0.5 mm
74AUP2G06GF
40 C to +125 C
XSON6
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1  1  0.5 mm
74AUP2G06GN
40 C to +125 C
XSON6
extremely thin small outline package; no leads;
6 terminals; body 0.9  1.0  0.35 mm
SOT1115
74AUP2G06GS
40 C to +125 C
XSON6
extremely thin small outline package; no leads;
6 terminals; body 1.0  1.0  0.35 mm
SOT1202
4. Marking
Table 2.
Marking
Marking code[1]
Type number
74AUP2G06GW
p6
74AUP2G06GM
p6
74AUP2G06GF
p6
74AUP2G06GN
p6
74AUP2G06GS
p6
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1
1A
1Y
6
1A
1
6
1Y
Y
3
2A
2Y
4
2A
3
4
2Y
A
GND
Fig 1.
Logic symbol
74AUP2G06
Product data sheet
mna620
mnb096
mnb095
Fig 2.
IEC logic symbol
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 6 December 2011
Fig 3.
Logic diagram (one driver)
© NXP B.V. 2011. All rights reserved.
2 of 18
74AUP2G06
NXP Semiconductors
Low-power dual inverter with open-drain output
6. Pinning information
6.1 Pinning
74AUP2G06
74AUP2G06
1A
1
6
1A
1
6
1Y
GND
2
5
VCC
74AUP2G06
1Y
GND
2
5
VCC
2A
3
4
2Y
2A
3
4
2Y
001aal425
Fig 4. Pin configuration SOT363
Fig 5. Pin configuration SOT886
1
6
1Y
GND
2
5
VCC
2A
3
4
2Y
001aal426
Transparent top view
Transparent top view
001aal424
1A
Fig 6.
Pin configuration SOT891,
SOT1115 and SOT1202
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
1A, 2A
1, 3
data input
GND
2
ground (0 V)
1Y, 2Y
6, 4
data output
VCC
5
supply voltage
7. Functional description
7.1 Function table
Table 4.
Function table[1]
Input nA
Output nY
L
Z
H
L
[1]
H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
74AUP2G06
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 6 December 2011
© NXP B.V. 2011. All rights reserved.
3 of 18
74AUP2G06
NXP Semiconductors
Low-power dual inverter with open-drain output
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
VI
input voltage
IOK
output clamping current
Conditions
VI < 0 V
[1]
VO < 0 V
VO
output voltage
Active mode and Power-down mode
VO = 0 V to VCC
[1]
Min
Max
Unit
0.5
+4.6
V
50
-
mA
0.5
+4.6
V
50
-
mA
0.5
+4.6
V
IO
output current
-
+20
mA
ICC
supply current
-
+50
mA
IGND
ground current
50
-
mA
Tstg
storage temperature
65
+150
C
-
250
mW
total power dissipation
Ptot
[1]
[2]
Tamb = 40 C to +125 C
[2]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SC-88 package: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For XSON6 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Symbol
Parameter
VCC
supply voltage
VI
input voltage
VO
output voltage
Conditions
Tamb
ambient temperature
t/V
input transition rise and fall rate
Min
Max
Unit
0.8
3.6
V
0
3.6
V
Active mode
0
VCC
V
Power-down mode; VCC = 0 V
0
3.6
V
40
+125
C
0
200
ns/V
Typ
Max
Unit
VCC = 0.8 V to 3.6 V
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
VCC = 0.8 V
0.70  VCC -
-
V
VCC = 0.9 V to 1.95 V
0.65  VCC -
-
V
VCC = 2.3 V to 2.7 V
1.6
-
-
V
VCC = 3.0 V to 3.6 V
2.0
-
-
V
VCC = 0.8 V
-
-
0.30  VCC V
Tamb = 25 C
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
74AUP2G06
Product data sheet
VCC = 0.9 V to 1.95 V
-
-
0.35  VCC V
VCC = 2.3 V to 2.7 V
-
-
0.7
V
VCC = 3.0 V to 3.6 V
-
-
0.9
V
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 6 December 2011
© NXP B.V. 2011. All rights reserved.
4 of 18
74AUP2G06
NXP Semiconductors
Low-power dual inverter with open-drain output
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
VOL
VI = VIH or VIL
LOW-level output voltage
Min
Typ
Max
Unit
IO = 20 A; VCC = 0.8 V to 3.6 V
-
-
0.1
V
IO = 1.1 mA; VCC = 1.1 V
-
-
0.3  VCC
V
IO = 1.7 mA; VCC = 1.4 V
-
-
0.31
V
IO = 1.9 mA; VCC = 1.65 V
-
-
0.31
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.31
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.44
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.31
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.44
V
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
0.1
A
IOZ
OFF-state output current
VI = VIL; VO = 0 V to 3.6 V;
VCC = 0 V to 3.6 V
-
-
0.1
A
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
0.2
A
IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
0.2
A
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
0.5
A
ICC
additional supply current
VI = VCC  0.6 V; IO = 0 A; VCC = 3.3 V
-
-
40
A
CI
input capacitance
VCC = 0 V to 3.6 V; VI = GND or VCC
-
0.8
-
pF
CO
output capacitance
output enabled; VO = GND; VCC = 0 V
-
1.7
-
pF
output disabled; VO = GND; VCC = 0 V
-
1.1
-
pF
VCC = 0.8 V
0.70  VCC -
-
V
VCC = 0.9 V to 1.95 V
0.65  VCC -
-
V
VCC = 2.3 V to 2.7 V
1.6
-
-
V
VCC = 3.0 V to 3.6 V
2.0
-
-
V
VCC = 0.8 V
-
-
0.30  VCC V
VCC = 0.9 V to 1.95 V
-
-
0.35  VCC V
VCC = 2.3 V to 2.7 V
-
-
0.7
V
VCC = 3.0 V to 3.6 V
-
-
0.9
V
IO = 20 A; VCC = 0.8 V to 3.6 V
-
-
0.1
V
IO = 1.1 mA; VCC = 1.1 V
-
-
0.3  VCC
V
IO = 1.7 mA; VCC = 1.4 V
-
-
0.37
V
Tamb = 40 C to +85 C
VIH
VIL
VOL
II
HIGH-level input voltage
LOW-level input voltage
LOW-level output voltage
input leakage current
74AUP2G06
Product data sheet
VI = VIH or VIL
IO = 1.9 mA; VCC = 1.65 V
-
-
0.35
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.33
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.45
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.33
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.45
V
-
-
0.5
A
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 6 December 2011
© NXP B.V. 2011. All rights reserved.
5 of 18
74AUP2G06
NXP Semiconductors
Low-power dual inverter with open-drain output
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
IOZ
OFF-state output current
VI = VIL; VO = 0 V to 3.6 V;
VCC = 0 V to 3.6 V
-
-
0.5
A
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
0.5
A
IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
0.6
A
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
0.9
A
ICC
additional supply current
VI = VCC  0.6 V; IO = 0 A; VCC = 3.3 V
-
-
50
A
VCC = 0.8 V
0.75  VCC -
-
V
VCC = 0.9 V to 1.95 V
0.70  VCC -
-
V
VCC = 2.3 V to 2.7 V
1.6
-
-
V
VCC = 3.0 V to 3.6 V
2.0
-
-
V
VCC = 0.8 V
-
-
0.25  VCC V
Tamb = 40 C to +125 C
VIH
VIL
VOL
HIGH-level input voltage
LOW-level input voltage
LOW-level output voltage
VCC = 0.9 V to 1.95 V
-
-
0.30  VCC V
VCC = 2.3 V to 2.7 V
-
-
0.7
V
VCC = 3.0 V to 3.6 V
-
-
0.9
V
V
VI = VIH or VIL
IO = 20 A; VCC = 0.8 V to 3.6 V
-
-
0.11
IO = 1.1 mA; VCC = 1.1 V
-
-
0.33  VCC V
IO = 1.7 mA; VCC = 1.4 V
-
-
0.41
V
IO = 1.9 mA; VCC = 1.65 V
-
-
0.39
V
IO = 2.3 mA; VCC = 2.3 V
-
-
0.36
V
IO = 3.1 mA; VCC = 2.3 V
-
-
0.50
V
IO = 2.7 mA; VCC = 3.0 V
-
-
0.36
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.50
V
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
0.75
A
IOZ
OFF-state output current
VI = VIL; VO = 0 V to 3.6 V;
VCC = 0 V to 3.6 V
-
-
0.75
A
IOFF
power-off leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
-
-
0.75
A
IOFF
additional power-off
leakage current
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
0.75
A
ICC
supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
-
-
1.4
A
ICC
additional supply current
VI = VCC  0.6 V; IO = 0 A; VCC = 3.3 V
-
-
75
A
74AUP2G06
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 6 December 2011
© NXP B.V. 2011. All rights reserved.
6 of 18
74AUP2G06
NXP Semiconductors
Low-power dual inverter with open-drain output
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter
25 C
Conditions
40 C to +125 C
Unit
Min
Typ[1]
Max
Min
-
12.8
-
-
-
-
ns
Max
Max
(85 C) (125 C)
CL = 5 pF
tpd
propagation delay nA to nY; see Figure 7
[2]
VCC = 0.8 V
VCC = 1.1 V to 1.3 V
2.3
4.3
9.9
2.0
10.9
12.0
ns
VCC = 1.4 V to 1.6 V
1.8
3.1
6.1
1.5
7.1
7.8
ns
VCC = 1.65 V to 1.95 V
1.5
2.8
4.7
1.2
5.7
6.3
ns
VCC = 2.3 V to 2.7 V
1.2
2.2
3.2
1.0
3.9
4.3
ns
VCC = 3.0 V to 3.6 V
1.1
2.2
3.3
0.8
3.6
4.0
ns
-
15.8
-
-
-
-
ns
CL = 10 pF
tpd
propagation delay nA to nY; see Figure 7
[2]
VCC = 0.8 V
VCC = 1.1 V to 1.3 V
2.7
5.4
11.2
2.5
13.2
15.0
ns
VCC = 1.4 V to 1.6 V
2.2
3.9
7.0
2.0
8.5
9.4
ns
VCC = 1.65 V to 1.95 V
1.9
3.6
5.4
1.7
6.7
7.4
ns
VCC = 2.3 V to 2.7 V
1.7
2.9
3.8
1.4
4.5
5.0
ns
VCC = 3.0 V to 3.6 V
1.6
3.2
4.6
1.2
4.9
5.4
ns
-
18.8
-
-
-
-
ns
CL = 15 pF
tpd
propagation delay nA to nY; see Figure 7
[2]
VCC = 0.8 V
VCC = 1.1 V to 1.3 V
3.2
6.4
12.2
2.9
15.2
17.0
ns
VCC = 1.4 V to 1.6 V
2.6
4.6
7.7
2.3
9.4
10.0
ns
VCC = 1.65 V to 1.95 V
2.3
4.5
6.6
2.1
7.3
8.1
ns
VCC = 2.3 V to 2.7 V
2.1
3.5
4.6
1.7
5.1
5.7
ns
VCC = 3.0 V to 3.6 V
2.0
4.0
6.0
1.5
6.5
7.2
ns
-
27.8
-
-
-
-
ns
VCC = 1.1 V to 1.3 V
4.4
9.3
16.5
3.9
19.3
21.3
ns
VCC = 1.4 V to 1.6 V
3.6
6.8
10.1
3.2
12.0
13.2
ns
VCC = 1.65 V to 1.95 V
3.2
6.8
10.7
2.9
11.0
12.1
ns
VCC = 2.3 V to 2.7 V
2.9
5.3
7.2
2.6
7.8
8.6
ns
VCC = 3.0 V to 3.6 V
2.9
6.5
10.5
2.5
10.8
11.9
ns
CL = 30 pF
tpd
propagation delay nA to nY; see Figure 7
VCC = 0.8 V
74AUP2G06
Product data sheet
[2]
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 6 December 2011
© NXP B.V. 2011. All rights reserved.
7 of 18
74AUP2G06
NXP Semiconductors
Low-power dual inverter with open-drain output
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8.
Symbol Parameter
25 C
Conditions
40 C to +125 C
Unit
Min
Typ[1]
Max
Min
VCC = 0.8 V
-
0.5
-
-
-
-
pF
VCC = 1.1 V to 1.3 V
-
0.6
-
-
-
-
pF
Max
Max
(85 C) (125 C)
CL = 5 pF, 10 pF, 15 pF and 30 pF
power dissipation
capacitance
CPD
VCC = 1.4 V to 1.6 V
-
0.7
-
-
-
-
pF
VCC = 1.65 V to 1.95 V
-
0.7
-
-
-
-
pF
VCC = 2.3 V to 2.7 V
-
1.0
-
-
-
-
pF
VCC = 3.0 V to 3.6 V
-
1.2
-
-
-
-
pF
[1]
All typical values are measured at nominal VCC.
[2]
tpd is the same as tPZL and tPLZ.
[3]
[3]
fi = 1 MHz; VI = GND to VCC
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N where:
fi = input frequency in MHz;
VCC = supply voltage in V;
N = number of inputs switching.
12. Waveforms
VI
VM
nA input
GND
t PZL
t PLZ
VCC
nY output
VM
VOL
VX
mnb033
Measurement points are given in Table 9.
Logic level: VOL is the typical output voltage drop that occurs at the output load.
Fig 7.
Table 9.
The data input (nA) to output (nY) propagation delays
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
VX
0.8 V to 1.6 V
0.5  VCC
0.5  VCC
VOL + 0.1 V
1.65 V to 2.7 V
0.5  VCC
0.5  VCC
VOL + 0.15 V
3.0 V to 3.6 V
0.5  VCC
0.5  VCC
VOL + 0.3 V
74AUP2G06
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 6 December 2011
© NXP B.V. 2011. All rights reserved.
8 of 18
74AUP2G06
NXP Semiconductors
Low-power dual inverter with open-drain output
VCC
VEXT
5 kΩ
G
VI
VO
DUT
CL
RT
RL
001aac521
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 8.
Table 10.
Test circuit for measuring switching times
Test data
Supply voltage
Load
VEXT
[1]
VCC
CL
RL
0.8 V to 3.6 V
5 pF, 10 pF, 15 pF and 30 pF
5 k or 1 M
[1]
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
open
GND
2  VCC
For measuring enable and disable times RL = 5 k, for measuring propagation delays, setup and hold times and pulse width RL = 1 M.
74AUP2G06
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 6 December 2011
© NXP B.V. 2011. All rights reserved.
9 of 18
74AUP2G06
NXP Semiconductors
Low-power dual inverter with open-drain output
13. Package outline
Plastic surface-mounted package; 6 leads
SOT363
D
E
B
y
X
A
HE
6
5
v M A
4
Q
pin 1
index
A
A1
1
2
e1
3
bp
c
Lp
w M B
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
max
bp
c
D
E
e
e1
HE
Lp
Q
v
w
y
mm
1.1
0.8
0.1
0.30
0.20
0.25
0.10
2.2
1.8
1.35
1.15
1.3
0.65
2.2
2.0
0.45
0.15
0.25
0.15
0.2
0.2
0.1
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
SOT363
JEITA
SC-88
EUROPEAN
PROJECTION
ISSUE DATE
04-11-08
06-03-16
Fig 9. Package outline SOT363 (SC-88)
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XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b
1
2
3
4×
(2)
L
L1
e
6
5
4
e1
e1
6×
A
(2)
A1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A (1)
max
A1
max
b
D
E
e
e1
L
L1
mm
0.5
0.04
0.25
0.17
1.5
1.4
1.05
0.95
0.6
0.5
0.35
0.27
0.40
0.32
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
OUTLINE
VERSION
SOT886
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
04-07-15
04-07-22
MO-252
Fig 10. Package outline SOT886 (XSON6)
74AUP2G06
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Low-power dual inverter with open-drain output
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
1
SOT891
b
3
2
4×
(1)
L
L1
e
6
5
4
e1
e1
6×
A
(1)
A1
D
E
terminal 1
index area
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
max
b
D
E
e
e1
L
L1
mm
0.5
0.04
0.20
0.12
1.05
0.95
1.05
0.95
0.55
0.35
0.35
0.27
0.40
0.32
Note
1. Can be visible in some manufacturing processes.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
05-04-06
07-05-15
SOT891
Fig 11. Package outline SOT891 (XSON6)
74AUP2G06
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Low-power dual inverter with open-drain output
XSON6: extremely thin small outline package; no leads;
6 terminals; body 0.9 x 1.0 x 0.35 mm
1
SOT1115
b
3
2
(4×)(2)
L
L1
e
6
5
4
e1
e1
(6×)(2)
A1
A
D
E
terminal 1
index area
0
0.5
scale
Dimensions
Unit
mm
1 mm
A(1)
A1
b
D
E
e
e1
max 0.35 0.04 0.20 0.95 1.05
nom
0.15 0.90 1.00 0.55
min
0.12 0.85 0.95
0.3
L
L1
0.35 0.40
0.30 0.35
0.27 0.32
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
Outline
version
sot1115_po
References
IEC
JEDEC
JEITA
European
projection
Issue date
10-04-02
10-04-07
SOT1115
Fig 12. Package outline SOT1115 (XSON6)
74AUP2G06
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NXP Semiconductors
Low-power dual inverter with open-drain output
XSON6: extremely thin small outline package; no leads;
6 terminals; body 1.0 x 1.0 x 0.35 mm
1
SOT1202
b
3
2
(4×)(2)
L
L1
e
6
5
4
e1
e1
(6×)(2)
A1
A
D
E
terminal 1
index area
0
0.5
scale
Dimensions
Unit
mm
1 mm
A(1)
A1
b
D
E
e
e1
L
L1
max 0.35 0.04 0.20 1.05 1.05
0.35 0.40
nom
0.15 1.00 1.00 0.55 0.35 0.30 0.35
min
0.12 0.95 0.95
0.27 0.32
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
Outline
version
sot1202_po
References
IEC
JEDEC
JEITA
European
projection
Issue date
10-04-02
10-04-06
SOT1202
Fig 13. Package outline SOT1202 (XSON6)
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Low-power dual inverter with open-drain output
14. Abbreviations
Table 11.
Abbreviations
Acronym
Description
CDM
Charged Device Model
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
15. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74AUP2G06 v.4
20111206
Product data sheet
-
74AUP2G06 v.3
Modifications:
•
Legal pages updated.
74AUP2G06 v.3
20101026
Product data sheet
-
74AUP2G06 v.2
74AUP2G06 v.2
20100325
Product data sheet
-
74AUP2G06 v.1
74AUP2G06 v.1
20100211
Product data sheet
-
-
74AUP2G06
Product data sheet
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Rev. 4 — 6 December 2011
© NXP B.V. 2011. All rights reserved.
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16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
74AUP2G06
Product data sheet
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Rev. 4 — 6 December 2011
© NXP B.V. 2011. All rights reserved.
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NXP Semiconductors
Low-power dual inverter with open-drain output
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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Product data sheet
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Rev. 4 — 6 December 2011
© NXP B.V. 2011. All rights reserved.
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Low-power dual inverter with open-drain output
18. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Contact information. . . . . . . . . . . . . . . . . . . . . 17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 6 December 2011
Document identifier: 74AUP2G06