R R R R R A A A A A FT FT FT FT FT D R R A A FT FT FT FT A A R R D D D D D R R A A A R R D D N-channel QFN3333 30 V 9 mΩ logic level MOSFET FT FT Objective data sheet FT Rev. 01 — 12 February 2010 D D D D D PSMN9R0-30LL R A F FT FT A A R R D D D D FT FT A A R R D 1. Product profile D D R A FT 1.1 General description D High efficiency due to low switching and conduction losses Suitable for logic level gate drive sources Small footprint for compact designs 1.3 Applications Battery protection Load switching DC-to-DC converters Power ORing 1.4 Quick reference data Table 1. Quick reference Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C - - 30 V ID drain current Tmb = 25 °C; VGS = 10 V; see Figure 1 - - 21 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - - 50 W Tj junction temperature -55 - 150 °C VGS = 10 V; Tj(init) = 25 °C; ID = 40 A; Vsup ≤ 30 V; unclamped; RGS = 50 Ω - - 32 mJ VGS = 10 V; ID = 10 A; VDS = 15 V; see Figure 12 and 15 - 2.9 - nC - 20.6 - nC VGS = 10 V; ID = 7.5 A; Tj = 100 °C; see Figure 10 - - 11.9 mΩ VGS = 10 V; ID = 7.5 A; Tj = 25 °C; see Figure 11 - 8 9 mΩ Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy Dynamic characteristics QGD gate-drain charge QG(tot) total gate charge Static characteristics RDSon drain-source on-state resistance A 1.2 Features and benefits R Logic level N-channel MOSFET in QFN3333 package qualified to 150 °C. This product is designed and qualified for use in a wide range of industrial, communications and power supply equipment. D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R R S source 3 S source 4 G gate 5,6,7,8 D mounting base; connected to drain D 2 R source Graphic symbol D S FT Simplified outline FT A A R 1 A FT D 8 7 6 5 D R A G mbb076 S 1 2 3 4 Transparent top view SOT873-1 (HVSON8) 3. Ordering information Ordering information Package Name Description Version HVSON8 plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 3.3 x 3.3 x 0.85 mm SOT873-1 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C - 30 V VDGR drain-gate voltage Tj ≤ 150 °C; Tj ≥ 25 °C; RGS = 20 kΩ - 30 V VGS gate-source voltage -20 20 V ID drain current VGS = 10 V; Tmb = 100 °C; see Figure 1 - 21 A VGS = 10 V; Tmb = 25 °C; see Figure 1 - 21 A IDM peak drain current tp ≤ 10 µs; pulsed; Tmb = 25 °C - 226 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - 50 W Tstg storage temperature -55 150 °C Tj junction temperature -55 150 °C Tsld(M) peak soldering temperature - 260 °C Source-drain diode IS source current Tmb = 25 °C - 21 A ISM peak source current tp ≤ 10 µs; pulsed; Tmb = 25 °C - 226 A - 32 mJ Avalanche ruggedness EDS(AL)S non-repetitive VGS = 10 V; Tj(init) = 25 °C; ID = 40 A; Vsup ≤ 30 V; drain-source avalanche unclamped; RGS = 50 Ω energy PSMN9R0-30LL_1 Objective data sheet F D D Description PSMN9R0-30LL A FT FT A A R R D D D Symbol Type number FT FT FT FT Pinning information Pin Table 3. A A A A R R D D D 2. Pinning information FT FT FT FT FT N-channel QFN3333 30 V 9 mΩ logic level MOSFET Table 2. A A A A A PSMN9R0-30LL NXP Semiconductors All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 February 2010 © NXP B.V. 2010. All rights reserved. 2 of 13 D D D D D R R R R R D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A FT F FT A A R R D D D 003aab937 FT D Pder (%) D ID (A) FT A A R R D D 120 A A A A R R D D D 003aae127 FT FT FT FT FT N-channel QFN3333 30 V 9 mΩ logic level MOSFET 60 A A A A A PSMN9R0-30LL NXP Semiconductors R A FT D 80 40 R A (1) 40 20 0 0 0 Fig 1. 50 100 150 200 Tmb ( °C) Continuous drain current as a function of mounting base temperature 0 50 100 150 200 Tmb (°C) Fig 2. Normalized total power dissipation as a function of solder point temperature 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Rth(j-mb) thermal resistance from junction to mounting base Conditions Min Typ Max Unit - [tbd] [tbd] K/W Conditions Min Typ Max Unit drain-source breakdown voltage ID = 0.25 mA; VGS = 0 V; Tj = -55 °C 27 - - V ID = 0.25 mA; VGS = 0 V; Tj = 25 °C 30 - - V gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 150 °C; see Figure 8 0.65 - - V ID = 1 mA; VDS = VGS; Tj = 25 °C; see Figure 8 and 9 1.3 1.7 2.15 V ID = 1 mA; VDS = VGS; Tj = -55 °C; see Figure 8 - - 2.45 V 6. Characteristics Table 6. Symbol Characteristics Parameter Static characteristics V(BR)DSS VGS(th) IDSS drain leakage current VDS = 30 V; VGS = 0 V; Tj = 25 °C - - 1 µA IGSS gate leakage current VGS = 20 V; VDS = 0 V; Tj = 25 °C - 10 100 nA VGS = -20 V; VDS = 0 V; Tj = 25 °C - 10 100 nA PSMN9R0-30LL_1 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 February 2010 © NXP B.V. 2010. All rights reserved. 3 of 13 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D R Unit RDSon drain-source on-state resistance VGS = 10 V; ID = 7.5 A; Tj = 100 °C; see Figure 10 - - 11.9 VGS = 10 V; ID = 7.5 A; Tj = 150 °C; see Figure 10 - 14.4 16.2 mΩ VGS = 10 V; ID = 7.5 A; Tj = 25 °C; see Figure 11 - 8 9 mΩ - 1.46 - Ω ID = 10 A; VDS = 15 V; VGS = 10 V; see Figure 12 and 15 - 20.6 - nC ID = 0 A; VDS = 0 V; VGS = 10 V - 18.6 - nC ID = 10 A; VDS = 15 V; VGS = 10 V; see Figure 12 - 3.4 - nC - 1.9 - nC - 1.4 - nC D FT FT A A R R mΩ D D R A FT gate-source charge QGS(th) pre-threshold gate-source charge QGS(th-pl) post-threshold gate-source charge QGD gate-drain charge ID = 10 A; VDS = 15 V; VGS = 10 V; see Figure 12 and 15 - 2.9 - nC VGS(pl) gate-source plateau voltage ID = 10 A; VDS = 15 V; see Figure 12 and 15 - 2.6 - V Ciss input capacitance - 1193 - pF Coss output capacitance VDS = 15 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 13 - 223 - pF Crss reverse transfer capacitance - 106 - pF td(on) turn-on delay time - 16 - ns tr rise time - 18 - ns td(off) turn-off delay time - 22 - ns tf fall time - 8 - ns VDS = 15 V; RL = 1.5 Ω; VGS = 10 V; RG(ext) = 4.7 Ω; Tj = 25 °C Source-drain diode VSD source-drain voltage IS = 7.5 A; VGS = 0 V; Tj = 25 °C; see Figure 14 - 0.85 1.2 V trr reverse recovery time - 30 - ns Qr recovered charge IS = 10 A; dIS/dt = 100 A/µs; VGS = 0 V; VDS = 15 V - 22 - nC PSMN9R0-30LL_1 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 February 2010 © NXP B.V. 2010. All rights reserved. 4 of 13 A QGS R total gate charge D Dynamic characteristics QG(tot) F Max A Typ D Min FT Conditions FT A A R R D D D Parameter internal gate resistance f = 1 MHz (AC) FT FT FT FT Symbol RG A A A A R R D D D Characteristics …continued FT FT FT FT FT N-channel QFN3333 30 V 9 mΩ logic level MOSFET Table 6. A A A A A PSMN9R0-30LL NXP Semiconductors D D D D D R R R R R A A A A A D R R D R R A FT FT FT A A R R D D D R F FT D FT ID (A) FT A A R R D gfs (S) A FT A A R R D D D 003aae131 30 FT FT FT FT 003aae132 A A A A R R D D D N-channel QFN3333 30 V 9 mΩ logic level MOSFET 60 FT FT FT FT FT PSMN9R0-30LL NXP Semiconductors D D R A 45 FT D 20 R A 30 10 Tj = 150 °C 15 0 0 0 Fig 3. Tj = 25 °C 10 20 0 30 I D (A) Fig 4. 003aae133 Ciss C (pF) 2 3 4 VGS (V) Forward transconductance as a function of drain current; typical values 2000 1 Transfer characteristics: drain current as a function of gate-source voltage; typical values 003aae136 80 RDSon (mΩ) 1500 60 Crss 1000 40 500 20 0 0 0 Fig 5. 3 6 9 VGS (V) 12 Input and reverse transfer capacitances as a function of gate-source voltage, typical values PSMN9R0-30LL_1 Objective data sheet 0 Fig 6. 5 10 15 VGS (V) 20 Drain-source on-state resistance as a function of gate-source voltage; typical values All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 February 2010 © NXP B.V. 2010. All rights reserved. 5 of 13 D D D D D R R R R R D R R FT FT FT FT D R R A FT FT FT A A R R D D D R F FT FT D FT D VGS (th) (V) D ID (A) FT A A R R D 3 A A A R R D D D 003a a c337 3 A A A A R R D D D 003aae130 10 4.5 3.5 FT FT FT FT FT N-channel QFN3333 30 V 9 mΩ logic level MOSFET 30 A A A A A PSMN9R0-30LL NXP Semiconductors R A max D 2 R 2.8 FT 20 A typ min 2.6 10 1 2.4 VGS (V) = 2.2 0 0 Fig 7. 0.25 0.5 0.75 VDS(V) 0 -60 1 Output characteristics: drain current as a function of drain-source voltage; typical values Fig 8. ID (A) 10-2 60 120 Tj (°C) 180 Gate-source threshold voltage as a function of junction temperature 003aab271 10-1 0 03aa27 2 a 1.5 min typ max 10-3 1 10 -4 0.5 10-5 10-6 0 Fig 9. 1 2 VGS (V) 3 Sub-threshold drain current as a function of gate-source voltage PSMN9R0-30LL_1 Objective data sheet 0 −60 0 60 120 Tj (°C) 180 Fig 10. Normalized drain-source on-state resistance factor as a function of junction temperature All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 February 2010 © NXP B.V. 2010. All rights reserved. 6 of 13 D D D D D R R R R R D R R R A FT R A F FT FT A A R R D D D D FT FT A A R R D VDS 3.0 D R FT FT A A R R D D D 2.8 FT FT FT FT VGS (V) = 2.6 A A A A R R D D D 003aae135 40 FT FT FT FT FT N-channel QFN3333 30 V 9 mΩ logic level MOSFET RDSon (mΩ) A A A A A PSMN9R0-30LL NXP Semiconductors D D ID R A 30 FT D VGS(pl) R A VGS(th) 20 VGS 3.5 4.0 4.5 10 10 QGS1 QGS2 QGS QGD QG(tot) 003aaa508 0 0 10 20 I D (A) 30 Fig 12. Gate charge waveform definitions Fig 11. Drain-source on-state resistance as a function of drain current; typical values 003aae134 104 C (pF) 003aae138 30 IS (A) Ciss 103 20 Coss 10 2 10 10-1 10 Crss 1 10 VDS (V) Tj = 150 °C 102 Fig 13. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values PSMN9R0-30LL_1 Objective data sheet Tj = 25 °C 0 0 0.3 0.6 0.9 VSD (V) 1.2 Fig 14. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 February 2010 © NXP B.V. 2010. All rights reserved. 7 of 13 D D D D D R R R R R A A A A A D R R D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D VGS (V) FT FT FT FT 003aae137 A A A A R R D D D N-channel QFN3333 30 V 9 mΩ logic level MOSFET 10 FT FT FT FT FT PSMN9R0-30LL NXP Semiconductors D D 8 R A FT 24V D 6 R 6V A VDS = 15V 4 2 0 0 5 10 15 20 25 QG (nC) Fig 15. Gate-source voltage as a function of gate charge; typical values PSMN9R0-30LL_1 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 February 2010 © NXP B.V. 2010. All rights reserved. 8 of 13 D D D D D R R R R R A A A A A D R R FT FT FT FT A A A A R R D D D N-channel QFN3333 30 V 9 mΩ logic level MOSFET D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 7. Package outline FT FT FT FT FT PSMN9R0-30LL NXP Semiconductors D FT FT A A R R D HVSON8: plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 3.3 × 3.3 × 0.85 mm D D SOT873-1 R A FT D R A X B D A E terminal 1 index area A A1 c detail X terminal 1 index area e1 C v w b e 1 M M y y1 C C A B C 4 L1 Eh L2 8 5 Dh 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. mm 1 A1 b 0.05 0.35 0.00 0.25 c D Dh E 0.2 3.4 3.2 2.3 2.2 3.4 3.2 Eh e e1 L1 L2 0.55 0.52 1.68 0.65 1.95 0.45 0.42 1.58 v w y y1 0.1 0.05 0.1 0.1 REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT873-1 --- --- --- EUROPEAN PROJECTION ISSUE DATE 05-06-16 05-06-21 Fig 16. Package outline SOT873-1 (HVSON8) PSMN9R0-30LL_1 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 February 2010 © NXP B.V. 2010. All rights reserved. 9 of 13 D D D D D R R R R R D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D Supersedes PSMN9R0-30LL 20100212 Objective data sheet - - D Change notice R Data sheet status D Release date FT Document ID FT A A R R D Revision history A A A A R R D D D 8. Revision history FT FT FT FT FT N-channel QFN3333 30 V 9 mΩ logic level MOSFET Table 7. A A A A A PSMN9R0-30LL NXP Semiconductors A FT D R A PSMN9R0-30LL_1 Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 February 2010 © NXP B.V. 2010. All rights reserved. 10 of 13 D D D D D R R R R R D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D Data sheet status A A A A R R D D D 9. Legal information FT FT FT FT FT N-channel QFN3333 30 V 9 mΩ logic level MOSFET 9.1 A A A A A PSMN9R0-30LL NXP Semiconductors D D R Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. R A The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 9.3 Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. PSMN9R0-30LL_1 Objective data sheet Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 February 2010 D Please consult the most recently issued document before initiating or completing a design. [2] 9.2 FT [1] A Document status [1][2] © NXP B.V. 2010. All rights reserved. 11 of 13 D D D D D R R R R R D R R D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. D FT FT A A R R D D D R A FT Trademarks D 9.4 For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] All information provided in this document is subject to legal disclaimers. Rev. 01 — 12 February 2010 © NXP B.V. 2010. All rights reserved. 12 of 13 A TrenchMOS — is a trademark of NXP B.V. R Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 10. Contact information Objective data sheet FT FT FT FT Non-automotive qualified products — Unless the data sheet of an NXP Semiconductors product expressly states that the product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever A A A A R R D D D Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. FT FT FT FT FT N-channel QFN3333 30 V 9 mΩ logic level MOSFET PSMN9R0-30LL_1 A A A A A PSMN9R0-30LL NXP Semiconductors D D D D D R R R R R D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2 Thermal characteristics . . . . . . . . . . . . . . . . . . .3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .10 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Contact information. . . . . . . . . . . . . . . . . . . . . .12 A A A A R R D D D 11. Contents FT FT FT FT FT N-channel QFN3333 30 V 9 mΩ logic level MOSFET D D R A FT D R A 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 A A A A A PSMN9R0-30LL NXP Semiconductors Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 12 February 2010 Document identifier: PSMN9R0-30LL_1