D2 PA K PSMN1R1-30BL N-channel 30 V 1.1 mΩ logic level MOSFET in D2PAK Rev. 1 — 3 February 2011 Objective data sheet 1. Product profile 1.1 General description Logic level N-channel MOSFET in D2PAK package qualified to 175 °C. This product is designed and qualified for use in a wide range of industrial, communications and domestic equipment. 1.2 Features and benefits High efficiency due to low switching and conduction losses Suitable for logic level gate drive sources 1.3 Applications DC-to-DC converters Motor control Load switching Server power supplies 1.4 Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - - 30 V ID drain current Tmb = 25 °C; VGS = 10 V; see Figure 1 - - 120 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - - 306 W Tj junction temperature -55 - 175 °C VGS = 10 V; ID = 25 A; Tj = 25 °C; see Figure 12 - 1 1.1 mΩ VGS = 10 V; ID = 25 A; Tj = 100 °C; see Figure 13 - 1.53 1.8 mΩ [1] Static characteristics RDSon drain-source on-state resistance PSMN1R1-30BL NXP Semiconductors N-channel 30 V 1.1 mΩ logic level MOSFET in D2PAK Table 1. Symbol Quick reference data …continued Parameter Conditions Min Typ Max Unit - 37 - nC - 118 - nC - - 1.9 J Dynamic characteristics QGD QG(tot) gate-drain charge VGS = 4.5 V; ID = 75 A; total gate charge VDS = 15 V; see Figure 14; see Figure 15 Avalanche ruggedness EDS(AL)S [1] non-repetitive VGS = 10 V; Tj(init) = 25 °C; drain-source ID = 120 A; Vsup ≤ 30 V; avalanche energy RGS = 50 Ω; unclamped Continuous current is limited by package. 2. Pinning information Table 2. Pinning information Pin Symbol Description 1 G gate Simplified outline 2 D drain[1] 3 S source mb D mounting base; connected to drain Graphic symbol D mb G mbb076 S 2 1 3 SOT404 (D2PAK) [1] It is not possible to make connection to pin 2 3. Ordering information Table 3. Ordering information Type number PSMN1R1-30BL PSMN1R1-30BL Objective data sheet Package Name Description D2PAK plastic single-ended surface-mounted package (D2PAK); 3 leads SOT404 (one lead cropped) All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 February 2011 Version © NXP B.V. 2011. All rights reserved. 2 of 15 PSMN1R1-30BL NXP Semiconductors N-channel 30 V 1.1 mΩ logic level MOSFET in D2PAK 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C - 30 V VDGR drain-gate voltage Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ - 30 V VGS gate-source voltage ID drain current -20 20 V VGS = 10 V; Tmb = 100 °C; see Figure 1 [1] - 120 A VGS = 10 V; Tmb = 25 °C; see Figure 1 [1] - 120 A IDM peak drain current pulsed; tp ≤ 10 µs; Tmb = 25 °C; see Figure 3 - 1456 A Ptot total power dissipation Tmb = 25 °C; see Figure 2 - 306 W Tstg storage temperature -55 175 °C Tj junction temperature -55 175 °C Tsld(M) peak soldering temperature - 260 °C - 120 A Source-drain diode [1] IS source current Tmb = 25 °C ISM peak source current pulsed; tp ≤ 10 µs; Tmb = 25 °C - 1456 A VGS = 10 V; Tj(init) = 25 °C; ID = 120 A; Vsup ≤ 30 V; RGS = 50 Ω; unclamped - 1.9 J Avalanche ruggedness non-repetitive drain-source avalanche energy EDS(AL)S [1] Continuous current is limited by package. ID (A) 003aaf774 420 03aa16 120 Pder (%) 360 300 80 240 180 40 120 (1) 60 0 0 0 Fig 1. 50 100 150 Tmb (°C) 200 Objective data sheet 50 100 150 200 Tmb (°C) Continuous drain current as a function of mounting base temperature. PSMN1R1-30BL 0 Fig 2. Normalized total power dissipation as a function of mounting base temperature All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 February 2011 © NXP B.V. 2011. All rights reserved. 3 of 15 PSMN1R1-30BL NXP Semiconductors N-channel 30 V 1.1 mΩ logic level MOSFET in D2PAK 003aaf773 104 ID (A) 103 Limit RDSon = V DS / ID tp =10 μ s 100 μ s 102 1 ms DC 10 10 ms 100 ms 1 10-1 10-1 Fig 3. 1 10 102 V DS (V) Safe operating area; continuous and peak drain currents as a function of drain-source voltage 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit Rth(j-mb) thermal resistance from junction to mounting base see Figure 4 - 0.22 0.49 K/W Rth(j-a) thermal resistance from junction to ambient minimum footprint; mounted on a printed-circuit board - 50 - K/W 003aaf772 1 Zth(j-mb) (K/W) 10-1 δ = 0.5 0.2 0.1 0.05 10-2 δ= P 0.02 single shot t tp 10 T -3 10-6 Fig 4. tp T 10-5 10-4 10-3 10-2 10-1 tp (s) 1 Transient thermal impedance from junction to mounting base as a function of pulse duration; typical values PSMN1R1-30BL Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 February 2011 © NXP B.V. 2011. All rights reserved. 4 of 15 PSMN1R1-30BL NXP Semiconductors N-channel 30 V 1.1 mΩ logic level MOSFET in D2PAK 6. Characteristics Table 6. Characteristics Symbol Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 µA; VGS = 0 V; Tj = 25 °C 30 - - V ID = 250 µA; VGS = 0 V; Tj = -55 °C 27 - - V VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; Tj = 25 °C; see Figure 10; see Figure 11 1.3 1.7 2.2 V ID = 1 mA; VDS = VGS; Tj = 175 °C; see Figure 11 0.65 - - V ID = 1 mA; VDS = VGS; Tj = -55 °C; see Figure 11 - - 2.5 V IDSS drain leakage current VDS = 30 V; VGS = 0 V; Tj = 25 °C - 0.02 1 µA VDS = 30 V; VGS = 0 V; Tj = 175 °C - 250 500 µA IGSS gate leakage current VGS = 16 V; VDS = 0 V; Tj = 25 °C - 10 100 nA VGS = -16 V; VDS = 0 V; Tj = 25 °C - 10 100 nA VGS = 10 V; ID = 25 A; Tj = 25 °C; see Figure 12 - 1 1.1 mΩ VGS = 10 V; ID = 25 A; Tj = 175 °C; see Figure 12; see Figure 13 - 2 2.3 mΩ VGS = 10 V; ID = 25 A; Tj = 100 °C; see Figure 13 - 1.53 1.8 mΩ f = 1 MHz - 1.1 - Ω ID = 75 A; VDS = 15 V; VGS = 10 V; see Figure 14; see Figure 15 - 243 - nC ID = 0 A; VDS = 0 V; VGS = 10 V; see Figure 14; see Figure 15 - 222 - nC ID = 75 A; VDS = 15 V; VGS = 4.5 V; see Figure 14; see Figure 15 - 118 - nC RDSon RG drain-source on-state resistance gate resistance Dynamic characteristics QG(tot) total gate charge QGS gate-source charge - 39 - nC QGS(th) pre-threshold gate-source charge - 22 - nC QGS(th-pl) post-threshold gate-source charge - 17 - nC QGD gate-drain charge - 37 - nC VGS(pl) gate-source plateau voltage VDS = 15 V; see Figure 14; see Figure 15 - 2.8 - V Ciss input capacitance Coss output capacitance VDS = 15 V; VGS = 0 V; f = 1 MHz; Tj = 25 °C; see Figure 16 Crss reverse transfer capacitance td(on) turn-on delay time tr rise time PSMN1R1-30BL Objective data sheet - 14850 - pF - 2799 - pF - 1215 - pF VDS = 15 V; RL = 0.2 Ω; VGS = 5 V; RG(ext) = 5 Ω; ID = 75 A; Tj = 25 °C - 95.3 - ns VDS = 15 V; RL = 0.2 Ω; VGS = 5 V; RG(ext) = 5 Ω; Tj = 25 °C - 213 - ns All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 February 2011 © NXP B.V. 2011. All rights reserved. 5 of 15 PSMN1R1-30BL NXP Semiconductors N-channel 30 V 1.1 mΩ logic level MOSFET in D2PAK Table 6. Characteristics …continued Symbol Parameter Conditions Min Typ Max Unit td(off) turn-off delay time - 199 - ns tf fall time VDS = 15 V; RL = 0.2 Ω; VGS = 5 V; RG(ext) = 5 Ω; ID = 75 A; Tj = 25 °C - 115 - ns Source-drain diode VSD source-drain voltage IS = 25 A; VGS = 0 V; Tj = 25 °C; see Figure 17 - 0.8 1.2 V trr reverse recovery time - 67 - ns Qr recovered charge IS = 25 A; dIS/dt = -100 A/µs; VGS = 0 V; VDS = 15 V - 123 - nC PSMN1R1-30BL Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 February 2011 © NXP B.V. 2011. All rights reserved. 6 of 15 PSMN1R1-30BL NXP Semiconductors N-channel 30 V 1.1 mΩ logic level MOSFET in D2PAK 003aaf762 300 gfs (S) 003aaf763 75 ID (A) 240 60 180 45 120 30 60 15 0 Tj = 25 °C 0 0 Fig 5. Tj = 175 °C 20 40 60 ID (A) 80 Forward transconductance as a function of drain current; typical values 003aaf764 5 RDSon (mΩ) 4 0 Fig 6. 0.6 1.2 1.8 2.4 VGS (V) 3 Transfer characteristics: drain current as a function of gate-source voltage; typical values 003aad011 300 ID (A) 250 10 3 4.5 3.5 200 3 2.8 150 2 100 2.6 1 50 VGS (V) = 2.4 0 0 0 Fig 7. 4 8 12 VGS (V) Drain-source on-state resistance as a function of gate-source voltage; typical values PSMN1R1-30BL Objective data sheet 0 16 Fig 8. 2 4 6 8 10 VDS (V) Output characteristics: drain current as a function of drain-source voltage; typical values All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 February 2011 © NXP B.V. 2011. All rights reserved. 7 of 15 PSMN1R1-30BL NXP Semiconductors N-channel 30 V 1.1 mΩ logic level MOSFET in D2PAK 003aaf766 105 003aab271 10-1 ID (A) 10-2 C (pF) Ciss min typ 1 2 max 10-3 Crss 104 10-4 10-5 103 10-1 Fig 9. 1 10 VGS (V) 102 Input and reverse transfer capacitances as a function of gate-source voltage; typical values 003a a c982 3 10-6 0 3 Fig 10. Sub-threshold drain current as a function of gate-source voltage 003aad012 10 2.8 2.6 RDSon (mΩ) 8 VGS (th) (V) VGS (V) VGS (V) = 3 max 2 6 typ min 4 1 4.5 3.5 2 10 0 -60 0 0 60 120 Tj (°C) 180 Fig 11. Gate-source threshold voltage as a function of junction temperature PSMN1R1-30BL Objective data sheet 0 100 200 ID (A) 300 Fig 12. Drain-source on-state resistance as a function of drain current; typical values All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 February 2011 © NXP B.V. 2011. All rights reserved. 8 of 15 PSMN1R1-30BL NXP Semiconductors N-channel 30 V 1.1 mΩ logic level MOSFET in D2PAK 003aaf767 2.4 a 2 VDS 1.6 ID 1.2 VGS(pl) VGS(th) 0.8 VGS 0.4 QGS1 QGS2 QGS 0 -60 0 60 120 Tj (°C) 180 003aaa508 Fig 13. Normalized drain-source on-state resistance factor as a function of junction temperature 003aaf768 10 QGD QG(tot) VGS (V) Fig 14. Gate charge waveform definitions 003aaf769 105 C (pF) 8 24V Ciss 104 15V 6 VDS = 6V Coss 4 Crss 103 2 0 0 100 200 QG (nC) 300 Fig 15. Gate-source voltage as a function of gate charge; typical values PSMN1R1-30BL Objective data sheet 102 10-1 1 10 VDS (V) 102 Fig 16. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 February 2011 © NXP B.V. 2011. All rights reserved. 9 of 15 PSMN1R1-30BL NXP Semiconductors N-channel 30 V 1.1 mΩ logic level MOSFET in D2PAK 003aaf770 75 IS (A) 60 45 30 Tj = 175 °C Tj = 25 °C 15 0 0 0.2 0.4 0.6 0.8 VSD (V) 1 Fig 17. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values PSMN1R1-30BL Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 February 2011 © NXP B.V. 2011. All rights reserved. 10 of 15 PSMN1R1-30BL NXP Semiconductors N-channel 30 V 1.1 mΩ logic level MOSFET in D2PAK 7. Package outline SOT404 Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped) A A1 E mounting base D1 D HD 2 Lp 1 3 c b e e Q 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 b c D max. D1 E e Lp HD Q mm 4.50 4.10 1.40 1.27 0.85 0.60 0.64 0.46 11 1.60 1.20 10.30 9.70 2.54 2.90 2.10 15.80 14.80 2.60 2.20 OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-02-11 06-03-16 SOT404 Fig 18. Package outline SOT404 (D2PAK) PSMN1R1-30BL Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 February 2011 © NXP B.V. 2011. All rights reserved. 11 of 15 PSMN1R1-30BL NXP Semiconductors N-channel 30 V 1.1 mΩ logic level MOSFET in D2PAK 8. Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes PSMN1R1-30BL v.1 20110203 Objective data sheet - - PSMN1R1-30BL Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 February 2011 © NXP B.V. 2011. All rights reserved. 12 of 15 PSMN1R1-30BL NXP Semiconductors N-channel 30 V 1.1 mΩ logic level MOSFET in D2PAK 9. Legal information 9.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Draft — The document is a draft version only. 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Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). 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Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 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In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV, FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE, ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse, QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET, TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. 10. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PSMN1R1-30BL Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 3 February 2011 © NXP B.V. 2011. All rights reserved. 14 of 15 PSMN1R1-30BL NXP Semiconductors N-channel 30 V 1.1 mΩ logic level MOSFET in D2PAK 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3 Thermal characteristics . . . . . . . . . . . . . . . . . . .4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .12 Legal information. . . . . . . . . . . . . . . . . . . . . . . .13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Contact information. . . . . . . . . . . . . . . . . . . . . .14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 3 February 2011 Document identifier: PSMN1R1-30BL