PHILIPS P87C51UBAA

INTEGRATED CIRCUITS
80C51/87C51/80C52/87C52
80C51 8-bit microcontroller family
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V), low
power, high speed (33 MHz), 128/256 B RAM
Product specification
Replaces datasheet 80C51/87C51/80C31 of 2000 Jan 20
2000 Aug 07
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
DESCRIPTION
FEATURES
• 8051 Central Processing Unit
The Philips 80C51/87C51/80C52/87C52 is a high-performance
static 80C51 design fabricated with Philips high-density CMOS
technology with operation from 2.7 V to 5.5 V.
– 4k × 8 ROM (80C51)
– 8k × 8 ROM (80C52)
The 8xC51 and 8xC52 contain a 128 × 8 RAM and 256 × 8 RAM
respectively, 32 I/O lines, three 16-bit counter/timers, a six-source,
four-priority level nested interrupt structure, a serial I/O port for
either multi-processor communications, I/O expansion or full duplex
UART, and on-chip oscillator and clock circuits.
– 128 × 8 RAM (80C51)
– 256 × 8 RAM (80C52)
– Three 16-bit counter/timers
– Boolean processor
In addition, the device is a low power static design which offers a
wide range of operating frequencies down to zero. Two software
selectable modes of power reduction—idle mode and power-down
mode are available. The idle mode freezes the CPU while allowing
the RAM, timers, serial port, and interrupt system to continue
functioning. The power-down mode saves the RAM contents but
freezes the oscillator, causing all other chip functions to be
inoperative. Since the design is static, the clock can be stopped
without loss of user data and then the execution resumed from the
point the clock was stopped.
– Full static operation
– Low voltage (2.7 V to 5.5 V@ 16 MHz) operation
• Memory addressing capability
– 64k ROM and 64k RAM
• Power control modes:
– Clock can be stopped and resumed
– Idle mode
– Power-down mode
• CMOS and TTL compatible
• TWO speed ranges at VCC = 5 V
SELECTION TABLE
For applications requiring more ROM and RAM, see the 8XC54/58
and 8XC51RA+/RB+/RC+/80C51RA+ data sheet.
– 0 to 16 MHz
– 0 to 33 MHz
Note: 80C31/80C32 is specified in separate data sheet.
ROM/EPROM
Memory Size
(X by 8)
RAM Size
(X by 8)
Programmable
Timer Counter
(PCA)
Hardware
Watch Dog
Timer
No
No
• Three package styles
• Extended temperature ranges
• Dual Data Pointers
• Security bits:
80C31*/80C51/87C51
0K/4K
128
– ROM (2 bits)
– OTP/EPROM (3 bits)
80C32*/80C52/87C52
0K/8K/16K/32K
256
No
No
512
Yes
Yes
1024
Yes
Yes
• Encryption array – 64 bytes
• 4 level priority interrupt
• 6 interrupt sources
• Four 8-bit I/O ports
• Full–duplex enhanced UART
80C51RA+/8XC51RA+/RB+/RC+
0K/8K/16K/32K
8XC51RD+
64K
– Framing error detection
– Automatic address recognition
• Programmable clock out
• Asynchronous port reset
• Low EMI (inhibit ALE and slew rate controlled outputs)
• Wake-up from Power Down by an external interrupt
2000 Aug 07
2
853–0169 24291
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
80C51/87C51 ORDERING INFORMATION
MEMORY SIZE
4K × 8
ROM
P80C51SBPN
OTP
P87C51SBPN
ROM
P80C51SBAA
OTP
P87C51SBAA
ROM
P80C51SBBB
OTP
P87C51SBBB
ROM
P80C51SFP N
OTP
P87C51SFP N
ROM
P80C51SFA A
OTP
P87C51SFA A
ROM
P80C51SFB B
OTP
P87C51SFB B
ROM
P80C51UBAA
OTP
P87C51UBAA
ROM
P80C51UBPN
OTP
P87C51UBPN
ROM
P80C51UFA A
OTP
P87C51UFA A
TEMPERATURE RANGE °C
AND PACKAGE
VOLTAGE
RANGE
FREQ.
(MHz)
DWG. #
0 to +70
+70, Plastic Dual In
In-line
line Package
2 7 V to 5.5
2.7
55V
0 to 16
SOT129 1
SOT129-1
+70 Plastic Leaded Chip Carrier
0 to +70,
2 7 V to 5.5
55V
2.7
0 to 16
SOT187 2
SOT187-2
0 to +70
+70, Plastic Quad Flat Pack
2 7 V to 5.5
2.7
55V
0 to 16
SOT307 2
SOT307-2
–40
40 to +85
+85, Plastic Dual In
In-line
line Package
2 7 V to 5.5
2.7
55V
0 to 16
SOT129 1
SOT129-1
–40
40 to +85,
+85 Plastic Leaded Chip Carrier
2 7 V to 5.5
2.7
55V
0 to 16
SOT187 2
SOT187-2
–40
40 to +85
+85, Plastic Quad Flat Pack
2 7 V to 5.5
2.7
55V
0 to 16
SOT307 2
SOT307-2
0 to +70,
+70 Plastic Leaded Chip Carrier
5V
0 to 33
SOT187 2
SOT187-2
0 to +70
+70, Plastic Dual In
In-line
line Package
5V
0 to 33
SOT129 1
SOT129-1
–40
40 to +85,
+85 Plastic Leaded Chip Carrier
5V
0 to 33
SOT187 2
SOT187-2
PART NUMBER DERIVATION
DEVICE
NUMBER
DEVICE
NUMBER
OPERATING FREQUENCY, MAX (S)
TEMPERATURE RANGE (B)
PACKAGE (AA)
ROM
P80C51
S = 16 MHz
B = 0_ to +70_C
AA = PLCC
ROM
P80C52
S = 16 MHz
B = 0_ to +70_C
AA = PLCC
OTP
P87C51
U = 33 MHz
F = –40_C to +85_C
BB = PQFP
OTP
P87C52
U = 33 MHz
F = –40_C to +85_C
BB = PQFP
2000 Aug 07
3
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
80C52/87C52 ORDERING INFORMATION
MEMORY SIZE
8K × 8
ROM
P80C52SBPN
OTP
P87C52SBPN
ROM
P80C52SBAA
OTP
P87C52SBAA
ROM
P80C52SBBB
OTP
P87C52SBBB
ROM
P80C52SFP N
OTP
P87C52SFP N
ROM
P80C52SFA A
OTP
P87C52SFA A
ROM
P80C52SFB B
OTP
P87C52SFB B
ROM
P80C52UBAA
OTP
P87C52UBAA
ROM
P80C52UBPN
OTP
P87C52UBPN
ROM
P80C52UFA A
OTP
P87C52UFA A
2000 Aug 07
TEMPERATURE RANGE °C
AND PACKAGE
VOLTAGE
RANGE
FREQ.
(MHz)
DWG. #
0 to +70
+70, Plastic Dual In
In-line
line Package
2 7 V to 5.5
2.7
55V
0 to 16
SOT129 1
SOT129-1
+70 Plastic Leaded Chip Carrier
0 to +70,
2 7 V to 5.5
55V
2.7
0 to 16
SOT187 2
SOT187-2
0 to +70
+70, Plastic Quad Flat Pack
2 7 V to 5.5
2.7
55V
0 to 16
SOT307 2
SOT307-2
–40
40 to +85
+85, Plastic Dual In
In-line
line Package
2 7 V to 5.5
2.7
55V
0 to 16
SOT129 1
SOT129-1
–40
40 to +85,
+85 Plastic Leaded Chip Carrier
2 7 V to 5.5
2.7
55V
0 to 16
SOT187 2
SOT187-2
–40
40 to +85
+85, Plastic Quad Flat Pack
2 7 V to 5.5
2.7
55V
0 to 16
SOT307 2
SOT307-2
0 to +70,
+70 Plastic Leaded Chip Carrier
5V
0 to 33
SOT187 2
SOT187-2
0 to +70
+70, Plastic Dual In
In-line
line Package
5V
0 to 33
SOT129 1
SOT129-1
–40
40 to +85,
+85 Plastic Leaded Chip Carrier
5V
0 to 33
SOT187 2
SOT187-2
4
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
BLOCK DIAGRAM
P0.0–P0.7
P2.0–P2.7
PORT 0
DRIVERS
PORT 2
DRIVERS
VCC
VSS
RAM ADDR
REGISTER
PORT 0
LATCH
RAM
PORT 2
LATCH
ROM/EPROM
8
B
REGISTER
STACK
POINTER
ACC
PROGRAM
ADDRESS
REGISTER
TMP1
TMP2
BUFFER
ALU
SFRs
PC
INCREMENTER
TIMERS
PSW
8
16
PSEN
ALE/PROG
EAVPP
TIMING
AND
CONTROL
RST
INSTRUCTION
REGISTER
PROGRAM
COUNTER
PD
DPTR’S
MULTIPLE
PORT 1
LATCH
PORT 3
LATCH
PORT 1
DRIVERS
PORT 3
DRIVERS
P1.0–P1.7
P3.0–P3.7
OSCILLATOR
XTAL1
XTAL2
SU00845
2000 Aug 07
5
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
LOGIC SYMBOL
PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS
VCC
6
VSS
XTAL1
1
40
7
39
PORT 0
ADDRESS AND
DATA BUS
LCC
XTAL2
17
PORT 1
T2
T2EX
RST
EA/VPP
18
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RxD
TxD
INT0
INT1
T0
T1
WR
RD
PORT 2
ALE/PROG
PORT 3
SECONDARY FUNCTIONS
PSEN
29
ADDRESS BUS
SU00830
PIN CONFIGURATIONS
Function
NIC*
P1.0/T2
P1.1/T2EX
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
28
Function
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
NIC*
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
* NO INTERNAL CONNECTION
T2/P1.0 1
40 VCC
T2EX/P1.1 2
39 P0.0/AD0
P1.2 3
38 P0.1/AD1
P1.3 4
37 P0.2/AD2
P1.4 5
36 P0.3/AD3
P1.5 6
35 P0.4/AD4
P1.6 7
34 P0.5/AD5
P1.7 8
33 P0.6/AD6
RST 9
32 P0.7/AD7
SU01062
PLASTIC QUAD FLAT PACK
PIN FUNCTIONS
44
34
1
RxD/P3.0 10
TxD/P3.1 11
DUAL
IN-LINE
PACKAGE
33
PQFP
11
23
31 EA/VPP
12
30 ALE
INT0/P3.2 12
29 PSEN
INT1/P3.3 13
28 P2.7/A15
T0/P3.4 14
27 P2.6/A14
T1/P3.5 15
26 P2.5/A13
WR/P3.6 16
25 P2.4/A12
RD/P3.7 17
24 P2.3/A11
XTAL2 18
23 P2.2/A10
XTAL1 19
22 P2.1/A9
VSS 20
21 P2.0/A8
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Function
P1.5
P1.6
P1.7
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
Pin
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
* NO INTERNAL CONNECTION
SU01063
2000 Aug 07
Function
P2.7/A15
PSEN
ALE
NIC*
EA/VPP
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VCC
6
22
Function
VSS
NIC*
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
ALE
NIC*
EA/VPP
P0.7/AD7
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Function
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
VCC
NIC*
P1.0/T2
P1.1/T2EX
P1.2
P1.3
P1.4
SU01064
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC DIP
VSS
20
VCC
40
P0.0–0.7
39–32
LCC
22
44
43–36
QFP
16
38
37–30
TYPE
I
I
I/O
P1.0–P1.7
1–8
2–9
40–44,
1–3
I/O
P2.0–P2.7
1
2
21–28
2
3
24–31
40
41
18–25
I/O
I
I/O
P3.0–P3.7
10–17
11,
13–19
5,
7–13
I/O
RST
10
11
12
13
14
15
16
17
9
11
13
14
15
16
17
18
19
10
5
7
8
9
10
11
12
13
4
I
O
I
I
I
I
O
O
I
ALE/PROG
30
33
27
O
PSEN
29
32
26
O
EA/VPP
31
35
29
I
XTAL1
19
21
15
I
NAME AND FUNCTION
Ground: 0 V reference.
Power Supply: This is the power supply voltage for normal, idle, and power-down operation.
Port 0: Port 0 is an open-drain, bidirectional I/O port with Schmitt trigger inputs. Port 0 pins
that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also
the multiplexed low-order address and data bus during accesses to external program and
data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 0
also outputs the code bytes during program verification and received code bytes during
EPROM programming. External pull-ups are required during program verification.
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt trigger
inputs. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, port 1 pins that are externally pulled low will source
current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 1 also
receives the low-order address byte during program memory verification. Alternate functions
for Port 1 include:
T2 (P1.0): Timer/Counter 2 external count input/clockout (see Programmable Clock-Out)
T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction control
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt trigger
inputs. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source
current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits
the high-order address byte during fetches from external program memory and during
accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this
application, it uses strong internal pull-ups when emitting 1s. During accesses to external
data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2
special function register. Some Port 2 pins receive the high order address bits during
EPROM programming and verification.
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups and Schmitt trigger
inputs. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source
current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves
the special features of the 80C51 family, as listed below:
RxD (P3.0): Serial input port
TxD (P3.1): Serial output port
INT0 (P3.2): External interrupt
INT1 (P3.3): External interrupt
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to VSS permits a power-on reset using only an external
capacitor to VCC.
Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the
address during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking.
Note that one ALE pulse is skipped during each access to external data memory. This pin is
also the program pulse input (PROG) during EPROM programming. ALE can be disabled by
setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction.
Program Store Enable: The read strobe to external program memory. When the device is
executing code from the external program memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during each access to external data
memory. PSEN is not activated during fetches from internal program memory.
External Access Enable/Programming Supply Voltage: EA must be externally held low
to enable the device to fetch code from external program memory locations 0000H to
0FFFH. If EA is held high, the device executes from internal program memory unless the
program counter contains an address greater than the on-chip ROM/OTP. This pin also
receives the 12.75 V programming supply voltage (VPP) during EPROM programming. If
security bit 1 is programmed, EA will be internally latched on Reset.
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
Crystal 2: Output from the inverting oscillator amplifier.
XTAL2
18
20
14
O
NOTE:
To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than VCC + 0.5 V or VSS – 0.5 V, respectively.
2000 Aug 07
7
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
Table 1.
SYMBOL
80C51/87C51/80C52/87C52 Special Function Registers
DESCRIPTION
DIRECT
ADDRESS
E0H
8EH
A2H
F0H
ACC*
AUXR#
AUXR1#
B*
DPTR:
DPH
DPL
Accumulator
Auxiliary
Auxiliary 1
B register
Data Pointer (2 bytes)
Data Pointer High
Data Pointer Low
IE*
Interrupt Enable
A8H
IP*
Interrupt Priority
B8H
IPH#
Interrupt Priority High
B7H
P0*
Port 0
80H
P1*
Port 1
90H
P2*
Port 2
A0H
P3*
Port 3
B0H
PCON#1
Power Control
87H
PSW*
RACAP2H#
RACAP2L#
SADDR#
SADEN#
SBUF
Program Status Word
Timer 2 Capture High
Timer 2 Capture Low
Slave Address
Slave Address Mask
Serial Data Buffer
D0H
CBH
CAH
A9H
B9H
99H
SCON*
SP
Serial Control
Stack Pointer
98H
81H
TCON*
Timer Control
88H
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
MSB
LSB
E7
E6
E5
E4
E3
E2
E1
E0
–
–
–
–
–
–
–
AO
–
–
–
LPEP2 WUPD
0
–
DPS
F7
F6
F5
F4
F3
F2
F1
F0
83H
82H
00H
00H
AF
EA
BF
–
B7
–
87
AD7
97
–
A7
AD15
B7
RD
AE
–
BE
–
B6
–
86
AD6
96
–
A6
AD14
B6
WR
AD
ET2
BD
PT2
B5
PT2H
85
AD5
95
–
A5
AD13
B5
T1
AC
ES
BC
PS
B4
PSH
84
AD4
94
–
A4
AD12
B4
T0
AB
ET1
BB
PT1
B3
PT1H
83
AD3
93
–
A3
AD11
B3
INT1
AA
EX1
BA
PX1
B2
PX1H
82
AD2
92
–
A2
AD10
B2
INT0
A9
ET0
B9
PT0
B1
PT0H
81
AD1
91
T2EX
A1
AD9
B1
TxD
A8
EX0
B8
PX0
B0
PX0H
80
AD0
90
T2
A0
AD8
B0
RxD
SMOD1
D7
CY
SMOD0
D6
AC
–
D5
F0
POF
D4
RS1
GF1
D3
RS0
GF0
D2
OV
PD
D1
–
IDL
D0
P
9F
SM0/FE
9E
SM1
9D
SM2
9C
REN
9B
TB8
9A
RB8
99
TI
98
RI
8F
TF1
CF
TF2
–
8E
TR1
CE
EXF2
–
8D
TF0
CD
RCLK
–
8C
TR0
CC
TCLK
–
8B
IE1
CB
EXEN2
–
8A
IT1
CA
TR2
–
89
IE0
C9
C/T2
T2OE
88
IT0
C8
CP/RL2
DCEN
T2CON*
Timer 2 Control
C8H
T2MOD#
Timer 2 Mode Control
C9H
TH0
Timer High 0
8CH
TH1
Timer High 1
8DH
TH2#
Timer High 2
CDH
TL0
Timer Low 0
8AH
TL1
Timer Low 1
8BH
TL2#
Timer Low 2
CCH
TMOD
Timer Mode
89H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
NOTE:
Unused register bits that are not defined should not be set by the user’s program. If violated, the device could function incorrectly.
* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
– Reserved bits.
1. Reset value depends on reset source.
2. LPEP – Low Power EPROM operation (OTP/EPROM only)
2000 Aug 07
RESET
VALUE
00H
xxxxxxx0B
xxx000x0B
00H
8
0x000000B
xx000000B
xx000000B
FFH
FFH
FFH
FFH
00xx0000B
000000x0B
00H
00H
00H
00H
xxxxxxxxB
00H
07H
00H
00H
xxxxxx00B
00H
00H
00H
00H
00H
00H
00H
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
the SFRs but does not change the on-chip RAM. An external
interrupt allows both the SFRs and the on-chip RAM to retain their
values. WUPD (AUXR1.3–Wakeup from Power Down) enables or
disables the wakeup from power down with external interrupt.
Where:
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator, as shown in the logic symbol.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
WUPD = 0 Disable
WUPD = 1 Enable
To properly terminate Power Down the reset or external interrupt
should not be executed before VCC is restored to its normal
operating level and must be held active long enough for the
oscillator to restart and stabilize (normally less than 10 ms).
Reset
With an external interrupt, INT0 or INT1 must be enabled and
configured as level-sensitive. Holding the pin low restarts the
oscillator but bringing the pin back high completes the exit. Once the
interrupt is serviced, the next instruction to be executed after RETI
will be the one following the instruction that put the device into
Power Down.
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-up reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles.
Stop Clock Mode
LPEP
The static design enables the clock speed to be reduced down to
0 MHz (stopped). When the oscillator is stopped, the RAM and
Special Function Registers retain their values. This mode allows
step-by-step utilization and permits reduced system power
consumption by lowering the clock frequency down to any value. For
lowest power consumption the Power Down mode is suggested.
The eprom array contains some analog circuits that are not required
when VCC is less than 4 V, but are required for a VCC greater than
4 V. The LPEP bit (AUXR.4), when set, will powerdown these analog
circuits resulting in a reduced supply current. This bit should be set
ONLY for applications that operate at a VCC less than 4 V.
Design Consideration
• When the idle mode is terminated by a hardware reset, the device
Idle Mode
In idle mode (see Table 2), the CPU puts itself to sleep while all of
the on-chip peripherals stay active. The instruction to invoke the idle
mode is the last instruction executed in the normal operating mode
before the idle mode is activated. The CPU contents, the on-chip
RAM, and all of the special function registers remain intact during
this mode. The idle mode can be terminated either by any enabled
interrupt (at which time the process is picked up at the interrupt
service routine and continued), or by a hardware reset which starts
the processor in the same manner as a power-on reset.
normally resumes program execution, from where it left off, up to
two machine cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this
event, but access to the port pins is not inhibited. To eliminate the
possibility of an unexpected write when Idle is terminated by
reset, the instruction following the one that invokes Idle should not
be one that writes to a port pin or to external memory.
ONCE Mode
The ONCE (“On-Circuit Emulation”) Mode facilitates testing and
debugging of systems without the device having to be removed from
the circuit. The ONCE Mode is invoked by:
Power-Down Mode
To save even more power, a Power Down mode (see Table 2) can
be invoked by software. In this mode, the oscillator is stopped and
the instruction that invoked Power Down is the last instruction
executed. The on-chip RAM and Special Function Registers retain
their values down to 2.0 V and care must be taken to return VCC to
the minimum specified operating voltages before the Power Down
Mode is terminated.
1. Pull ALE low while the device is in reset and PSEN is high;
2. Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins go into a float
state, and the other port pins and ALE and PSEN are weakly pulled
high. The oscillator circuit remains active. While the device is in this
mode, an emulator or test CPU can be used to drive the circuit.
Normal operation is restored when a normal reset is applied.
For the 87C51 and 80C51 either a hardware reset or external
interrupt can be used to exit from Power Down. Reset redefines all
Table 2. External Pin Status During Idle and Power-Down Modes
PROGRAM MEMORY
ALE
PSEN
PORT 0
PORT 1
PORT 2
PORT 3
Idle
MODE
Internal
1
1
Data
Data
Data
Data
Idle
External
1
1
Float
Data
Address
Data
Power-down
Internal
0
0
Data
Data
Data
Data
Power-down
External
0
0
Float
Data
Data
Data
2000 Aug 07
9
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
TH2, to be captured into registers RCAP2L and RCAP2H,
respectively. In addition, the transition at T2EX causes bit EXF2 in
T2CON to be set, and EXF2 like TF2 can generate an interrupt
(which vectors to the same location as Timer 2 overflow interrupt.
The Timer 2 interrupt service routine can interrogate TF2 and EXF2
to determine which event caused the interrupt). The capture mode is
illustrated in Figure 2 (There is no reload value for TL2 and TH2 in
this mode. Even when a capture event occurs from T2EX, the
counter keeps on counting T2EX pin transitions or osc/12 pulses.).
Programmable Clock-Out
A 50% duty cycle clock can be programmed to come out on P1.0.
This pin, besides being a regular I/O pin, has two alternate
functions. It can be programmed:
1. to input the external clock for Timer/Counter 2, or
2. to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz at
a 16 MHz operating frequency.
To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in
T2CON) must be cleared and bit T20E in T2MOD must be set. Bit
TR2 (T2CON.2) also must be set to start the timer.
Auto-Reload Mode (Up or Down Counter)
In the 16-bit auto-reload mode, Timer 2 can be configured (as either
a timer or counter (C/T2* in T2CON)) then programmed to count up
or down. The counting direction is determined by bit DCEN (Down
Counter Enable) which is located in the T2MOD register (see
Figure 3). When reset is applied the DCEN=0 which means Timer 2
will default to counting up. If DCEN bit is set, Timer 2 can count up
or down depending on the value of the T2EX pin.
The Clock-Out frequency depends on the oscillator frequency and
the reload value of Timer 2 capture registers (RCAP2H, RCAP2L)
as shown in this equation:
4
Oscillator Frequency
(65536 * RCAP2H, RCAP2L)
Where:
Figure 4 shows Timer 2 which will count up automatically since
DCEN=0. In this mode there are two options selected by bit EXEN2
in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH
and sets the TF2 (Overflow Flag) bit upon overflow. This causes the
Timer 2 registers to be reloaded with the 16-bit value in RCAP2L
and RCAP2H. The values in RCAP2L and RCAP2H are preset by
software means.
(RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2L
taken as a 16-bit unsigned integer.
In the Clock-Out mode Timer 2 roll-overs will not generate an
interrupt. This is similar to when it is used as a baud-rate generator.
It is possible to use Timer 2 as a baud-rate generator and a clock
generator simultaneously. Note, however, that the baud-rate and the
Clock-Out frequency will be the same.
If EXEN2=1, then a 16-bit reload can be triggered either by an
overflow or by a 1-to-0 transition at input T2EX. This transition also
sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be
generated when either TF2 or EXF2 are 1.
TIMER 2 OPERATION
In Figure 5 DCEN=1 which enables Timer 2 to count up or down.
This mode allows pin T2EX to control the direction of count. When a
logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will
overflow at 0FFFFH and set the TF2 flag, which can then generate
an interrupt, if the interrupt is enabled. This timer overflow also
causes the 16–bit value in RCAP2L and RCAP2H to be reloaded
into the timer registers TL2 and TH2.
Timer 2
Timer 2 is a 16-bit Timer/Counter which can operate as either an
event timer or an event counter, as selected by C/T2* in the special
function register T2CON (see Figure 1). Timer 2 has three operating
modes:Capture, Auto-reload (up or down counting) ,and Baud Rate
Generator, which are selected by bits in the T2CON as shown in
Table 3.
When a logic 0 is applied at pin T2EX this causes Timer 2 to count
down. The timer will underflow when TL2 and TH2 become equal to
the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets
the TF2 flag and causes 0FFFFH to be reloaded into the timer
registers TL2 and TH2.
Capture Mode
In the capture mode there are two options which are selected by bit
EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or
counter (as selected by C/T2* in T2CON) which, upon overflowing
sets bit TF2, the timer 2 overflow bit. This bit can be used to
generate an interrupt (by enabling the Timer 2 interrupt bit in the
IE register). If EXEN2= 1, Timer 2 operates as described above, but
with the added feature that a 1- to -0 transition at external input
T2EX causes the current value in the Timer 2 registers, TL2 and
The external flag EXF2 toggles when Timer 2 underflows or
overflows. This EXF2 bit can be used as a 17th bit of resolution if
needed. The EXF2 flag does not generate an interrupt in this mode
of operation.
Table 3. Timer 2 Operating Modes
RCLK + TCLK
CP/RL2
TR2
0
0
1
16-bit Auto-reload
0
1
1
16-bit Capture
1
X
1
Baud rate generator
X
X
0
(off)
2000 Aug 07
MODE
10
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
(MSB)
(LSB)
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
Symbol
Position
Name and Significance
TF2
T2CON.7
EXF2
T2CON.6
RCLK
T2CON.5
TCLK
T2CON.4
EXEN2
T2CON.3
TR2
C/T2
T2CON.2
T2CON.1
CP/RL2
T2CON.0
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set
when either RCLK or TCLK = 1.
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and
EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2
interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down
counter mode (DCEN = 1).
Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock
in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.
Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock
in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative
transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to
ignore events at T2EX.
Start/stop control for Timer 2. A logic 1 starts the timer.
Timer or counter select. (Timer 2)
0 = Internal timer (OSC/12)
1 = External event counter (falling edge triggered).
Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When
cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when
EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload
on Timer 2 overflow.
SU00728
Figure 1. Timer/Counter 2 (T2CON) Control Register
OSC
÷ 12
C/T2 = 0
TL2
(8-bits)
TH2
(8-bits)
TF2
C/T2 = 1
T2 Pin
Control
TR2
Capture
Transition
Detector
Timer 2
Interrupt
RCAP2L
RCAP2H
T2EX Pin
EXF2
Control
EXEN2
SU00066
Figure 2. Timer 2 in Capture Mode
2000 Aug 07
11
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
T2MOD
Address = 0C9H
Reset Value = XXXX XX00B
Not Bit Addressable
Bit
*
—
—
—
—
—
—
T2OE
DCEN
7
6
5
4
3
2
1
0
Symbol
Function
—
Not implemented, reserved for future use.*
T2OE
Timer 2 Output Enable bit.
DCEN
Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter.
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features.
In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is
indeterminate.
SU00729
Figure 3. Timer 2 Mode (T2MOD) Control Register
OSC
÷ 12
C/T2 = 0
TL2
(8-BITS)
TH2
(8-BITS)
C/T2 = 1
T2 PIN
CONTROL
TR2
RELOAD
TRANSITION
DETECTOR
RCAP2L
RCAP2H
TF2
TIMER 2
INTERRUPT
T2EX PIN
EXF2
CONTROL
SU00067
EXEN2
Figure 4. Timer 2 in Auto-Reload Mode (DCEN = 0)
2000 Aug 07
12
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
(DOWN COUNTING RELOAD VALUE)
FFH
FFH
TOGGLE
EXF2
÷12
OSC
C/T2 = 0
OVERFLOW
TL2
T2 PIN
TH2
TF2
INTERRUPT
C/T2 = 1
CONTROL
TR2
COUNT
DIRECTION
1 = UP
0 = DOWN
RCAP2L
RCAP2H
(UP COUNTING RELOAD VALUE)
T2EX PIN
SU00730
Figure 5. Timer 2 Auto Reload Mode (DCEN = 1)
Timer 1
Overflow
÷2
NOTE: OSC. Freq. is divided by 2, not 12.
OSC
“0”
÷2
“1”
C/T2 = 0
SMOD
TL2
(8-bits)
“1”
TH2
(8-bits)
“0”
RCLK
C/T2 = 1
T2 Pin
Control
÷ 16
“1”
TR2
Reload
Transition
Detector
RCAP2L
T2EX Pin
EXF2
RCAP2H
RX Clock
“0”
TCLK
÷ 16
TX Clock
Timer 2
Interrupt
Control
EXEN2
Note availability of additional external interrupt.
Figure 6. Timer 2 in Baud Rate Generator Mode
2000 Aug 07
13
SU00068
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
under these conditions, a read or write of TH2 or TL2 may not be
accurate. The RCAP2 registers may be read, but should not be
written to, because a write might overlap a reload and cause write
and/or reload errors. The timer should be turned off (clear TR2)
before accessing the Timer 2 or RCAP2 registers.
Baud Rate Generator Mode
Bits TCLK and/or RCLK in T2CON (Table 3) allow the serial port
transmit and receive baud rates to be derived from either Timer 1 or
Timer 2. When TCLK= 0, Timer 1 is used as the serial port transmit
baud rate generator. When TCLK= 1, Timer 2 is used as the serial
port transmit baud rate generator. RCLK has the same effect for the
serial port receive baud rate. With these two bits, the serial port can
have different receive and transmit baud rates – one generated by
Timer 1, the other by Timer 2.
Table 4 shows commonly used baud rates and how they can be
obtained from Timer 2.
Table 4.
Figure 6 shows the Timer 2 in baud rate generation mode. The baud
rate generation mode is like the auto-reload mode, in that a rollover
in TH2 causes the Timer 2 registers to be reloaded with the 16-bit
value in registers RCAP2H and RCAP2L, which are preset by
software.
Timer 2
The baud rates in modes 1 and 3 are determined by Timer 2’s
overflow rate given below:
Modes 1 and 3 Baud Rates + Timer 2 Overflow Rate
16
The timer can be configured for either “timer” or “counter” operation.
In many applications, it is configured for “timer” operation (C/T2*=0).
Timer operation is different for Timer 2 when it is being used as a
baud rate generator.
Usually, as a timer it would increment every machine cycle (i.e., 1/12
the oscillator frequency). As a baud rate generator, it increments
every state time (i.e., 1/2 the oscillator frequency). Thus the baud
rate formula is as follows:
Ba d Rate
Baud
Osc Freq
375 K
9.6 K
2.8 K
2.4 K
1.2 K
300
110
300
110
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
12 MHz
6 MHz
6 MHz
RCAP2H
RCAP2L
FF
FF
FF
FF
FE
FB
F2
FD
F9
FF
D9
B2
64
C8
1E
AF
8F
57
Summary Of Baud Rate Equations
Timer 2 is in baud rate generating mode. If Timer 2 is being clocked
through pin T2(P1.0) the baud rate is:
Baud Rate + Timer 2 Overflow Rate
16
Modes 1 and 3 Baud Rates =
Oscillator Frequency
[32 [65536 * (RCAP2H, RCAP2L)]]
If Timer 2 is being clocked internally, the baud rate is:
Where: (RCAP2H, RCAP2L)= The content of RCAP2H and
RCAP2L taken as a 16-bit unsigned integer.
Baud Rate +
The Timer 2 as a baud rate generator mode shown in Figure 6, is
valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a
rollover in TH2 does not set TF2, and will not generate an interrupt.
Thus, the Timer 2 interrupt does not have to be disabled when
Timer 2 is in the baud rate generator mode. Also if the EXEN2
(T2 external enable flag) is set, a 1-to-0 transition in T2EX
(Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but
will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2).
Therefore when Timer 2 is in use as a baud rate generator, T2EX
can be used as an additional external interrupt, if needed.
[32
f OSC
[65536 * (RCAP2H, RCAP2L)]]
Where fOSC= Oscillator Frequency
To obtain the reload value for RCAP2H and RCAP2L, the above
equation can be rewritten as:
RCAP2H, RCAP2L + 65536 *
ǒ
32
Ǔ
f OSC
Baud Rate
Timer/Counter 2 Set-up
Except for the baud rate generator mode, the values given for
T2CON do not include the setting of the TR2 bit. Therefore, bit TR2
must be set, separately, to turn the timer on. See Table 5 for set-up
of Timer 2 as a timer. Also see Table 6 for set-up of Timer 2 as a
counter.
When Timer 2 is in the baud rate generator mode, one should not try
to read or write TH2 and TL2. As a baud rate generator, Timer 2 is
incremented every state time (osc/2) or asynchronously from pin T2;
2000 Aug 07
Timer 2 Generated Commonly Used
Baud Rates
14
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
Table 5. Timer 2 as a Timer
MODE
T2CON
INTERNAL CONTROL (Note 1)
EXTERNAL CONTROL (Note 2)
16-bit Auto-Reload
00H
08H
16-bit Capture
01H
09H
Baud rate generator receive and transmit same baud rate
34H
36H
Receive only
24H
26H
Transmit only
14H
16H
Table 6. Timer 2 as a Counter
MODE
TMOD
INTERNAL CONTROL (Note 1)
EXTERNAL CONTROL (Note 2)
16-bit
02H
0AH
Auto-Reload
03H
0BH
NOTES:
1. Capture/reload occurs only on timer/counter overflow.
2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate
generator mode.
SADDR are to b used and which bits are “don’t care”. The SADEN
mask can be logically ANDed with the SADDR to create the “Given”
address which the master will use for addressing each of the slaves.
Use of the Given address allows multiple slaves to be recognized
while excluding others. The following examples will help to show the
versatility of this scheme:
Enhanced UART
The UART operates in all of the usual modes that are described in
the first section of Data Handbook IC20, 80C51-Based 8-Bit
Microcontrollers. In addition the UART can perform framing error
detect by looking for missing stop bits, and automatic address
recognition. The UART also fully supports multiprocessor
communication.
When used for framing error detect the UART looks for missing stop
bits in the communication. A missing bit will set the FE bit in the
SCON register. The FE bit shares the SCON.7 bit with SM0 and the
function of SCON.7 is determined by PCON.6 (SMOD0) (see
Figure 7). If SMOD0 is set then SCON.7 functions as FE. SCON.7
functions as SM0 when SMOD0 is cleared. When used as FE
SCON.7 can only be cleared by software. Refer to Figure 8.
SADDR =
SADEN =
Given
=
1100 0000
1111 1101
1100 00X0
Slave 1
SADDR =
SADEN =
Given
=
1100 0000
1111 1110
1100 000X
In the above example SADDR is the same and the SADEN data is
used to differentiate between the two slaves. Slave 0 requires a 0 in
bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is
ignored. A unique address for Slave 0 would be 1100 0010 since
slave 1 requires a 0 in bit 1. A unique address for slave 1 would be
1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be
selected at the same time by an address which has bit 0 = 0 (for
slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed
with 1100 0000.
Automatic Address Recognition
Automatic Address Recognition is a feature which allows the UART
to recognize certain addresses in the serial bit stream by using
hardware to make the comparisons. This feature saves a great deal
of software overhead by eliminating the need for the software to
examine every serial address which passes by the serial port. This
feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART
modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be
automatically set when the received byte contains either the “Given”
address or the “Broadcast” address. The 9 bit mode requires that
the 9th information bit is a 1 to indicate that the received information
is an address and not data. Automatic address recognition is shown
in Figure 9.
In a more complex system the following could be used to select
slaves 1 and 2 while excluding slave 0:
The 8 bit mode is called Mode 1. In this mode the RI flag will be set
if SM2 is enabled and the information received has a valid stop bit
following the 8 address bits and the information is either a Given or
Broadcast address.
Mode 0 is the Shift Register mode and SM2 is ignored.
Using the Automatic Address Recognition feature allows a master to
selectively communicate with one or more slaves by invoking the
Given slave address or addresses. All of the slaves may be
contacted by using the Broadcast address. Two special Function
Registers are used to define the slave’s address, SADDR, and the
address mask, SADEN. SADEN is used to define which bits in the
2000 Aug 07
Slave 0
Slave 0
SADDR =
SADEN =
Given
=
1100 0000
1111 1001
1100 0XX0
Slave 1
SADDR =
SADEN =
Given
=
1110 0000
1111 1010
1110 0X0X
Slave 2
SADDR =
SADEN =
Given
=
1110 0000
1111 1100
1110 00XX
In the above example the differentiation among the 3 slaves is in the
lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be
uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and
it can be uniquely addressed by 1110 and 0101. Slave 2 requires
that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0
15
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
and 1 and exclude Slave 2 use address 1110 0100, since it is
necessary to make bit 2 = 1 to exclude slave 2.
Upon reset SADDR (SFR address 0A9H) and SADEN (SFR
address 0B9H) are leaded with 0s. This produces a given address
of all “don’t cares” as well as a Broadcast address of all “don’t
cares”. This effectively disables the Automatic Addressing mode and
allows the microcontroller to use standard 80C51 type UART drivers
which do not make use of this feature.
The Broadcast Address for each slave is created by taking the
logical OR of SADDR and SADEN. Zeros in this result are trended
as don’t-cares. In most cases, interpreting the don’t-cares as ones,
the broadcast address will be FF hexadecimal.
SCON Address = 98H
Reset Value = 0000 0000B
Bit Addressable
SM0/FE
Bit:
SM1
7
6
(SMOD0 = 0/1)*
SM2
REN
TB8
RB8
Tl
Rl
5
4
3
2
1
0
Symbol
Function
FE
Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid
frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.
SM0
Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)
SM1
Serial Port Mode Bit 1
SM0
SM1
Mode
0
0
1
1
0
1
0
1
0
1
2
3
Description
Baud Rate**
shift register
8-bit UART
9-bit UART
9-bit UART
fOSC/12
variable
fOSC/64 or fOSC/32
variable
SM2
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the
received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address.
In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a
Given or Broadcast Address. In Mode 0, SM2 should be 0.
REN
Enables serial reception. Set by software to enable reception. Clear by software to disable reception.
TB8
The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.
RB8
In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.
In Mode 0, RB8 is not used.
Tl
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the
other modes, in any serial transmission. Must be cleared by software.
Rl
Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in
the other modes, in any serial reception (except see SM2). Must be cleared by software.
NOTE:
*SMOD0 is located at PCON6.
**fOSC = oscillator frequency
SU00043
Figure 7. SCON: Serial Port Control Register
2000 Aug 07
16
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
D0
D1
D2
D3
D4
D5
D6
D7
D8
DATA BYTE
START
BIT
ONLY IN
MODE 2, 3
STOP
BIT
SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR)
SM0 TO UART MODE CONTROL
SM0 / FE
SM1
SM2
REN
SMOD1
SMOD0
–
POF
TB8
GF1
RB8
TI
GF0
PD
RI
SCON
(98H)
IDL
PCON
(87H)
0 : SCON.7 = SM0
1 : SCON.7 = FE
SU01191
Figure 8. UART Framing Error Detection
D0
D1
D2
D3
D4
SM0
SM1
1
1
1
0
D5
SM2
1
D6
D7
D8
REN
TB8
RB8
1
X
TI
RI
SCON
(98H)
RECEIVED ADDRESS D0 TO D7
COMPARATOR
PROGRAMMED ADDRESS
IN UART MODE 2 OR MODE 3 AND SM2 = 1:
INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS”
– WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES
– WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.
SU00045
Figure 9. UART Multiprocessor Communication, Automatic Address Recognition
2000 Aug 07
17
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
An interrupt will be serviced as long as an interrupt of equal or
higher priority is not already being serviced. If an interrupt of equal
or higher level priority is being serviced, the new interrupt will wait
until it is finished before being serviced. If a lower priority level
interrupt is being serviced, it will be stopped and the new interrupt
serviced. When the new interrupt is finished, the lower priority level
interrupt that was stopped will be completed.
Interrupt Priority Structure
The 80C51/87C51 and 80C52/87C52 have a 6-source four-level
interrupt structure. They are the IE, IP and IPH. (See Figures 10, 11,
and 12.) The IPH (Interrupt Priority High) register that makes the
four-level interrupt structure possible. The IPH is located at SFR
address B7H. The structure of the IPH register and a description of
its bits is shown in Figure 12.
The function of the IPH SFR is simple and when combined with the
IP SFR determines the priority of each interrupt. The priority of each
interrupt is determined as shown in the following table:
PRIORITY BITS
INTERRUPT PRIORITY LEVEL
IPH.x
IP.x
0
0
Level 0 (lowest priority)
0
1
Level 1
1
0
Level 2
1
1
Level 3 (highest priority)
Table 7.
Interrupt Table
SOURCE
POLLING PRIORITY
REQUEST BITS
HARDWARE CLEAR?
N
(L)1
Y
(T)2
VECTOR ADDRESS
X0
1
IE0
T0
2
TP0
Y
03H
X1
3
IE1
N (L) Y (T)
13H
T1
4
TF1
Y
1BH
SP
5
RI, TI
N
23H
T2
6
TF2, EXF2
N
2BH
0BH
NOTES:
1. L = Level activated
2. T = Transition activated
IE (0A8H)
7
6
5
4
3
2
1
0
EA
—
ET2
ES
ET1
EX1
ET0
EX0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables it.
BIT
IE.7
SYMBOL
EA
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
—
ET2
ES
ET1
EX1
ET0
EX0
FUNCTION
Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually
enabled or disabled by setting or clearing its enable bit.
Not implemented. Reserved for future use.
Timer 2 interrupt enable bit.
Serial Port interrupt enable bit.
Timer 1 interrupt enable bit.
External interrupt 1 enable bit.
Timer 0 interrupt enable bit.
External interrupt 0 enable bit.
SU00571
Figure 10. IE Registers
2000 Aug 07
18
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
IP (0B8H)
7
6
5
4
3
2
1
0
—
—
PT2
PS
PT1
PX1
PT0
PX0
Priority Bit = 1 assigns higher priority
Priority Bit = 0 assigns lower priority
BIT
IP.7
IP.6
IP.5
IP.4
IP.3
IP.2
IP.1
IP.0
SYMBOL
—
—
PT2
PS
PT1
PX1
PT0
PX0
FUNCTION
Not implemented, reserved for future use.
Not implemented, reserved for future use.
Timer 2 interrupt priority bit.
Serial Port interrupt priority bit.
Timer 1 interrupt priority bit.
External interrupt 1 priority bit.
Timer 0 interrupt priority bit.
External interrupt 0 priority bit.
SU00572
Figure 11. IP Registers
IPH (B7H)
7
6
5
4
3
2
1
0
—
—
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
Priority Bit = 1 assigns higher priority
Priority Bit = 0 assigns lower priority
BIT
IPH.7
IPH.6
IPH.5
IPH.4
IPH.3
IPH.2
IPH.1
IPH.0
SYMBOL
—
—
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
FUNCTION
Not implemented, reserved for future use.
Not implemented, reserved for future use.
Timer 2 interrupt priority bit high.
Serial Port interrupt priority bit high.
Timer 1 interrupt priority bit high.
External interrupt 1 priority bit high.
Timer 0 interrupt priority bit high.
External interrupt 0 priority bit high.
Figure 12. IPH Registers
2000 Aug 07
19
SU01058
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
Note that bit 2 is not writable and is always read as a zero. This
allows the DPS bit to be quickly toggled simply by executing an INC
DPTR instruction without affecting the WOPD or LPEP bits.
Reduced EMI
All port pins of the 8xC51 and 8xC52 have slew rate controlled
outputs. This is to limit noise generated by quickly switching output
signals. The slew rate is factory set to approximately 10 ns rise and
fall times.
Reduced EMI Mode
DPS
The AO bit (AUXR.0) in the AUXR register when set disables the
ALE output.
BIT0
AUXR1
DPTR1
DPTR0
AUXR (8EH)
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
AO
AUXR.0
AO
DPH
(83H)
DPL
(82H)
EXTERNAL
DATA
MEMORY
Turns off ALE output.
SU00745A
Figure 13.
Dual DPTR
DPTR Instructions
The instructions that refer to DPTR refer to the data pointer that is
currently selected using the AUXR1/bit 0 register. The six
instructions that use the DPTR are as follows:
The dual DPTR structure (see Figure 13) enables a way to specify
the address of an external data memory location. There are two
16-bit DPTR registers that address the external memory, and a
single bit called DPS = AUXR1/bit0 that allows the program code to
switch between them.
• New Register Name: AUXR1#
• SFR Address: A2H
• Reset Value: xxx000x0B
INC DPTR
AUXR1 (A2H)
7
6
5
4
3
2
1
0
–
–
–
LPEP
WUPD
0
–
DPS
Where:
DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1.
Select Reg
DPS
DPTR0
0
DPTR1
1
MOV DPTR, #data16
Loads the DPTR with a 16-bit constant
MOV A, @ A+DPTR
Move code byte relative to DPTR to ACC
MOVX A, @ DPTR
Move external RAM (16-bit address) to
ACC
MOVX @ DPTR , A
Move ACC to external RAM (16-bit
address)
JMP @ A + DPTR
Jump indirect relative to DPTR
The data pointer can be accessed on a byte-by-byte basis by
specifying the low or high byte in an instruction which accesses the
SFRs. See application note AN458 for more details.
The DPS bit status should be saved by software when switching
between DPTR0 and DPTR1.
2000 Aug 07
Increments the data pointer by 1
20
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
ABSOLUTE MAXIMUM RATINGS1, 2, 3
PARAMETER
Operating temperature under bias
Storage temperature range
RATING
UNIT
0 to +70 or –40 to +85
°C
–65 to +150
°C
0 to +13.0
V
Voltage on EA/VPP pin to VSS
Voltage on any other pin to VSS
–0.5 to +6.5
V
15
mA
Maximum IOL per I/O pin
Power dissipation (based on package heat transfer limitations, not device power consumption)
1.5
W
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise
noted.
AC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C or –40°C to +85°C
CLOCK FREQUENCY
RANGE –f
SYMBOL
1/tCLCL
2000 Aug 07
FIGURE
29
PARAMETER
Oscillator frequency
Speed versions : S (16 MHz)
U (33 MHz)
21
MIN
MAX
0
0
16
33
UNIT
MHz
MHz
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
DC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 2.7 V to 5.5 V, VSS = 0 V (16 MHz devices)
SYMBOL
PARAMETER
VIL
Input low voltage11
VIH
Input high voltage (ports 0, 1, 2, 3, EA)
VIH1
Input high voltage, XTAL1,
MIN
4.0 V < VCC < 5.5 V
–0.5
2.7 V<VCC< 4.0 V
RST11
VOL
Output low voltage, ports 1, 2, 8
VCC = 2.7 V
IOL = 1.6 mA2
VOL1
Output low voltage, port 0, ALE, PSEN8, 7
VCC = 2.7 V
IOL = 3.2 mA2
VOH
O
voltage ports 1,
1 2,
2 3
Output high voltage,
3
LIMITS
TEST
CONDITIONS
TYP1
MAX
UNIT
0.2 VCC–0.1
V
–0.5
0.7
V
0.2 VCC+0.9
VCC+0.5
V
0.7 VCC
VCC+0.5
V
0.4
V
0.4
V
VCC = 2.7 V
IOH = –20 µA
VCC – 0.7
V
VCC = 4.5 V
IOH = –30 µA
VCC – 0.7
V
VCC = 2.7 V
IOH = –3.2 mA
VCC – 0.7
V
–1
VOH1
Output high voltage (port 0 in external bus
mode), ALE9, PSEN3
IIL
Logical 0 input current, ports 1, 2, 3
VIN = 0.4 V
–50
µA
ITL
Logical 1-to-0 transition current, ports 1, 2, 36
VIN = 2.0 V
See note 4
–650
µA
ILI
Input leakage current, port 0
0.45 < VIN < VCC – 0.3
±10
µA
ICC
Power supply current (see Figure 21):
Active mode @ 16 MHz
Idle mode @ 16 MHz
Power-down mode or clock stopped (see
Figure
Fi
25 ffor conditions)
diti
)
50
75
µA
µA
µA
µA
225
kΩ
RRST
See note 5
Tamb = 0°C to 70°C
Tamb = –40°C to +85°C
Internal reset pull-down resistor
3
40
CIO
Pin capacitance10 (except EA)
15
pF
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no
single output sinks more than 5 mA and no more than two outputs exceed the test conditions.
3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC–0.7 specification when the
address bits are stabilizing.
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when VIN is approximately 2 V.
5. See Figures 22 through 25 for ICC test conditions.
Active mode:
ICC = 0.9 × FREQ. + 1.1 mA
Idle mode:
ICC = 0.18 × FREQ. +1.01 mA; See Figure 21.
6. This value applies to Tamb = 0°C to +70°C. For Tamb = –40°C to +85°C, ITL = –750 µA.
7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
8. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:
15 mA (*NOTE: This is 85°C specification.)
26 mA
Maximum IOL per 8-bit port:
Maximum total IOL for all outputs:
71 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
9. ALE is tested to VOH1, except when ALE is off then VOH is the voltage specification.
10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF
(except EA is 25 pF).
11. To improve noise rejection a nominal 100 ns glitch rejection circuitry has been added to the RST pin, and a nominal 15 ns glitch rejection
circuitry has been added to the INT0 and INT1 pins. Previous devices provided only an inherent 5 ns of glitch rejection.
2000 Aug 07
22
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
DC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C or –40°C to +85°C, 33 MHz devices; 5 V ±10%; VSS = 0 V
SYMBOL
PARAMETER
VIL
Input low voltage11
VIH
Input high voltage (ports 0, 1, 2, 3, EA)
VIH1
Input high voltage, XTAL1, RST11
VOL
Output low voltage, ports 1, 2, 3 8
VOL1
TEST
CONDITIONS
MIN
TYP1
UNIT
MAX
–0.5
0.2 VCC–0.1
V
0.2 VCC+0.9
VCC+0.5
V
0.7 VCC
VCC+0.5
V
VCC = 4.5 V
IOL = 1.6mA2
0.4
V
Output low voltage, port 0, ALE, PSEN 7, 8
VCC = 4.5 V
IOL = 3.2mA2
0.4
V
VOH
Output high voltage, ports 1, 2, 3 3
VCC = 4.5 V
IOH = –30µA
VCC – 0.7
V
VOH1
Output high voltage (port 0 in external bus
mode), ALE9, PSEN3
VCC = 4.5 V
IOH = –3.2mA
VCC – 0.7
V
IIL
Logical 0 input current, ports 1, 2, 3
VIN = 0.4 V
–1
ITL
Logical 1-to-0 transition current, ports 1, 2, 36
ILI
Input leakage current, port 0
ICC
Power supply current (see Figure 21):
Active mode (see Note 5)
Idle mode (see Note 5)
Power-down mode or clock stopped (see Figure 25 ffor conditions)
diti
)
RRST
CIO
4.5 V < VCC < 5.5 V
LIMITS
–50
µA
VIN = 2.0 V
See note 4
–650
µA
0.45 < VIN < VCC – 0.3
±10
µA
50
75
µA
µA
225
kΩ
15
pF
See note 5
Tamb = 0°C to 70°C
Tamb = –40°C to +85°C
Internal reset pull-down resistor
Pin
capacitance10
3
40
(except EA)
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5 V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC–0.7 specification when the
address bits are stabilizing.
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when VIN is approximately 2 V.
5. See Figures 22 through 25 for ICC test conditions.
Active mode:
ICC(MAX) = 0.9 × FREQ. + 1.1 mA
Idle mode:
ICC(MAX) = 0.18 × FREQ. +1.0 mA; See Figure 21.
6. This value applies to Tamb = 0°C to +70°C. For Tamb = –40°C to +85°C, ITL = –750 µA.
7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
8. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
15 mA (*NOTE: This is 85°C specification.)
Maximum IOL per port pin:
Maximum IOL per 8-bit port:
26 mA
71 mA
Maximum total IOL for all outputs:
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
9. ALE is tested to VOH1, except when ALE is off then VOH is the voltage specification.
10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF
(except EA is 25 pF).
11. To improve noise rejection a nominal 100 ns glitch rejection circuitry has been added to the RST pin, and a nominal 15 ns glitch rejection
circuitry has been added to the INT0 and INT1 pins. Previous devices provided only an inherent 5 ns of glitch rejection.
2000 Aug 07
23
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
AC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C or –40°C to +85°C, VCC = +2.7 V to +5.5 V, VSS = 0 V1, 2, 3
16 MHz CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
MAX
VARIABLE CLOCK
MIN
MAX
UNIT
3.5
16
MHz
14
Oscillator frequency5
Speed versions :S
ALE pulse width
85
2tCLCL–40
ns
tAVLL
14
Address valid to ALE low
22
tCLCL–40
ns
tLLAX
14
Address hold after ALE low
32
tCLCL–30
tLLIV
14
ALE low to valid instruction in
tLLPL
14
ALE low to PSEN low
32
tCLCL–30
tPLPH
14
PSEN pulse width
142
3tCLCL–45
tPLIV
14
PSEN low to valid instruction in
tPXIX
14
Input instruction hold after PSEN
tPXIZ
14
Input instruction float after PSEN
37
tCLCL–25
ns
tAVIV 4
14
Address to valid instruction in
207
5tCLCL–105
ns
tPLAZ
14
PSEN low to address float
10
10
ns
1/tCLCL
14
tLHLL
150
82
0
ns
4tCLCL–100
ns
ns
ns
3tCLCL–105
0
ns
ns
Data Memory
tRLRH
15, 16
RD pulse width
275
6tCLCL–100
tWLWH
15, 16
WR pulse width
275
6tCLCL–100
tRLDV
15, 16
RD low to valid data in
tRHDX
15, 16
Data hold after RD
tRHDZ
15, 16
Data float after RD
65
2tCLCL–60
ns
tLLDV
15, 16
ALE low to valid data in
350
8tCLCL–150
ns
tAVDV
15, 16
Address to valid data in
397
9tCLCL–165
ns
tLLWL
15, 16
ALE low to RD or WR low
137
3tCLCL+50
ns
tAVWL
15, 16
Address valid to WR low or RD low
122
4tCLCL–130
ns
tQVWX
15, 16
Data valid to WR transition
13
tCLCL–50
ns
tWHQX
15, 16
Data hold after WR
13
tCLCL–50
ns
tQVWH
16
Data valid to WR high
287
7tCLCL–150
tRLAZ
15, 16
RD low to address float
tWHLH
15, 16
RD or WR high to ALE high
23
147
0
ns
ns
5tCLCL–165
0
239
3tCLCL–50
0
103
tCLCL–40
ns
ns
ns
0
ns
tCLCL+40
ns
External Clock
tCHCX
18
High time
20
20
tCLCL–tCLCX
ns
tCLCX
18
Low time
20
20
tCLCL–tCHCX
ns
tCLCH
18
Rise time
20
20
ns
tCHCL
18
Fall time
20
20
ns
tXLXL
17
Serial port clock cycle time
750
12tCLCL
ns
tQVXH
17
Output data setup to clock rising edge
492
10tCLCL–133
ns
tXHQX
17
Output data hold after clock rising edge
8
2tCLCL–117
ns
tXHDX
17
Input data hold after clock rising edge
0
0
ns
Shift Register
tXHDV
17
Clock rising edge to input data valid
492
10tCLCL–133
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. Interfacing the 87C51, 80C51, 87C52, or 80C52 to devices with float times up to 45 ns is permitted. This limited bus contention will not
cause damage to Port 0 drivers.
4. See application note AN457 for external memory interface.
5. Parts are guaranteed to operate down to 0 Hz. When an external clock source is used, the RST pin should be held high for a minimum of
20 µs for power-on or wakeup from power down.
2000 Aug 07
24
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
AC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5 V ±10%, VSS = 0 V1, 2, 3
VARIABLE CLOCK4
33 MHz CLOCK
16 MHz to fmax
SYMBOL
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
tLHLL
14
ALE pulse width
2tCLCL–40
21
ns
tAVLL
14
Address valid to ALE low
tCLCL–25
5
ns
tLLAX
14
Address hold after ALE low
tCLCL–25
tLLIV
14
ALE low to valid instruction in
tLLPL
14
ALE low to PSEN low
tCLCL–25
5
ns
tPLPH
14
PSEN pulse width
3tCLCL–45
45
ns
tPLIV
14
PSEN low to valid instruction in
tPXIX
14
Input instruction hold after PSEN
tPXIZ
14
Input instruction float after PSEN
tCLCL–25
5
ns
tAVIV
14
Address to valid instruction in
5tCLCL–80
70
ns
tPLAZ
14
PSEN low to address float
10
10
ns
ns
4tCLCL–65
55
3tCLCL–60
0
30
0
ns
ns
ns
Data Memory
tRLRH
15, 16
RD pulse width
6tCLCL–100
82
tWLWH
15, 16
WR pulse width
6tCLCL–100
82
tRLDV
15, 16
RD low to valid data in
tRHDX
15, 16
Data hold after RD
tRHDZ
15, 16
Data float after RD
2tCLCL–28
32
ns
tLLDV
15, 16
ALE low to valid data in
8tCLCL–150
90
ns
tAVDV
15, 16
Address to valid data in
9tCLCL–165
105
ns
tLLWL
15, 16
ALE low to RD or WR low
3tCLCL–50
140
ns
tAVWL
15, 16
Address valid to WR low or RD low
4tCLCL–75
45
ns
tQVWX
15, 16
Data valid to WR transition
tCLCL–30
0
ns
tWHQX
15, 16
Data hold after WR
tCLCL–25
5
ns
tQVWH
16
7tCLCL–130
80
tRLAZ
15, 16
RD low to address float
tWHLH
15, 16
RD or WR high to ALE high
tCLCL–25
5tCLCL–90
0
Data valid to WR high
ns
ns
60
0
3tCLCL+50
40
0
tCLCL+25
5
ns
ns
ns
0
ns
55
ns
External Clock
tCHCX
18
High time
0.38tCLCL
tCLCL–tCLCX
ns
tCLCX
18
Low time
0.38tCLCL
tCLCL–tCHCX
ns
tCLCH
18
Rise time
5
ns
tCHCL
18
Fall time
5
ns
tXLXL
17
Serial port clock cycle time
12tCLCL
360
ns
tQVXH
17
Output data setup to clock rising edge
10tCLCL–133
167
ns
tXHQX
17
Output data hold after clock rising edge
2tCLCL–80
tXHDX
17
Input data hold after clock rising edge
Shift Register
0
ns
0
ns
tXHDV
17
Clock rising edge to input data valid
10tCLCL–133
167
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. Interfacing the 87C51, 80C51, 87C52 or 80C52 to devices with float times up to 45ns is permitted. This limited bus contention will not cause
damage to Port 0 drivers.
4. Variable clock is specified for oscillator frequencies greater than 16 MHz to 33 MHz. For frequencies equal or less than 16 MHz, see 16 MHz
“AC Electrical Characteristics”, page 24.
5. Parts are guaranteed to operate down to 0 Hz. When an external clock source is used, the RST pin should be held high for a minimum of
20 µs for power-on or wakeup from power down.
2000 Aug 07
25
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
EXPLANATION OF THE AC SYMBOLS
P – PSEN
Q – Output data
R – RD signal
t – Time
V – Valid
W – WR signal
X – No longer a valid logic level
Z – Float
Examples: tAVLL = Time for address valid to ALE low.
tLLPL =Time for ALE low to PSEN low.
Each timing symbol has five characters. The first character is always
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
designations are:
A – Address
C – Clock
D – Input data
H – Logic level high
I – Instruction (program memory contents)
L – Logic level low, or ALE
tLHLL
ALE
tAVLL
tLLPL
tPLPH
tLLIV
tPLIV
PSEN
tLLAX
INSTR IN
A0–A7
PORT 0
tPXIZ
tPLAZ
tPXIX
A0–A7
tAVIV
PORT 2
A0–A15
A8–A15
SU00006
Figure 14. External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLDV
tLLWL
tRLRH
RD
tAVLL
tLLAX
tRLAZ
PORT 0
tRHDZ
tRLDV
tRHDX
A0–A7
FROM RI OR DPL
DATA IN
A0–A7 FROM PCL
INSTR IN
tAVWL
tAVDV
PORT 2
P2.0–P2.7 OR A8–A15 FROM DPF
A0–A15 FROM PCH
SU00025
Figure 15. External Data Memory Read Cycle
2000 Aug 07
26
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
ALE
tWHLH
PSEN
tWLWH
tLLWL
WR
tLLAX
tAVLL
tWHQX
tQVWX
tQVWH
A0–A7
FROM RI OR DPL
PORT 0
DATA OUT
A0–A7 FROM PCL
INSTR IN
tAVWL
PORT 2
P2.0–P2.7 OR A8–A15 FROM DPF
A0–A15 FROM PCH
SU00026
Figure 16. External Data Memory Write Cycle
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
tXLXL
CLOCK
tXHQX
tQVXH
OUTPUT DATA
0
1
2
WRITE TO SBUF
3
4
5
6
7
tXHDX
tXHDV
SET TI
INPUT DATA
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
CLEAR RI
SET RI
SU00027
Figure 17. Shift Register Mode Timing
VCC–0.5
0.45V
0.7VCC
0.2VCC–0.1
tCHCL
tCHCX
tCLCH
tCLCX
tCLCL
SU00009
Figure 18. External Clock Drive
2000 Aug 07
27
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
VCC–0.5
VLOAD+0.1V
0.2VCC+0.9
TIMING
REFERENCE
POINTS
VLOAD
0.45V
0.2VCC–0.1
VLOAD–0.1V
SU00717
SU00718
Figure 19. AC Testing Input/Output
Figure 20. Float Waveform
35
30
ICC(mA)
25
MAX ACTIVE
MODE
20
ICCMAX = 0.9 X FREQ. + 1.1
TYP ACTIVE MODE
10
MAX IDLE MODE
5
TYP IDLE MODE
4
8
12
16
20
24
28
32
36
FREQ AT XTAL1 (MHz)
SU01413
Figure 21. ICC vs. FREQ
Valid only within frequency specifications of the device under test
2000 Aug 07
VOL+0.1V
NOTE:
For timing purposes, a port is no longer floating when a 100mV change from
load voltage occurs, and begins to float when a 100mV change from the loaded
VOH/VOL level occurs. IOH/IOL ≥ ±20mA.
NOTE:
AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’.
15
VOH–0.1V
28
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
VCC
VCC
ICC
ICC
VCC
VCC
VCC
VCC
RST
RST
P0
P0
EA
EA
(NC)
XTAL2
(NC)
XTAL2
CLOCK SIGNAL
XTAL1
CLOCK SIGNAL
XTAL1
VSS
VSS
SU00719
SU00720
Figure 22. ICC Test Condition, Active Mode
All other pins are disconnected
VCC–0.5
Figure 23. ICC Test Condition, Idle Mode
All other pins are disconnected
0.7VCC
0.2VCC–0.1
0.45V
tCHCL
tCHCX
tCLCH
tCLCX
tCLCL
SU00009
Figure 24. Clock Signal Waveform for ICC Tests in Active and Idle Modes
tCLCH = tCHCL = 5ns
VCC
ICC
VCC
VCC
RST
P0
EA
(NC)
XTAL2
XTAL1
VSS
SU00016
Figure 25. ICC Test Condition, Power Down Mode
All other pins are disconnected. VCC = 2 V to 5.5 V
2000 Aug 07
VCC
29
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
device. The VPP source should be well regulated and free of glitches
and overshoot.
EPROM CHARACTERISTICS
These devices can be programmed by using a modified Improved
Quick-Pulse Programming algorithm. It differs from older methods
in the value used for VPP (programming supply voltage) and in the
width and number of the ALE/PROG pulses.
Program Verification
If security bits 2 and 3 have not been programmed, the on-chip
program memory can be read out for program verification. The
address of the program memory locations to be read is applied to
ports 1 and 2 as shown in Figure 28. The other pins are held at the
‘Verify Code Data’ levels indicated in Table 8. The contents of the
address location will be emitted on port 0. External pull-ups are
required on port 0 for this operation.
The family contains two signature bytes that can be read and used
by an EPROM programming system to identify the device. The
signature bytes identify the device as being manufactured by
Philips.
Table 8 shows the logic levels for reading the signature byte, and for
programming the program memory, the encryption table, and the
security bits. The circuit configuration and waveforms for quick-pulse
programming are shown in Figures 26 and 27. Figure 28 shows the
circuit configuration for normal program memory verification.
If the 64 byte encryption table has been programmed, the data
presented at port 0 will be the exclusive NOR of the program byte
with one of the encryption bytes. The user will have to know the
encryption table contents in order to correctly decode the verification
data. The encryption table itself cannot be read out.
Quick-Pulse Programming
Reading the Signature Bytes
The signature bytes are read by the same procedure as a normal
verification of locations 030H and 031H, except that P3.6 and P3.7
need to be pulled to a logic low. The values are:
(030H) = 15H indicates manufactured by Philips
(031H) = 92H indicates 87C51
The setup for microcontroller quick-pulse programming is shown in
Figure 26. Note that the device is running with a 4 to 6 MHz
oscillator. The reason the oscillator needs to be running is that the
device is executing internal address and program data transfers.
The address of the EPROM location to be programmed is applied to
ports 1 and 2, as shown in Figure 26. The code byte to be
programmed into that location is applied to port 0. RST, PSEN and
pins of ports 2 and 3 specified in Table 8 are held at the ‘Program
Code Data’ levels indicated in Table 8. The ALE/PROG is pulsed
low 5 times as shown in Figure 27.
Program/Verify Algorithms
Any algorithm in agreement with the conditions listed in Table 8, and
which satisfies the timing specifications, is suitable.
Security Bits
To program the encryption table, repeat the 5 pulse programming
sequence for addresses 0 through 1FH, using the ‘Pgm Encryption
Table’ levels. Do not forget that after the encryption table is
programmed, verification cycles will produce only encrypted data.
With none of the security bits programmed the code in the program
memory can be verified. If the encryption table is programmed, the
code will be encrypted when verified. When only security bit 1 (see
Table 9) is programmed, MOVC instructions executed from external
program memory are disabled from fetching code bytes from the
internal memory, EA is latched on Reset and all further programming
of the EPROM is disabled. When security bits 1 and 2 are
programmed, in addition to the above, verify mode is disabled.
When all three security bits are programmed, all of the conditions
above apply and all external program memory execution is disabled.
To program the security bits, repeat the 5 pulse programming
sequence using the ‘Pgm Security Bit’ levels. After one security bit is
programmed, further programming of the code memory and
encryption table is disabled. However, the other security bits can still
be programmed.
Note that the EA/VPP pin must not be allowed to go above the
maximum specified VPP level for any amount of time. Even a narrow
glitch above that voltage can cause permanent damage to the
Encryption Array
64 bytes of encryption array are initially unprogrammed (all 1s).
Table 8. EPROM Programming Modes
RST
PSEN
ALE/PROG
EA/VPP
P2.7
P2.6
P3.7
P3.6
Read signature
MODE
1
0
1
1
0
0
0
0
Program code data
1
0
0*
VPP
1
0
1
1
Verify code data
1
0
1
1
0
0
1
1
Pgm encryption table
1
0
0*
VPP
1
0
1
0
Pgm security bit 1
1
0
0*
VPP
1
1
1
1
Pgm security bit 2
1
0
0*
VPP
1
1
0
0
Pgm security bit 3
1
0
0*
VPP
0
1
0
1
NOTES:
1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.
2. VPP = 12.75 V ±0.25 V.
3. VCC = 5 V±10% during programming and verification.
* ALE/PROG receives 5 programming pulses for code data (also for user array; 5 pulses for encryption or security bits) while VPP is held at
12.75 V. Each programming pulse is low for 100 µs (±10 µs) and high for a minimum of 10 µs.
Trademark phrase of Intel Corporation.
2000 Aug 07
30
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
Table 9. Program Security Bits for EPROM Devices
PROGRAM LOCK BITS1, 2
SB1
SB2
SB3
PROTECTION DESCRIPTION
1
U
U
U
No Program Security features enabled. (Code verify will still be encrypted by the Encryption Array if
programmed.)
2
P
U
U
MOVC instructions executed from external program memory are disabled from fetching code bytes
from internal memory, EA is sampled and latched on Reset, and further programming of the EPROM
is disabled.
3
P
P
U
Same as 2, also verify is disabled.
4
P
P
P
Same as 3, external execution is disabled. Internal data RAM is not accessible.
NOTES:
1. P – programmed. U – unprogrammed.
2. Any other combination of the security bits is not defined.
+5V
A0–A7
VCC
P1
P0
1
RST
1
P3.6
EA/VPP
1
P3.7
ALE/PROG
EPROM/OTP
XTAL2
4–6MHz
XTAL1
PGM DATA
+12.75V
5 PULSES TO GROUND
PSEN
0
P2.7
1
P2.6
0
A8–A12
P2.0–P2.5
VSS
SU00873
Figure 26. Programming Configuration
5 PULSES
1
ALE/PROG:
0
1
2
3
4
5
SEE EXPLODED VIEW BELOW
tGHGL = 10µs MIN
tGLGH = 100µs±10µs
1
ALE/PROG:
1
0
SU00875
Figure 27. PROG Waveform
2000 Aug 07
31
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
+5V
VCC
A0–A7
P0
P1
1
RST
1
P3.6
1
P3.7
EPROM/OTP
XTAL2
4–6MHz
XTAL1
PGM DATA
EA/VPP
1
ALE/PROG
1
PSEN
0
P2.7
0 ENABLE
P2.6
0
P2.0–P2.5
A8–A12
VSS
SU00839
Figure 28. Program Verification
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
Tamb = 21°C to +27°C, VCC = 5 V±10%, VSS = 0 V (See Figure 29)
SYMBOL
VPP
PARAMETER
Programming supply voltage
MIN
MAX
UNIT
12.5
13.0
V
50
1
IPP
Programming supply current
1/tCLCL
Oscillator frequency
tAVGL
Address setup to PROG low
48tCLCL
tGHAX
Address hold after PROG
48tCLCL
tDVGL
Data setup to PROG low
48tCLCL
tGHDX
Data hold after PROG
48tCLCL
tEHSH
P2.7 (ENABLE) high to VPP
48tCLCL
tSHGL
VPP setup to PROG low
10
µs
tGHSL
VPP hold after PROG
10
µs
tGLGH
PROG width
90
tAVQV
Address to data valid
48tCLCL
tELQZ
ENABLE low to data valid
48tCLCL
tEHQZ
Data float after ENABLE
0
tGHGL
PROG high to PROG low
10
4
NOTE:
1. Not tested.
2000 Aug 07
32
6
110
mA
MHz
µs
48tCLCL
µs
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
PROGRAMMING*
VERIFICATION*
P1.0–P1.7
P2.0–P2.5
P3.4
(A0 – A12)
ADDRESS
ADDRESS
PORT 0
P0.0 – P0.7
(D0 – D7)
DATA IN
tAVQV
DATA OUT
tDVGL
tAVGL
tGHDX
tGHAX
ALE/PROG
tGLGH
tSHGL
tGHGL
tGHSL
LOGIC 1
LOGIC 1
EA/VPP
LOGIC 0
tEHSH
tELQV
tEHQZ
P2.7
**
SU01414
NOTES:
* FOR PROGRAMMING CONFIGURATION SEE FIGURE 26.
FOR VERIFICATION CONDITIONS SEE FIGURE 28.
**
SEE TABLE 8.
Figure 29. EPROM Programming and Verification
MASK ROM DEVICES
from the internal memory, EA is latched on Reset and all further
programming of the EPROM is disabled. When security bits 1 and 2
are programmed, in addition to the above, verify mode is disabled.
Security Bits
With none of the security bits programmed the code in the program
memory can be verified. If the encryption table is programmed, the
code will be encrypted when verified. When only security bit 1 (see
Table 10) is programmed, MOVC instructions executed from
external program memory are disabled from fetching code bytes
Encryption Array
64 bytes of encryption array are initially unprogrammed (all 1s).
Table 10. Program Security Bits
PROGRAM LOCK BITS1, 2
SB1
SB2
PROTECTION DESCRIPTION
1
U
U
No Program Security features enabled.
(Code verify will still be encrypted by the Encryption Array if programmed.)
2
P
U
MOVC instructions executed from external program memory are disabled from fetching code bytes from
internal memory, EA is sampled and latched on Reset, and further programming of the EPROM is disabled.
NOTES:
1. P – programmed. U – unprogrammed.
2. Any other combination of the security bits is not defined.
2000 Aug 07
33
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
80C51 ROM CODE SUBMISSION
When submitting ROM code for the 80C51, the following must be specified:
1. 4k byte user ROM data
2. 64 byte ROM encryption key
3. ROM security bits.
ADDRESS
CONTENT
BIT(S)
COMMENT
0000H to 0FFFH
DATA
7:0
User ROM Data
1000H to 103FH
KEY
7:0
ROM Encryption Key
1040H
SEC
0
ROM Security Bit 1
1040H
SEC
1
ROM Security Bit 2
Security Bit 1: When programmed, this bit has two effects on masked ROM parts:
1. External MOVC is disabled, and
2. EA is latched on Reset.
Security Bit 2: When programmed, this bit inhibits Verify User ROM.
NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled.
If the ROM Code file does not include the options, the following information must be included with the ROM code.
For each of the following, check the appropriate box, and send to Philips along with the code:
Security Bit #1:
V
Enabled
V
Disabled
Security Bit #2:
V
Enabled
V
Disabled
Encryption:
V
No
V
Yes
If Yes, must send key file.
80C52 ROM CODE SUBMISSION
When submitting ROM code for the 80C52, the following must be specified:
1. 8k byte user ROM data
2. 64 byte ROM encryption key
3. ROM security bits.
ADDRESS
CONTENT
BIT(S)
COMMENT
0000H to 1FFFH
DATA
7:0
User ROM Data
2000H to 203FH
KEY
7:0
ROM Encryption Key
2040H
SEC
0
ROM Security Bit 1
2040H
SEC
1
ROM Security Bit 2
Security Bit 1: When programmed, this bit has two effects on masked ROM parts:
1. External MOVC is disabled, and
2. EA is latched on Reset.
Security Bit 2: When programmed, this bit inhibits Verify User ROM.
NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled.
If the ROM Code file does not include the options, the following information must be included with the ROM code.
For each of the following, check the appropriate box, and send to Philips along with the code:
Security Bit #1:
V
Enabled
V
Disabled
Security Bit #2:
V
Enabled
V
Disabled
Encryption:
V
No
V
Yes
2000 Aug 07
If Yes, must send key file.
34
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
DIP40: plastic dual in-line package; 40 leads (600 mil)
2000 Aug 07
35
SOT129-1
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
PLCC44: plastic leaded chip carrier; 44 leads
2000 Aug 07
SOT187-2
36
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
2000 Aug 07
37
SOT307-2
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
80C51/87C51/80C52/87C52
4 K/8 K OTP/ROM low voltage (2.7 V–5.5 V),
low power, high speed (33 MHz), 128/256 B RAM
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 2000
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 08-00
Document order number:
2000 Aug 07
38
9397 750 07404