INTEGRATED CIRCUITS 80C550/83C550/87C550 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer Product specification Supersedes data of 1998 Jan 19 IC20 Data Handbook 1998 May 01 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer DESCRIPTION 80C550/83C550/87C550 FEATURES • 80C51 based architecture The Philips 8XC550 is a high-performance microcontroller fabricated with Philips high-density CMOS technology. This Philips CMOS technology combines the high speed and density characteristics of HMOS with the low power attributes of CMOS. Philips epitaxial substrate minimizes latch-up sensitivity. The CMOS 8XC550 has the same instruction set as the 80C51. – 4k × 8 EPROM (87C550)/ROM (83C550) – 128 × 8 RAM – Eight channels of 8-bit A/D – Two 16-bit counter/timers The 8XC550 contains a 4k × 8 EPROM (87C550)/ROM (83C550)/ROMless (80C550 has no program memory on-chip), a 128 × 8 RAM, 8 channels of 8-bit A/D, four 8-bit ports (port 1 is input only), a watchdog timer, two 16-bit counter/timers, a seven-source, two-priority level nested interrupt structure, a serial I/O port for either multi-processor communications, I/O expansion or full duplex UART, and an on-chip oscillator and clock circuits. – Watchdog timer – Full duplex serial channel – Boolean processor • Memory addressing capability – 64k ROM and 64k RAM • Power control modes: In addition, the 8XC550 has two software selectable modes of power reduction—idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. – Idle mode – Power-down mode • CMOS and TTL compatible • One speed range at VCC = 5V ±10% – 3.5 to 16MHz • Extended temperature ranges • OTP package available ORDERING INFORMATION ROMless ROM P80C550EBP N P83C550EBP N P87C550EBP N P80C550EBA A P83C550EBA A P87C550EBA A P80C550EFA A P83C550EFA A P87C550EFA A TEMPERATURE RANGE °C AND PACKAGE 1 FREQ MHz DRAWING NUMBER OTP 0 to +70, Plastic Dual In-Line Package 3.5 to 16 SOT129-1 OTP 0 to +70, Plastic Leaded Chip Carrier 3.5 to 16 SOT187-2 OTP –40 to +85, Plastic Leaded Chip Carrier 3.5 to 16 SOT187-2 EPROM NOTES: 1. OTP = One Time Programmable EPROM. 1998 May 01 2 853-1568 19329 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C550/83C550/87C550 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer BLOCK DIAGRAM P0.0–P0.7 P2.0–P2.7 PORT 0 DRIVERS PORT 2 DRIVERS VCC VSS RAM ADDR REGISTER PORT 0 LATCH RAM B REGISTER PORT 2 LATCH ROM/EPROM STACK POINTER ACC PROGRAM ADDRESS REGISTER TMP1 TMP2 PCON ALU SCON TMOD TCON TH0 TL0 TH1 SBUF IE IP BUFFER TL1 PSW INTERRUPT, SERIAL PORT AND TIMER BLOCKS PC INCREMENTER PSEN ALE/PROG EA/VPP TIMING AND CONTROL RST INSTRUCTION REGISTER PROGRAM COUNTER PD DPTR PORT 1 LATCH PORT 3 LATCH PORT 1 DRIVERS PORT 3 DRIVERS P1.0–P1.7 P3.0–P3.7 OSCILLATOR XTAL1 XTAL2 SU00005 1998 May 01 3 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer PIN CONFIGURATIONS AVCC/Vref+ 1 40 VCC AVSS/Vref– 2 39 P0.0/AD0 P1.0/ADC0 3 38 P0.1/AD1 P1.1/ADC1 4 37 P0.2/AD2 P1.2/ADC2 5 36 P0.3/AD3 P1.3/ADC3 6 35 P0.4/AD4 P1.4/ADC4 7 34 P0.5/AD5 P1.5/ADC5 8 33 P0.6/AD6 RST 9 RxD/P3.0 10 TxD/P3.1 11 32 P0.7/AD7 PLASTIC DUAL IN-LINE PACKAGE 31 EA/VPP 30 ALE/PROG INT0/P3.2 12 29 PSEN INT1/P3.3 13 28 P2.7/A15 T0/P3.4 14 27 P2.6/A14 T1/P3.5 15 26 P2.5/A13 WR/P3.6 16 25 P2.4/A12 RD/P3.7 17 24 P2.3/A11 XTAL2 18 23 P2.2/A10 XTAL1 19 22 P2.1/A9 VSS 20 21 P2.0/A8 6 1 40 7 39 PLASTIC LEADED CHIP CARRIER 17 29 18 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function AVCC Vref+ Vref– AVSS P1.0/ADC0 P1.1/ADC1 P1.2/ADC2 P1.3/ADC3 P1.4/ADC4 P1.5/ADC5 P1.6/ADC6 P1.7/ADC7 RST P3.0/RxD P3.1/TxD 1998 May 01 28 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P2.6/A14 P2.7/A15 PSEN ALE/PROG EA/VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC SU00196 4 80C550/83C550/87C550 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer 80C550/83C550/87C550 PIN DESCRIPTION PIN NO. MNEMONIC DIP LCC TYPE VSS 20 24 I Ground: 0V reference. VCC 40 44 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation. AVCC 1 1 I Analog Power Supply: Analog supply voltage. AVSS 2 4 I Analog Ground: Analog 0V reference. 2 3 I I Vref: A/D converter reference level inputs. Note that these references are combined with AVCC and AVSS in the 40-pin DIP package. 39–32 43–36 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification in the S87C550. External pull-ups are required during program verification. P1.0–P1.7 3–8 5–12 I ADC0–ADC7 3–8 5–12 P2.0–P2.7 21–28 25–32 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. P3.0–P3.7 10–17 14–21 I/O 10 11 12 13 14 15 16 17 14 15 16 17 18 19 20 21 I O I I I I O O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the SC80C51 family, as listed below: RxD (P3.0): Serial input port TxD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe RST 9 13 I ALE/PROG 30 34 I/O Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during EPROM programming. PSEN 29 33 O Program Store Enable: The read strobe to external program memory. When the device is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA/VPP 31 35 I External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to 0FFFH. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 0FFFH. For the 80C550 ROMless part, EA must be held low for the part to operate properly. This pin also receives the 12.75V programming supply voltage (VPP) during EPROM programming. XTAL1 19 23 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 18 22 O Crystal 2: Output from the inverting oscillator amplifier. Vref+ Vref– P0.0–0.7 1998 May 01 NAME AND FUNCTION Port 1: Port 1 is an 8-bit input only port (6-bit in the DIP package; bits P1.6 and P1.7 are not implemented). Port 1 digital input can be read out any time. ADCx: Inputs to the analog multiplexer input of the 8-bit A/D. There are only six A/D inputs in the DIP package. Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. 5 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C550/83C550/87C550 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer Table 1. SYMBOL 8XC550 Special Function Registers DESCRIPTION DIRECT ADDRESS ACC* Accumulator E0H ADAT# A/D result C6H ADCON# A/D control B* DPTR: DPH DPL IP*# BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB E7 E6 E5 E4 E3 E2 E1 E0 C5H – – – ADCI ADCS AADR2 AADR1 AADR0 B register F0H F7 F6 F5 F4 F3 F2 F1 F0 Data pointer (2 bytes): High byte Low byte 83H 82H Interrupt priority B8H RESET VALUE 00H xxH xxx00000B 00H 00H 00H BF BE BD BC BB BA B9 B8 – PWD PAD PS PT1 PX1 PT0 PX0 AF AE AD AC AB AA A9 A8 x0000000B IE*# Interrupt enable A8H EA EWD EAD ES ET1 EX1 ET0 EX0 00H P0* Port 0 80H 87 86 85 84 83 82 81 80 FFH P1* Port 1 90H 97 96 95 94 93 92 91 90 FFH P2* Port 2 A0H A7 A6 A5 A4 A3 A2 A1 A0 FFH P3* Port 3 B0H B7 B6 B5 B4 B3 B2 B1 B0 FFH PCON# Power control 87H SMOD SIDL – – GF1 GF0 PD IDL 00xx0000B D7 D6 D5 D4 D3 D2 D1 D0 PSW* Program status word D0H CY AC F0 RS1 RS0 OV – P SBUF Serial data buffer 99H 9F 9E 9D 9C 9B 9A 99 98 SM0 SM1 SM2 REN TB8 RB8 TI RI 00H xxH SCON* Serial port control 98H SP Stack pointer 81H 00H 8F 8E 8D 8C 8B 8A 89 88 00H TCON* Timer counter/control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H TMOD Timer/counter mode 89H GATE C/T M1 M0 GATE C/T M1 M0 00H TH0 Timer 0 high byte 8CH 00H TH1 Timer 1 high byte 8DH 00H TL0 Timer 0 low byte 8AH 00H TL1 Timer 1 low byte 8BH 07H 00H C7 C6 C5 C4 C3 C2 C1 C0 PRE2 PRE1 PRE0 – – WDRUN WDTOF WDMOD WDCON*# Watchdog timer control C0H WDL# Watchdog timer reload C1H FFH** WFEED1# Watchdog timer feed 1 C2H xxH WFEED2# Watchdog timer feed 2 C3H xxH * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. **This value is not valid for a masked ROM part (83C550) when running from internal memory (EA = 1). See data sheet for details. 1998 May 01 6 000xx000B** Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C550/83C550/87C550 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer MSB SMOD LSB SIDL X BIT PCON.7 PCON.6 PCON.5 PCON.4 PCON.3 PCON.2 PCON.1 PCON.0 X SYMBOL SMOD SIDL X X GF1 GF0 PD IDL GF1 GF0 PD IDL FUNCTION Double baud rate Serial port idle Reserved for future use Reserved for future use General purpose flag bit General purpose flag bit Power down bit Idle mode bit NOTE: The PCON register is at SFR byte address 87H. Its contents following a reset are 00XX0000. SU00197 Figure 1. Power Control Register (PCON) MSB X LSB X X ADCI ADCS AADR2 AADR1 AADR0 INPUT CHANNEL SELECTION ADDR2 0 0 0 0 1 1 1 1 BIT ADCON.7 ADCON.6 ADCON.5 ADCON.4 SYMBOL — — — ADCI ADCON.3 ADCS ADCON.2 ADDR2 ADCON.1 ADDR1 ADCON.0 ADDR0 ADDR1 0 0 1 1 0 0 1 1 ADDR0 0 1 0 1 0 1 0 1 INPUT PIN ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 FUNCTION Not used Not used Not used ADC Interrupt flag. This flag is set when an ADC conversion result is ready to be read. An interrupt is invoked if the A/D interrupt is enabled. The flag must be cleared by software. It cannot be set by software. ADC Start and Status. Setting this flag starts an A/D conversion. The ADC logic insures that this signal is high while the ADC is busy. On completion of the conversion, ADCS is reset at the same time the interrupt flag ADCI is set. ADCS cannot be reset by software. Analog Input Select 2 Analog Input Select 1 Analog Input Select 0 SU00198 Figure 2. A/D Control Register (ADCON) 1998 May 01 7 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C550/83C550/87C550 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer ADCON Register A/D CONVERTER MSB The analog input circuitry consists of an 8-input analog multiplexer and an analog-to-digital converter with 8-bit resolution. In the LCC package, the analog reference voltage and analog power supplies are connected via separate input pins; in the DIP package, Vref+ is combined with AVCC and Vref– is combined with AVSS. The analog inputs are alternate functions to port 1, which is an input only port. Digital input to port 1 can be read any time during an A/D conversion. Care should be exercised in mixing analog and digital signals on port 1, because cross talk from the digital input signals can degrade the A/D conversion accuracy of the analog input. An A/D conversion requires 40 machine cycles. X X ADCI 0 0 1 1 X ADCS 0 1 0 1 ADCI SDCS AADR2 AADR1 AADR0 Operation ADC not busy, a conversion can be started. ADC busy, start of a new conversion is blocked. Conversion completed, start of a new is blocked. Not possible. INPUT CHANNEL SELECTION The A/D converter is controlled by the ADCON special function register. The input channel to be converted is selected by the analog multiplexer by setting ADCON register bits, ADDR2–ADDR0 (see Figure 2). These bits can only be changed when ADCI and ADCS are both low. ADDR2 ADDR1 ADDR0 INPUT PIN 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6* P1.7* The completion of the 8-bit ADC conversion is flagged by ADCI in the ADCON register and the result is stored in the special function register ADAT. *Not present on 40-pin DIP versions. An ADC conversion in progress is unaffected by a software ADC start. The result of a completed conversion remains unaffected provided ADCI remains at a logic 1. While ADCS is a logic 1 or ADCI is a logic 1, a new ADC START will be blocked and consequently lost. An A/D conversion in progress will be aborted when the idle or power-down mode is entered. The result of a completed conversion (ADCI = logic 1) remains unaffected when entering the idle mode, but will be lost if power-down mode is entered. See Figure 3 for the A/D input equivalent circuit. Symbol Position ADCI ADCON.4 ADCS The analog input pins ADC0-ADC7 may still be used as digital inputs. The analog input channel that is selected by the ADDR2-ADDR0 bits in ADCON cannot be used as a digital input. Reading the selected A/D channel as a digital input will always return a 1. The unselected A/D inputs may always be used as digital inputs. ADCON.3 AADR2 ADCON.2 AADR1 ADCON.1 AADR0 ADCON.0 On RESET the A/D port pins are set to the Digital mode and will work as a normal port and need no further initialization. To use the A/D converter a single byte should be written to ADCON which selects the A/D mux and concurrently sets the ADCS bit to start the A/D conversion. The 40 machine cycles of the A/D conversion include time for signal settling after the mux is selected and before the Sample and Hold procedure is completed. The circuitry which disables the digital buffer from the port pin is updated at the start of an A/D conversion by setting the ADCS bit in ADCON. After powerup, problems will occur the first time that ADCON is written to if ADCS is not set; in this case, the digital signal disable registers contain random data and some o the 8 port pins will have their digital buffers disabled. When read, these disabled buffers will ignore their input and only return a 1. This condition will be corrected by writing a 1 to ADCS in ADCON which starts and A/D conversion. Thus, there are two operating modes: 1. DIGITAL ONLY - No Analog inputs are used and ADCON is never written to. In this case pins ADC0-ADC7 are configured as digital inputs. 2. A/D CONVERTER USED - The input multiplexer select field must be written to and ADCS must be set in ADCON. This allows unselected A/D inputs to be used as digital inputs. 1998 May 01 LSB 8 Function ADC interrupt flag. This flag is set when an ADC conversion is complete. If IE.5 = 1, an interrupt is requested when ADCI = 1. The ADCI flag must be cleared by software after A/D data is read, before the next conversion can begin. ADC start and status. Setting this bit starts an A/D conversion. Once set, ADCS remains high throughout the conversion cycle. On completion of the conversion, it is reset at the same time the ADCI interrupt flag is set. ADCS cannot be reset by software. Analog input selects. Binary coded address selects one of the five analog input port pins of P1 to be input to the converter. It can only be changed when ADCI and ADCS are both low. AADR2 is the most significant bit. Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C550/83C550/87C550 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer The routine StartAD will start a read of the A/D channel identified by R7 and exit back to the calling program. When the conversion is complete, the A/D interrupt occurs, calling the A/D interrupt service routine. The result of the conversion is returned in register R6. Sample A/D Routines The following routines demonstrate two methods of operating the A/D converter. The first method uses polling to determine when the A/D conversion is complete. The second method uses the A/D interrupt to flag the end of conversion. StartAD: MOV ORL MOV RET . . . ORG ADInt: MOV MOV RETI The routine ReadAD will start a read of the A/D channel identified by R7, and wait for the conversion to complete, polling the A/D interrupt flag. The result is returned in the accumulator. ReadAD:MOV ORL MOV ADLoop: MOV JNB MOV MOV RET A,#08h ;Basic A/D start command. A,R7 ;Add channel # to be read. ADCON,A; ;Start A/D. A,ADCON ;Get A/D status. ACC.4,ADLoop;Wait for ADCI (A/D ;finished). A,ADAT ;Get conversion result ADCON,#0 ;Clear ADCI. SmN+1 RmN+1 SmN RmN A,#08h A,R7 ADCON,A ;Basic A/D start command. ;Add channel # to be read. ;Start A/D. 2Bh R6,ADAT ADCON,#0 ;A/D interrupt address. ;Get conversion result. ;Clear ADCI. IN+1 IN To Comparator + Multiplexer RS CC CS VANALOG INPUT Rm = 0.5 - 3 kΩ CS + CC = 15pF maximum RS = Recommended < 9.6 kΩ for 1 LSB @ 12MHz NOTE: Because the analog to digital converter has a sampled-data comparator, the input looks capacitive to a source. When a conversion is initiated, switch Sm closes for 8tcy (8µs @ 12MHz crystal frequency) during which time capacitance Cs + Cc is charged. It should be noted that the sampling causes the analog input to present a varying load to an analog source. SU00199 Figure 3. 1998 May 01 A/D Input: Equivalent Circuit 9 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C550/83C550/87C550 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer A/D CONVERTER PARAMETER DEFINITIONS WATCHDOG TIMER The following definitions are included to clarify some specifications given and do not represent a complete set of A/D parameter definitions. The purpose of the watchdog timer is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state, possibly due to a programming error, electrical noise, or RFI. When enabled, the watchdog circuit will generate a system reset if the user program fails to “feed” (or reload) the watchdog within a predetermined amount of time. Absolute Accuracy Error Absolute accuracy error of a given output is the difference between the theoretical analog input voltage to produce a given output and the actual analog input voltage required to produce the same code. Since the same output code is produced by a band of input voltages, the “required input voltage” is defined as the midpoint of the band of input voltage that will produce that code. Absolute accuracy error not specified with a code is the maximum over all codes. The watchdog timer implemented on the 8XC550 has a programmable interval and can thus be fine tuned to a particular application. If the watchdog function is not used, the timer may still be used as a versatile general purpose timer. The watchdog function consists of a programmable 13-bit prescaler, and an 8-bit main timer. The main timer is clocked by a tap taken from one of the top 8 bits of the prescaler. The prescaler is incremented once every machine cycle, or 1/12 of the oscillator frequency. Thus, the main counter can be clocked as often as once every 64 machine cycles or as seldom as once every 8192 machine cycles. Nonlinearity If a straight line is drawn between the end points of the actual converter characteristics such that zero offset and full scale errors are removed, then non-linearity is the maximum deviation of the code transitions of the actual characteristics from that of the straight line so constructed. This is also referred to as relative accuracy and also integral non-linearity. When clocked, the main counter decrements. If the main watchdog counter reaches zero, a system reset will occur. To prevent the watchdog timer from under-flowing, the watchdog must be fed before it counts down to zero. When the watchdog is fed, the contents of the WDL register are loaded into the main watchdog counter and the prescaler is cleared. Differential Non-Linearity Differential non-linearity is the maximum difference between the actual and ideal code widths fo the converter. The code widths are the differences expressed in LSB between the code transition points, as the input voltage is varied through the range for the complete set of codes. WDCON Register MSB PRE1 PRE2 Gain Error Gain error is the deviation between the ideal and actual analog input voltage required to cause the final code transition to a full-scale output code after the offset error has been removed. This may sometimes be referred to as full scale error. PRE0 X X WDRUN WDTOF WDMOD Symbol Position Function WDCON.7 PRE2 Prescaler select (read/write). WDCON.6 PRE1 WDCON.5 PRE0 Offset Error Offset error is the difference between the actual input voltage that causes the first code transition and the ideal value to cause the first code transition. This ideal value is 1/2 LSB above Vref–. Channel to Channel Matching Channel to channel matching is the maximum difference between the corresponding code transitions of the actual characteristics taken from different channels under the same temperature, voltage and frequency conditions. These bits select theprescaler divide ratio according to the following table: PRE2 PRE1 PRE0 DIVISOR (FROM fOSC) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 12 × 64 12 × 64 × 2 12 × 64 × 4 12 × 64 × 8 12 × 64 × 16 12 × 64 × 32 12 × 64 × 64 12 × 64 × 128 WDCON.4 – Not used WDCON.3 – Not used WDCON.2 WDRUN Run control (read/write). This bit turns the timer on (WDRUN = 1) or off (WDRUN = 0) if the timer mode has been selected. WDCON.1 WDTOF Timeout flag (read/write). This bit is set when the watchdog timer underflows. It is cleared by an external reset and can be cleared by software. WDCON.0 WDMOD Mode selection (read/write). When WDMOD = 1, the watchdog is selected; when WDMOD = 0, the timer is selected. Selecting the watchdog mode automatically disables power-down mode. WDMOD is cleared by external reset. Once the watchdog mode is selected, this bit can only be cleared by writing a 0 to this bit and then performing a feed operation. Crosstalk Crosstalk is the measured level of a signal at the output of the converter resulting from a signal applied to one deselected channel. Total Error Maximum deviation of any step point from a line connecting the ideal first transition point to the ideal last transition point. Relative Accuracy Relative accuracy error is the deviation of the ADC’s actual code transition points from the ideal code transition points on a straight line which connects the ideal first code transition point and the final code transition point, after nullifying offset error and gain error. It is generally expressed in LSBs or in percent of FSR. 1998 May 01 LSB 10 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer A very specific sequence of events must take place to feed the watchdog timer; it cannot be fed accidentally by a runaway program. The following routines demonstrate setting up and feeding the watchdog timer. These routines apply to all versions of the 8XC550 except the ROM part when running from internal program memory. 80C550/83C550/87C550 Watchdog Detailed Operation EPROM Device (and ROMless Operation: EA = 0) In the ROMless operation (ROM part, EA = 0) and in the EPROM device, the watchdog operates in the following manner. Whether the watchdog is in the watchdog or timer mode, when external RESET is applied, the following takes place: – Watchdog mode bit set to timer mode. – Watchdog run control bit set to OFF. This routine sets up and starts the watchdog timer. This is not necessary for internal ROM operation, because setup of the watchdog timer on masked ROM parts is accomplished directly via ROM mask options. – – – – SetWD: MOV WDL,#0FFh ;Set watchdog reload value. MOV WDCON,#0E5;Set up timer prescaler, mode, and ;run bits. ACALL FeedWD ;Start watchdog with a feed ;operation. RET Autoload register set to FF (max count). Watchdog time-out flag cleared. Prescaler is cleared. Prescaler tap set to the highest divide. – Autoload takes place. The watchdog can be fed even though it is in the timer mode. This routine executes a watchdog timer feed operation, causing the timer to reload from WDL. Interrupts must be disabled during this operation due to the fact that the two feed registers must be loaded on consecutive instruction cycles, or a system reset will occur immediately. Note that the operational concept is for the watchdog mode of operation, when coming out of a hardware reset, the software should load the autoload registers, set the mode to watchdog, and then feed the watchdog (cause an autoload). The watchdog will now be starting at a known point. FeedWD:CLR EA ;This sequence must not be ;interrupted. MOV WFEED1,#0A5h;First instruction of feed sequence. MOV WFEED2,#05Ah;Second instruction of feed ;sequence. SETB EA ;Turn interrupts back on. RET If the watchdog is in the watchdog mode and running and happens to underflow at the time the external RESET is applied, the watchdog time-out flag will be cleared. When the watchdog is in the watchdog mode and the watchdog underflows, the following action takes place: – Autoload takes place. – Watchdog time-out flag is set – Timer mode interrupt flag unchanged. An interrupt is available to allow the watchdog timer to be used as a general purpose timer in applications where the watchdog function is not needed. The timer operates in the same manner when used as a general purpose timer except that the timer interrupt is generated on timer underflow instead of a chip reset. Refer to the 87C550 data sheet for additional information on watchdog timer operation. – – – – Programming the Watchdog Timer Mode bit unchanged. Watchdog run bit unchanged. Autoload register unchanged. Prescaler tap unchanged. – All other device action same as external reset. Both the EPROM and ROM devices have a set of SFRs for holding the watchdog autoload values and the control bits. The watchdog time-out flag is present in the watchdog control register and operates the same in all versions. In the EPROM device, the watchdog parameters (autoload value and control) are always taken from the SFRs. In the ROM device, the watchdog parameters can be mask programmed or taken from the SFRs. The selection to take the watchdog parameters from the SFRs or from the mask programmed values is controlled by EA (external access). When EA is high (internal ROM access), the watchdog parameters are taken from the mask programmed values. If the watchdog is masked programmed to the timer mode, then the autoload values and the pre-scaler taps are taken from the SFRs. When EA is low (external access), the watchdog parameters are taken from the SFRs. The user should be able to leave code in his program which initializes the watchdog SFRs even though he has migrated to the mask ROM part. This allows no code changes from EPROM prototyping to ROM coded production parts. Note that if the watchdog underflows, the program counter will start from 00H as in the case of an external reset. The watchdog time-out flag can be examined to determine if the watchdog has caused the reset condition. The watchdog time-out flag bit can be cleared by software. When the watchdog is in the timer mode and the timer software underflows, the following action takes place: – Autoload takes place. – Watchdog time-out flag is set – – – – Mode bit unchanged. Watchdog run bit unchanged. Autoload register unchanged. Prescaler tap unchanged. The timer mode interrupt flag is cleared when the interrupt routine is invoked. This bit can also be cleared directly by software without a software feed operation. Mask ROM Device (EA = 1) In the mask ROM device, the watchdog mode bit (WDMOD) is mask programmed and the bit in the watchdog command register is read only and reflects the mask programmed selection. If the mask programmed mode bit selects the timer mode, then the watchdog run bit (WDRUN) operates as described under EPROM Device. If the mask programmed bit selects the watchdog mode, then the watchdog run bit has no effect on the timer operation. 1998 May 01 11 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C550/83C550/87C550 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer Watchdog Function The watchdog consists of a programmable prescaler and the main timer. The prescaler derives its clock from the on-chip oscillator. The prescaler consists of a divide by 12 followed by a 13 stage counter with taps from stage 6 through stage 13. The tap selection is programmable. The watchdog main counter is a down counter clocked (decremented) each time the programmable prescaler underflows. The watchdog generates an underflow signal (and is autoloaded) when the watchdog is at count 0 and the clock to decrement the watchdog occurs. The watchdog is 8 bits long and the autoload value can range from 0 to FFH. (The autoload value of 0 is permissible since the prescaler is cleared upon autoload). Interrupt Enable Register MSB EA – W = tD / tMIN – 1 The software must be written so that a feed operation takes place every tD seconds from the last feed operation. Some tradeoffs may need to be made. It is not advisable to include feed operations in minor loops or in subroutines unless the feed operation is a specific subroutine. Interrupts The 8XC550 interrupt structure is a seven-source, two-priority level interrupt system similar to that of the standard 80C51 microcontroller. The interrupt sources are listed below in the order of their internal polling sequence. This is the order in which simultaneous interrupts of the same priority level would be serviced. WDTOF 0033H Lowest PT0 PX0 LSB PWD PAD PS PT1 PX1 Function Watchdog timer A/D conversion Serial port interrupt Timer 1 interrupt External interrupt 1 Timer 0 interrupt External interrupt 0 MSB SMOD LSB SIDL Symbol SMOD Position PCON.7 SIDL PCON.6 – – GF1 GF0 PD PCON.5 PCON.4 PCON.3 PCON.2 PCON.1 IDL PCON.0 FUNCTION External interrupt 0 Counter/timer 0 overflow External interrupt 1 Counter/timer 1 overflow Serial port transmit/receive A/D converter conversion complete Watchdog timer overflow (only when not in watchdog mode) – – GF1 GF0 PD 12 IDL Function Double baud rate bit. When set to a 1 and Timer 1 is used to generate baud rate, and the serial port is used in modes 1, 2, or 3. Separately idles the serial port for additional power savings. Reserved Reserved General-purpose flag bit. General-purpose flag bit. Power-down bit. Starting this bit activates power-down operation. Idle mode bit. Setting this bit activates idle mode operation. If 1s are written to PD and IDL at the same time, PD takes precedence. Interrupt Control Registers The standard 80C51 interrupt enable and priority registers have been modified slightly to take into account the additional interrupt sources of the 8XC550. 1998 May 01 EX0 Power Control Register Interrupt Priorities 0003H 000BH 0013H 001BH 0023H 002BH ET0 Power-Down and Idle Modes The 8XC550 includes the standard 80C51 power-down and idle modes of reduced power consumption. In addition, the 8XC550 includes an option to separately turn off the serial port for extra power savings when it is not needed. Also, the individual functional blocks such as the counter/timers are automatically disabled when they are not running. This actually turns off the clocks to the block in question, resulting in additional power savings. Note that when the watchdog timer is operating, the processor is inhibited from entering the power-down mode. This is due to the fact that the oscillator is stopped in the power-down mode, which would effectively turn off the watchdog timer. In keeping with the purpose of the watchdog timer, the processor is prevented from accidentally entering power-down due to some erroneous operation. prescaler = log2 (tMAX / (tOSC × 12 × 256)) – 6 INT0 TF0 INT1 TF1 TI & RI ADCI EX1 Function Global interrupt enable Watchdog timer overflow A/D conversion complete Serial port transmit or receive Timer 1 overflow External interrupt 1 Timer 0 overflow External interrupt 0 Symbol Position PWD IP.6 PAD IP.5 PS IP.4 PT1 IP.3 PX1 IP.2 PT0 IP.1 PX0 IP.0 This then also fixes tMIN. An autoload value would then be chosen from: Highest ET1 MSB Note that the design procedure is anticipated to be as follows. A tMAX will be chosen either from equipment or operation considerations and will most likely be the next convenient value higher than tD. (If the watchdog were inadvertently to start from FFH, an overflow would be guaranteed, barring other anomalies, to occur within tMAX). Then the value for the prescaler would be chosen from: VECTOR ADDRESS ES Interrupt Priority Register tMIN = tOSC × 12 × 64 tMAX = tMIN × 128 × 256 tD = tMIN × 2PRESCALER × W (where prescaler = 0, 1, 2, 3, 4, 5, 6, or 7) SOURCE EAD Symbol Position EA IE.7 EWD IE.6 EAD IE.5 ES IE.4 ET1 IE.3 EX1 IE.2 ET0 IE.1 EX0 IE.0 This leads to the following user design equations. Definitions: tOSC is the oscillator period, N is the selected prescaler tap value, W is the main counter autoload value, tMIN is the minimum watchdog time-out value (when the autoload value is 0), tMAX is the maximum time-out value (when the autoload value is FFH), tD is the design time-out value. PRIORITY LSB EWD Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer 80C550/83C550/87C550 remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator, as shown in the Block Diagram, page 3). To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed. Programmable Idle Modes The programmable idle modes have been dispersed throughout the functional blocks. Each block has its own ability to be disabled. For example, if timer 0 is not commanded to be running (TR = 0), then the clock to the timer is disabled resulting in an idle mode power saving. An additional idle control bit has been added to the serial communications port. IDLE MODE A/D Operation in Idle Mode In idle mode, the CPU puts itself to sleep while all of the on-chip peripherals except the A/D stay active. the instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. An A/D conversion in progress will be aborted when idle mode is entered. The CPU contents, the on-chip RAM, and all of the special function registers When in the idle mode, the A/D converter will be disabled. However, the current through the VREF pins will be present and will not be reduced internally in either the idle or the power-down modes. It is the responsibility of the user to disconnect VREF to reduce power supply current. MSB LSB PRE2 PRE1 PRE0 BIT WDCON.7 WDCON.6 WDCON.5 SYMBOL PRE2 PRE1 PRE0 0 0 0 0 1 1 1 1 WDCON.1 WDTOF WDCON.0 WDMOD X WDRUN WDTOF WDMOD FUNCTION Prescaler Select (Read/Write). Prescaler Select (Read/Write). Prescaler Select (Read/Write). Thses bits select the prescaler divide ratio according to the following table: PRE2 WDCON.4 — WDCON.3 — WDCON.2 WDRUN X PRE1 PRE0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 DIVISOR (from fOSC) 12 X 64 12 X 64 X 2 12 X 64 X 4 12 X 64 X 8 12 X 64 X 16 12 X 64 X 32 12 X 64 X 64 12 X 64 X 128 Not used. Not used. Run Control (Read/Write). This bit turns the timer on (WDRUN = 1) or off (WDRUN = 0) if the timer mode has been selected. Timeout Flag (Read/Write). This bit is set when the watchdog timer underflows. It is cleared by an external reset and can be cleared by software. Mode Selection (Read/Write). When WDMOD = 1, the watchdog mode is selected; when WDMOD = 0, the timer mode is selected. Selecting the watchdog mode automatically disables power-down mode. WDMOD is cleared by external reset. Once the watchdog mode is selected, this bit can only be cleared by writing a 0 to this bit and then performing a feed operation. SU00200 Figure 4. Watchdog Control Register (WDCON) 1998 May 01 13 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C550/83C550/87C550 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer DESIGN CONSIDERATIONS Security Bits At power-on, the voltage on VCC and RST must come up at the same time for a proper start-up. There are two security bits on the 83C550 and 87C550 that, when set, prevent the program data memory from being read out or programmed further. When the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when idle is terminated by reset, the instruction following the one that invokes idle should not be one that writes to a port pin or to external memory. Table 2 shows the state of I/O ports during low current operating modes. After the first security bit is programmed, the external MOVC instruction is disabled, and for the 87C550, further programming of the code memory or the encryption table is disabled. The other security bit can of course still be programmed. With only security bit one programmed, the memory can still be read out for program verification. After the second security bit is programmed, it is no longer possible to read out (verify) the program memory. To program the security bits for the 87C550, repeat the programming sequence using the “Pgm Security Bit” levels specified in Table 4. For the masked ROM 83C550 the security bit information is submitted with the ROM code as shown in Table 3. Encryption Table The encryption table is a feature of the 83C550 and 87C550 that protects the code from being easily read by anyone other than the programmer. The encryption table is 32 bytes of code that are exclusive NORed with the program code data as it is read out. The first byte is XNORed with the first location read, the second with the second read, etc. ROM Code Submission When submitting a ROM code for the 83C550, the following must be specified: 1. The 4k byte user ROM program. After the encryption table has been programmed, the user has to know its contents in order to correctly decode the program code data. The encryption table itself cannot be read out. 2. The 32 byte ROM encryption key. 3. The ROM security bits. For the EPROM (87C550) part, the encryption table is programmed in the same manner as the program memory, but using the “Pgm Encryption Table” levels specified in Table 4. After the encryption table is programmed, verification cycles will produce only encrypted information. 4. The watchdog timer parameters. This information can be submitted in an EPROM (2764) or hex file with the format specified in Table 3. For the ROM part (83C550) the encryption table information is submitted with the ROM code as shown in Table 3. Table 2. External Pin Status During Idle and Power-Down Modes PROGRAM MEMORY ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3 Idle MODE Internal 1 1 Data Data Data Data Idle External 1 1 Float Data Address Data Power-down Internal 0 0 Data Data Data Data Power-down External 0 0 Float Data Data Data Table 3. ROM Code Submittal Requirements ADDRESS CONTENT BIT(s) COMMENT 0000H to 0FFFH Data 7:0 User ROM data 1000H to 101FH Key 7:0 ROM encryption key; FFH = no encryption 1020H Security bit 0 ROM security bit 1 1020H Security bit 1 ROM security bit 2 0 = enable security feature 1 = disable security feature 1030H 1030H 1030H 1030H 1030H 1030H WDCON1 WDCON1 WDCON1 WDCON1 WDCON1 WDCON1 7:5 4 3 2 1 0 PRE2:0 Not used Not used WDRUN = 0, not ROM coded WDTOF = 0, not ROM coded WDMOD 1031H Not used 1032H WD 7:0 Watchdog autoload value (see specification) NOTE: 1. See Watchdog Timer Specification for definition of WDL and WDCON bits. 1998 May 01 14 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer 80C550/83C550/87C550 Electrical Deviations from Commercial Specifications for Extended Temperature Range DC and AC parameters not included here are the same as in the commercial temperature range table. DC ELECTRICAL CHARACTERISTICS Tamb = –40°C to +85°C, VCC = 5V ±10% (87C550), VCC = 5V ±20% (80/83C550), VSS = 0V TEST SYMBOL PARAMETER CONDITIONS VIL Input low voltage, except EA VIL1 Input low voltage to EA VIH Input high voltage, except XTAL1, RST VIH1 Input high voltage to XTAL1, RST IIL Logical 0 input current, ports 2, 3 VIN = 0.45V ITL Logical 1-to-0 transition current, ports 2, 3 VIN = 2.0V ICC Power supply current: Active mode Idle mode Power down mode LIMITS MIN MAX UNIT –0.5 0.2VCC–0.15 V 0 0.2VCC–0.35 V 0.2VCC+1 VCC+0.5 V 0.7VCC+0.1 VCC+0.5 V –75 µA –750 µA 35 6 50 mA mA µA MAX UNIT VCC = 4.5–5.5V, Frequency range = 3.5 to 16MHz ADC DC ELECTRICAL CHARACTERISTICS AVCC = 5V ±10%, AVSS = 0V, Tamb = –40°C to 85°C, unless otherwise specified TEST SYMBOL PARAMETER CONDITIONS AVCC = VCC ± 0.2 LIMITS MIN AVCC Analog supply VREF Analog reference; AVREF+ AVREF– 4.5 5.5 V AVSS – 0.2 AVCC + 0.2 V AICC Analog operating supply current AVIN Analog input voltage 3.0 mA AVSS – 0.2 AVCC + 0.2 V AIC, CIA Analog input capacitance tADS Sampling time 8tCY 15 pF tADC Conversion time 40tCY Ae Absolute voltage error ±1.5 LSB ERA Relative accuracy ±1 LSB OSe Offset error See note 1 ±1 LSB Ge Gain error See note 1 0.4 % MCTC Channel-to-channel matching ±1 LSB Ct Crosstalk 0 – 100kHz –60 dB Rref Resistance between AVREF+ and AVREF– 10.0 KΩ AIID Idle mode supply current 50 µA See note 1 1.0 See note 4 AIPD Power down supply current See note 4 50 µA NOTES: 1. Conditions: VREF+ = 4.99712V, VREF– = 0V. AICC value does not include the resistor ladder current. For the 40-pin package, where the VREF– inputs are connected to AVCC and AVSS, the current AICC will be increased by the register ladder current and may exceed the maximum shown here. 2. The resistor ladder network is not disconnected in the power-down or idle modes. Thus to conserve power, the user must remove AVCC and VREF+. 3. If the A/D function is not required, or if the A/D function is only needed periodically, AVCC can be removed without affecting the operation of the digital circuitry. Contents of ADCON and ADAT are not guaranteed to be valid. Digital inputs P1.0 to P1.7 will not function normally. No digital outputs are present on these pins. 4. For this test, the Analog inputs must be at the supplies (either VDD or VSS). 1998 May 01 15 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer 80C550/83C550/87C550 ABSOLUTE MAXIMUM RATINGS1, 2, 3 RATING UNIT Operating temperature under bias PARAMETER –40 to +85 °C Storage temperature range –65 to +150 °C Voltage on EA/VPP pin to VSS (87C550 only) Voltage on any other pin to VSS 0 to +13.0 V –0.5 to +6.5 V ±10 mA Input, output current on any two I/O pins Power dissipation (based on package heat transfer limitations, not device power consumption) 1.5 W NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. DC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10% (87C550), VCC = 5V ±20% (80/83C550), VSS = 0V TEST SYMBOL VIL PARAMETER CONDITIONS Input low voltage, except EA7 EA7 VIL1 Input low voltage to VIH Input high voltage, except XTAL1, RST7 VIH1 Input high voltage, XTAL1, RST7 MIN TYPICAL1 MAX UNIT –0.5 0.2VCC–0.1 V 0 0.2VCC–0.3 V 0.2VCC+0.9 VCC+0.5 V 0.7VCC VCC+0.5 V 1.6mA2 0.45 V 0.45 V VOL Output low voltage, ports 2, 3 IOL = VOL1 Output low voltage, port 0, ALE, PSEN IOL = 3.2mA2 PSEN3 LIMITS VOH Output high voltage, ports 2, 3, ALE, VOH1 Output high voltage (port 0 in external bus mode) IIL Logical 0 input current, ports 1, 2, 37 VIN = 0.45V –50 µA ITL Logical 1-to-0 transition current, ports 1, 2, 37 See note 4 –650 µA ILI Input leakage current, port 0 VIN = VIL or VIH +10 µA ICC Power supply current (does not include AICC):7 Active mode @ 16MHz5 Idle mode @ 16MHz Power down mode 25 5 50 mA mA µA 300 kΩ RRST IOH = –60µA, IOH = –25µA IOH = –10µA 2.4 0.75VCC 0.9VCC V V V IOH = –800µA, IOH = –300µA IOH = –80µA 2.4 0.75VCC 0.9VCC V V V See note 6 11.5 1.3 3 Internal reset pull-down resistor 50 CIO Pin capacitance (I/O pins only) 10 pF NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the address bits are stabilizing. 4. Pins of ports 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 5. ICCMAX at other frequencies is given by: Active mode; ICCMAX = 1.43 × FREQ + 1.90: Idle mode; ICCMAX = 0.14 × FREQ +2.31, where FREQ is the external oscillator frequency in MHz. ICCMAX is given in mA. See Figure 12. 6. See Figures 13 through 16 for ICC test conditions. 7. These values apply only to Tamb = 0°C to +70°C. For Tamb = –40°C to +85°C. See table on previous page. 1998 May 01 16 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C550/83C550/87C550 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10% (87C550), VCC = 5V ±20% (80/83C550), VSS = 0V1, 2 16MHz CLOCK SYMBOL FIGURE PARAMETER MIN MAX VARIABLE CLOCK MIN MAX UNIT 3.5 16 MHz 1/tCLCL 5 Oscillator frequency: Speed Versions S8XC550 Exx tLHLL 5 ALE pulse width tAVLL 5 tLLAX 5 tLLIV 5 ALE low to valid instruction in tLLPL 5 ALE low to PSEN low 22 tCLCL–40 ns tPLPH 5 PSEN pulse width 142 3tCLCL–45 ns tPLIV 5 PSEN low to valid instruction in tPXIX 5 Input instruction hold after PSEN tPXIZ 5 Input instruction float after PSEN 37 tCLCL–25 ns tAVIV 5 Address to valid instruction in 207 5tCLCL–105 ns tPLAZ 5 PSEN low to address float 10 10 ns 85 2tCLCL–40 ns Address valid to ALE low 7 tCLCL–55 ns Address hold after ALE low 27 tCLCL–35 ns 150 4tCLCL–100 82 0 3tCLCL–105 0 ns ns ns Data Memory tRLRH 6, 7 RD pulse width 275 6tCLCL–100 ns tWLWH 6, 7 WR pulse width 275 6tCLCL–100 ns tRLDV 6, 7 RD low to valid data in tRHDX 6, 7 Data hold after RD tRHDZ 6, 7 Data float after RD 55 2tCLCL–70 ns tLLDV 6, 7 ALE low to valid data in 350 8tCLCL–150 ns tAVDV 6, 7 Address to valid data in 397 9tCLCL–165 ns tLLWL 6, 7 ALE low to RD or WR low 137 3tCLCL+50 ns tAVWL 6, 7 Address valid to WR low or RD low 120 4tCLCL–130 ns tQVWX 6, 7 Data valid to WR transition 12 tCLCL–50 ns tWHQX 6, 7 Data hold after WR 12 tCLCL–50 ns tRLAZ 6, 7 RD low to address float tWHLH 6, 7 RD or WR high to ALE high 22 212 0 5tCLCL–165 0 247 3tCLCL–50 0 102 tCLCL–40 ns ns 0 ns tCLCL+40 ns External Clock tCHCX 9 High time 20 20 ns tCLCX 9 Low time 20 20 ns tCLCH 9 Rise time 20 20 ns tCHCL 9 Fall time 20 20 ns tXLXL 8 Serial port clock cycle time 750 12tCLCL ns tQVXH 8 Output data setup to clock rising edge 492 10tCLCL–133 ns tXHQX 8 Output data hold after clock rising edge 8 2tCLCL–117 ns tXHDX 8 Input data hold after clock rising edge 0 0 Shift Register tXHDV 8 Clock rising edge to input data valid 492 NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 1998 May 01 17 ns 10tCLCL–133 ns Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C550/83C550/87C550 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer EXPLANATION OF THE AC SYMBOLS P – PSEN Q – Output data R – RD signal t – Time V – Valid W – WR signal X – No longer a valid logic level Z – Float Examples: tAVLL = Time for address valid to ALE low. tLLPL = Time for ALE low to PSEN low. Each timing symbol has five characters. The first character is always ‘t’ (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A – Address C – Clock D – Input data H – Logic level high I – Instruction (program memory contents) L – Logic level low, or ALE tLHLL ALE tAVLL tLLPL tPLPH tLLIV tPLIV PSEN tLLAX A0–A7 PORT 0 tPXIZ tPLAZ tPXIX A0–A7 INSTR IN tAVIV PORT 2 A0–A15 A8–A15 SU00006 Figure 5. External Program Memory Read Cycle ALE tWHLH PSEN tLLDV tLLWL tRLRH RD tAVLL tLLAX tRLAZ PORT 0 tRHDZ tRLDV tRHDX A0–A7 FROM RI OR DPL DATA IN A0–A7 FROM PCL INSTR IN tAVWL tAVDV PORT 2 P2.0–P2.7 OR A8–A15 FROM DPF A0–A15 FROM PCH SU00025 Figure 6. External Data Memory Read Cycle 1998 May 01 18 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C550/83C550/87C550 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer ALE tWHLH PSEN tWLWH tLLWL WR tLLAX tAVLL A0–A7 FROM RI OR DPL PORT 0 tWHQX tQVWX DATA OUT A0–A7 FROM PCL INSTR IN tAVWL PORT 2 P2.0–P2.7 OR A8–A15 FROM DPF A0–A15 FROM PCH SU00069 Figure 7. External Data Memory Write Cycle INSTRUCTION 0 1 2 3 4 5 6 7 8 ALE tXLXL CLOCK tXHQX tQVXH OUTPUT DATA 0 1 2 WRITE TO SBUF 3 4 5 6 7 tXHDX tXHDV SET TI INPUT DATA VALID VALID VALID VALID VALID VALID VALID VALID CLEAR RI SET RI SU00027 Figure 8. Shift Register Mode Timing VCC–0.5 0.45V 0.7VCC 0.2VCC–0.1 tCHCL tCHCX tCLCH tCLCX tCLCL SU00009 Figure 9. External Clock Drive 1998 May 01 19 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C550/83C550/87C550 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer VCC–0.5 0.45V VLOAD+0.1V 0.2VCC+0.9 TIMING REFERENCE POINTS VLOAD VLOAD–0.1V 0.2VCC–0.1 SU00011 SU00717 Figure 10. AC Testing Input/Output Figure 11. Float Waveform 30 25 MAX ACTIVE MODE 20 15 TYP ACTIVE MODE 10 5 MAX IDLE MODE TYP IDLE MODE 4MHz 8MHz 12MHz 16MHz FREQ at XTAL1 SU00201 Figure 12. ICC vs. FREQ (Commercial Temp. Range) Valid only within frequency specifications of the device under test 1998 May 01 VOL+0.1V NOTE: For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded VOH/VOL level occurs. IOH/IOL ≥ ±20mA. NOTE: AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’. ICC mA VOH–0.1V 20 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C550/83C550/87C550 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer VCC VCC ICC ICC VCC VCC VCC VCC RST P0 RST VCC P1 EA P0 (NC) XTAL2 CLOCK SIGNAL XTAL1 (NC) XTAL2 CLOCK SIGNAL XTAL1 P1 EA VSS VSS SU00202 SU00203 Figure 13. ICC Test Condition, Active Mode All other pins are disconnected VCC–0.5 0.45V Figure 14. ICC Test Condition, Idle Mode All other pins are disconnected 0.7VCC 0.2VCC–0.1 tCHCL tCHCX tCLCH tCLCX tCLCL SU00009 Figure 15. Clock Signal Waveform for ICC Tests in Active and Idle Modes tCLCH = tCHCL = 5ns VCC ICC VCC RST VCC P1 P0 (NC) XTAL2 EA XTAL1 VSS SU00204 Figure 16. ICC Test Condition, Power Down Mode All other pins are disconnected. VCC = 2V to 5.5V. 1998 May 01 21 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C550/83C550/87C550 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer programmed, further programming of the code memory and encryption table is disabled. However, the other security bit can still be programmed. EPROM CHARACTERISTICS The 87C550 is programmed by using a modified Quick-Pulse Programming algorithm. It differs from older methods in the value used for VPP (programming supply voltage) and in the width and number of the ALE/PROG pulses. Note that the EA/VPP pin must not be allowed to go above the maximum specified VPP level for any amount of time. Even a narrow glitch above that voltage can cause permanent damage to the device. The VPP source should be well regulated and free of glitches and overshoot. The 87C550 contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as an S87C550 manufactured by Philips. Program Verification If security bit 2 has not been programmed, the on-chip program memory can be read out for program verification. The address of the program memory locations to be read is applied to ports 2 and 3 as shown in Figure 19. The other pins are held at the ‘Verify Code Data’ levels indicated in Table 4. The contents of the address location will be emitted on port 0. External pull-ups are required on port 0 for this operation. Table 4 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the lock bits. The circuit configuration and waveforms for quick-pulse programming are shown in Figures 17 and 18. Figure 19 shows the circuit configuration for normal program memory verification. Quick-Pulse Programming The setup for microcontroller quick-pulse programming is shown in Figure 17. Note that the 87C550 is running with a 4 to 6MHz oscillator. The reason the oscillator needs to be running is that the device is executing internal address and program data transfers. If the encryption table has been programmed, the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will have to know the encryption table contents in order to correctly decode the verification data. The encryption table itself cannot be read out. The address of the EPROM location to be programmed is applied to ports 2 and 3, as shown in Figure 17. The code byte to be programmed into that location is applied to port 0. RST, PSEN and pins of ports 1 and 2 specified in Table 4 are held at the ‘Program Code Data’ levels indicated in Table 4. The ALE/PROG is pulsed low 25 times as shown in Figure 18. Reading the Signature Bytes The signature bytes are read by the same procedure as a normal verification of locations 030H and 031H, except that P1.0 and P1.1 need to be pulled to a logic low. The values are: (030H) = 15H indicates manufactured by Philips (031H) = 96H indicates S87C550 To program the encryption table, repeat the 25 pulse programming sequence for addresses 0 through 1FH, using the ‘Pgm Encryption Table’ levels. Do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. Program/Verify Algorithms Any algorithm in agreement with the conditions listed in Table 4, and which satisfies the timing specifications, is suitable. To program the security bits, repeat the 25 pulse programming sequence using the ‘Pgm Security Bit’ levels. After one security bit is Table 4. EPROM Programming Modes MODE RST PSEN ALE/PROG EA/VPP P2.7 P2.6 P1.1 P1.0 Read signature 1 0 1 1 0 0 0 0 Program code data 1 0 0* VPP 1 0 1 1 Verify code data 1 0 1 1 0 0 1 1 Pgm encryption table 1 0 0* VPP 1 0 1 0 Pgm security bit 1 1 0 0* VPP 1 1 1 1 Pgm security bit 2 1 0 0* VPP 1 1 0 0 NOTES: 1. ’0’ = Valid low for that pin, ’1’ = valid high for that pin. 2. VPP = 12.75V ±0.25V. 3. VCC = 5V±10% during programming and verification. * ALE/PROG receives 25 programming pulses while VPP is held at 12.75V. Each programming pulse is low for 100µs (±10µs) and high for a minimum of 10µs. Trademark phrase of Intel Corporation. 1998 May 01 22 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C550/83C550/87C550 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer +5V AVCC VCC A0–A7 P3 P0 1 RST EA/VPP 1 P1.0 ALE/PROG 1 P1.1 87C550 XTAL2 4–6MHz XTAL1 PGM DATA +12.75V 25 100µs PULSES TO GROUND PSEN 0 P2.7 1 P2.6 0 A8–A11 P2.0–P2.4 AVSS VSS SU00205 Figure 17. Programming Configuration 25 PULSES 1 ALE/PROG: 0 10µs MIN 1 ALE/PROG: 100µs+10 0 SU00018 Figure 18. PROG Waveform +5V AVCC VCC A0–A7 P3 1 RST 1 P1.0 1 P1.1 P0 87C550 XTAL2 4–6MHz XTAL1 PGM Data EA/VPP 1 ALE/PROG 1 PSEN 0 P2.7 0 ENABLE P2.6 0 P2.0–P2.4 A8–A11 AVSS VSS SU00206 Figure 19. Program Verification 1998 May 01 23 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 80C550/83C550/87C550 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS Tamb = 21°C to +27°C, VCC = 5V±10%, VSS = 0V (See Figure 20) SYMBOL PARAMETER MIN MAX 12.5 13.0 V 50 mA 6 MHz VPP Programming supply voltage IPP Programming supply current 1/tCLCL Oscillator frequency tAVGL Address setup to PROG low 48tCLCL tGHAX Address hold after PROG 48tCLCL tDVGL Data setup to PROG low 48tCLCL tGHDX Data hold after PROG 48tCLCL tEHSH P2.7 (ENABLE) high to VPP 48tCLCL tSHGL VPP setup to PROG low 10 tGHSL VPP hold after PROG 10 tGLGH PROG width 90 tAVQV Address to data valid 48tCLCL tELQZ ENABLE low to data valid 48tCLCL tEHQZ Data float after ENABLE 0 tGHGL PROG high to PROG low 10 4 µs µs µs 110 48tCLCL µs PROGRAMMING* VERIFICATION* ADDRESS ADDRESS P3.0–P3.7 P2.0–P2.4 UNIT tAVQV DATA IN PORT 0 DATA OUT tDVGL tGHDX tAVGL tGHAX ALE/PROG tGHGL tGHSL tGLGH tSHGL LOGIC 1 LOGIC 1 EA/VPP LOGIC 0 tEHSH tELQV tEHQZ P2.7 ENABLE SU00207 NOTE: * FOR PROGRAMMING VERIFICATION, SEE FIGURE 17. FOR VERIFICATION CONDITIONS, SEE FIGURE 19. Figure 20. EPROM Programming and Verification 1998 May 01 24 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer DIP40: plastic dual in-line package; 40 leads (600 mil) 1998 May 01 25 80C550/83C550/87C550 SOT129-1 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer PLCC44: plastic leaded chip carrier; 44 leads 1998 May 01 80C550/83C550/87C550 SOT187-2 26 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer NOTES 1998 May 01 27 80C550/83C550/87C550 Philips Semiconductors Product specification 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer 80C550/83C550/87C550 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 05-98 Document order number: 1998 May 01 28 9397 750 03853