74HC75 Quad bistable transparant latch Rev. 03 — 12 November 2004 Product data sheet 1. General description The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDEC standard no. 7A. The 74HC75 has four bistable latches. The two latches are simultaneously controlled by one of two active HIGH enable inputs (LE12 and LE34). When LEnn is HIGH, the data enters the latches and appears at the nQ outputs. The nQ outputs follow the data inputs (nD) as long as LEnn is HIGH (transparent). The data on the nD inputs one set-up time prior to the HIGH-to-LOW transition of the LEnn will be stored in the latches. The latched outputs remain stable as long as the LEnn is LOW. 2. Features ■ ■ ■ ■ ■ Complementary Q and Q outputs VCC and GND on the center pins Low-power dissipation Complies with JEDEC standard no. 7A ESD protection: ◆ HBM EIA/JESD22-A114-B exceeds 2000 V ◆ MM EIA/JESD22-A115-A exceeds 200 V. ■ Multiple package options ■ Specified from −40 °C to +80 °C and from −40 °C to +125 °C. 74HC75 Philips Semiconductors Quad bistable transparant latch 3. Quick reference data Table 1: Quick reference data Symbol Parameter Conditions tPHL, tPLH propagation delay CL = 15 pF; VCC = 5 V Max Unit nD to nQ, nQ - 11 - ns - 11 - ns - 3.5 - pF - 42 - pF power dissipation capacitance per latch CPD Typ LEnn to nQ, nQ input capacitance CI [1] Min VI = GND to VCC [1] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 4. Ordering information Table 2: Ordering information Type number Package Temperature range Name Description 74HC75N −40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74HC75D −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HC75DB −40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74HC75PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 9397 750 13816 Product data sheet Version © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 2 of 20 74HC75 Philips Semiconductors Quad bistable transparant latch 5. Functional diagram 2 13 1D LE12 D Q 1Q 1Q CP 16 1 L1 3 2D D Q 2Q 2Q CP 13 15 LE12 2 14 3 L2 1Q 1D 1Q 2Q 2D 2Q 16 1 15 14 L1,2 6 4 3D LE34 D Q 3Q 3Q CP L3,4 10 11 7 D 7 3Q 3D 3Q 4Q 4D 4Q L3 4D 6 LE34 4 Q 4Q 4Q CP 10 11 9 8 001aab851 9 8 L4 001aab853 Fig 1. Functional diagram 9397 750 13816 Product data sheet Fig 2. Logic symbol © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 3 of 20 74HC75 Philips Semiconductors Quad bistable transparant latch 1D D CP LE12 13 1Q 1Q LATCH 1 C1 16 2 Q 1D 2D D Q 2Q 1 CP 15 2Q 3 14 4 LATCH 2 C1 3D D Q 3Q 9 7 1D CP LE34 8 3Q LATCH 3 10 6 11 001aab852 4D D Q CP LATCH 4 Fig 3. IEC logic symbol 4Q 4Q 001aab854 Fig 4. Logic diagram 6. Pinning information 6.1 Pinning 1Q 1 16 1Q 1D 2 15 2Q 2D 3 14 2Q LE34 4 13 LE12 75 VCC 5 12 GND 3D 6 11 3Q 4D 7 10 3Q 4Q 8 9 4Q 001aab850 Fig 5. Pin configuration 9397 750 13816 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 4 of 20 74HC75 Philips Semiconductors Quad bistable transparant latch 6.2 Pin description Table 3: Pin description Symbol Pin Description 1Q 1 complementary latch output 1 1D 2 data input 1 2D 3 data input 2 LE34 4 latch enable input for latches 3 and 4 (active HIGH) VCC 5 positive supply voltage 3D 6 data input 3 4D 7 data input 4 4Q 8 complementary latch output 4 4Q 9 latch output 4 3Q 10 latch output 3 3Q 11 complementary latch output 3 GND 12 ground (0 V) LE12 13 latch enable input for latches 1 and 2 (active HIGH) 2Q 14 complementary latch output 2 2Q 15 latch output 2 1Q 16 latch output 1 7. Functional description 7.1 Function table Table 4: Function table [1] Operating mode Input LEnn nD nQ nQ Data enabled H L L H H H H L L X q q Data latched [1] Output H = HIGH voltage level; L = LOW voltage level; q = lower case letters indicate the state of the referenced output one set-up time prior to the HIGH-to-LOW LEnn transition; X = don’t care. 9397 750 13816 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 5 of 20 74HC75 Philips Semiconductors Quad bistable transparant latch 8. Limiting values Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage IIK input diode current VI < −0.5 V or VI > VCC + 0.5 V −0.5 +7 V - ±20 mA IOK output diode current VO < −0.5 V or VO > VCC + 0.5 V - ±20 mA IO output source or sink current VO = −0.5 V to VCC + 0.5 V - ±25 mA ICC, IGND VCC or GND current - ±50 mA Tstg storage temperature −65 +150 °C Ptot power dissipation DIP16 package [1] - 750 mW SO16, SSOP16 and TSSOP16 packages [2] - 500 mW [1] Above 70 °C: Ptot derates linearly with 12 mW/K. [2] Above 70 °C: Ptot derates linearly with 8 mW/K. 9. Recommended operating conditions Table 6: Recommended operating conditions Symbol Parameter Conditions Typ Max Unit VCC supply voltage 2.0 5.0 6.0 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V tr, tf input rise and fall times VCC = 2.0 V - - 1000 ns VCC = 4.5 V - 6.0 500 ns VCC = 6.0 V - - 400 ns −40 - +125 °C Tamb ambient temperature 9397 750 13816 Product data sheet Min © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 6 of 20 74HC75 Philips Semiconductors Quad bistable transparant latch 10. Static characteristics Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit Tamb = 25 °C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VCC = 2.0 V 1.5 1.2 - V VCC = 4.5 V 3.15 2.4 - V VCC = 6.0 V 4.2 3.2 - V VCC = 2.0 V - 0.8 0.5 V VCC = 4.5 V - 2.1 1.35 V VCC = 6.0 V - 2.8 1.8 V IO = −20 µA; VCC = 2.0 V 1.9 2.0 - V IO = −20 µA; VCC = 4.5 V 4.4 4.5 - V IO = −20 µA; VCC = 6.0 V 5.9 6.0 - V IO = −4 mA; VCC = 4.5 V 3.98 4.32 - V IO = −5.2 mA; VCC = 6.0 V 5.48 5.81 - V IO = 20 µA; VCC = 2.0 V - 0 0.1 V IO = 20 µA; VCC = 4.5 V - 0 0.1 V IO = 20 µA; VCC = 6.0 V - 0 0.1 V IO = 4 mA; VCC = 4.5 V - 0.15 0.26 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 V VI = VIH or VIL VI = VIH or VIL ILI input leakage current VI = VCC or GND; VCC = 6.0 V - - ±0.1 µA ICC quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 µA CI input capacitance - 3.5 - pF VCC = 2.0 V 1.5 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 2.0 V - - 0.5 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V IO = −20 µA; VCC = 2.0 V 1.9 - - V IO = −20 µA; VCC = 4.5 V 4.4 - - V IO = −20 µA; VCC = 6.0 V 5.9 - - V IO = −4 mA; VCC = 4.5 V 3.84 - - V IO = −5.2 mA; VCC = 6.0 V 5.34 - - V Tamb = −40 °C to +85 °C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL 9397 750 13816 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 7 of 20 74HC75 Philips Semiconductors Quad bistable transparant latch Table 7: Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA; VCC = 2.0 V - - 0.1 V IO = 20 µA; VCC = 4.5 V - - 0.1 V IO = 20 µA; VCC = 6.0 V - - 0.1 V IO = 4 mA; VCC = 4.5 V - - 0.33 V IO = 5.2 mA; VCC = 6.0 V - - 0.33 V ILI input leakage current VI = VCC or GND; VCC = 6.0 V - - ±1.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 80 µA Tamb = −40 °C to +125 °C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VCC = 2.0 V 1.5 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 2.0 V - - 0.5 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V VI = VIH or VIL - IO = −20 µA; VCC = 2.0 V 1.9 - - V IO = −20 µA; VCC = 4.5 V 4.4 - - V IO = −20 µA; VCC = 6.0 V 5.9 - - V IO = −4 mA; VCC = 4.5 V 3.7 - - V IO = −5.2 mA; VCC = 6.0 V 5.2 - - V IO = 20 µA; VCC = 2.0 V - - 0.1 V IO = 20 µA; VCC = 4.5 V - - 0.1 V IO = 20 µA; VCC = 6.0 V - - 0.1 V IO = 4 mA; VCC = 4.5 V - - 0.4 V IO = 5.2 mA; VCC = 6.0 V - - 0.4 V VI = VIH or VIL - ILI input leakage current VI = VCC or GND; VCC = 6.0 V - - ±1.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 160 µA 9397 750 13816 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 8 of 20 74HC75 Philips Semiconductors Quad bistable transparant latch 11. Dynamic characteristics Table 8: Dynamic characteristics GND = 0 V; tr = tf = 6 ns; CL = 50 pF; unless otherwise specified, see Figure 10. Symbol Parameter Conditions Min Typ Max Unit propagation delay nD to nQ see Figure 6 VCC = 2.0 V - 33 110 ns VCC = 4.5 V - 12 22 ns VCC = 6.0 V - 10 19 ns VCC = 5.0 V; CL = 15 pF - 11 - ns VCC = 2.0 V - 39 120 ns VCC = 4.5 V - 14 24 ns Tamb = 25 °C tPHL, tPLH propagation delay nD to nQ propagation delay LEnn to nQ propagation delay LEnn to nQ tTHL, tTLH tW tsu th output transition time enable pulse width HIGH set-up time nD to LEnn hold time nD to LEnn see Figure 7 VCC = 6.0 V - 11 20 ns VCC = 5.0 V; CL = 15 pF - 11 - ns VCC = 2.0 V - 33 120 ns VCC = 4.5 V - 12 24 ns VCC = 6.0 V - 10 20 ns VCC = 5.0 V; CL = 15 pF - 11 - ns see Figure 9 see Figure 9 VCC = 2.0 V - 39 125 ns VCC = 4.5 V - 14 25 ns VCC = 6.0 V - 11 21 ns VCC = 5.0 V; CL = 15 pF - 11 - ns VCC = 2.0 V - 19 75 ns VCC = 4.5 V - 7 15 ns VCC = 6.0 V - 6 13 ns VCC = 2.0 V 80 17 - ns VCC = 4.5 V 16 6 - ns VCC = 6.0 V 14 5 - ns VCC = 2.0 V 60 14 - ns VCC = 4.5 V 12 5 - ns VCC = 6.0 V 10 4 - ns VCC = 2.0 V 3 −8 - ns VCC = 4.5 V 3 −3 - ns VCC = 6.0 V 3 −2 - ns see Figure 6 and 7 see Figure 9 see Figure 8 see Figure 8 9397 750 13816 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 9 of 20 74HC75 Philips Semiconductors Quad bistable transparant latch Table 8: Dynamic characteristics …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; unless otherwise specified, see Figure 10. Symbol CPD Parameter power dissipation capacitance per latch Conditions Min Typ Max Unit - 42 - pF VCC = 2.0 V - - 140 ns VCC = 4.5 V - - 28 ns VCC = 6.0 V - - 24 ns VCC = 2.0 V - - 150 ns VCC = 4.5 V - - 30 ns VCC = 6.0 V - - 26 ns VCC = 2.0 V - - 150 ns VCC = 4.5 V - - 30 ns VCC = 6.0 V - - 26 ns VCC = 2.0 V - - 155 ns VCC = 4.5 V - - 31 ns VCC = 6.0 V - - 26 ns VCC = 2.0 V - - 95 ns VCC = 4.5 V - - 19 ns VCC = 6.0 V - - 16 ns VCC = 2.0 V 100 - - ns VCC = 4.5 V 20 - - ns VCC = 6.0 V 17 - - ns VCC = 2.0 V 75 - - ns VCC = 4.5 V 15 - - ns VCC = 6.0 V 13 - - ns VCC = 2.0 V 3 - - ns VCC = 4.5 V 3 - - ns VCC = 6.0 V 3 - - ns VI = GND to VCC [1] Tamb = −40 °C to +85 °C tPHL, tPLH propagation delay nD to nQ propagation delay nD to nQ propagation delay LEnn to nQ propagation delay LEnn to nQ tTHL, tTLH tW tsu th output transition time enable pulse width HIGH set-up time nD to LEnn hold time nD to LEnn see Figure 6 see Figure 7 see Figure 9 see Figure 9 see Figure 6 and 7 see Figure 9 see Figure 8 see Figure 8 9397 750 13816 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 10 of 20 74HC75 Philips Semiconductors Quad bistable transparant latch Table 8: Dynamic characteristics …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; unless otherwise specified, see Figure 10. Symbol Parameter Conditions Min Typ Max Unit Tamb = −40 °C to +125 °C tPHL, tPLH propagation delay nD to nQ propagation delay nD to nQ propagation delay LEnn to nQ propagation delay LEnn to nQ tTHL, tTLH enable pulse width HIGH tW set-up time nD to LEnn tsu hold time nD to LEnn th [1] output transition time see Figure 6 VCC = 2.0 V - - 165 ns VCC = 4.5 V - - 33 ns VCC = 6.0 V - - 28 ns see Figure 7 VCC = 2.0 V - - 180 ns VCC = 4.5 V - - 36 ns VCC = 6.0 V - - 31 ns see Figure 9 VCC = 2.0 V - - 180 ns VCC = 4.5 V - - 36 ns VCC = 6.0 V - - 31 ns see Figure 9 VCC = 2.0 V - - 190 ns VCC = 4.5 V - - 38 ns VCC = 6.0 V - - 32 ns see Figure 6 and 7 VCC = 2.0 V - - 110 ns VCC = 4.5 V - - 22 ns VCC = 6.0 V - - 19 ns see Figure 9 VCC = 2.0 V 120 - - ns VCC = 4.5 V 24 - - ns VCC = 6.0 V 20 - - ns see Figure 8 VCC = 2.0 V 90 - - ns VCC = 4.5 V 18 - - ns VCC = 6.0 V 15 - - ns see Figure 8 VCC = 2.0 V 3 - - ns VCC = 4.5 V 3 - - ns VCC = 6.0 V 3 - - ns CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 9397 750 13816 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 11 of 20 74HC75 Philips Semiconductors Quad bistable transparant latch 12. Waveforms nD input VM tPHL nQ output tPLH VM tTHL tTLH 001aab855 VM = 0.5 × VI. Fig 6. Waveforms showing the data input (nD) to output (nQ) propagation delays and the output transition times nD input VM tPHL nQ output tPLH VM tTHL tTLH 001aab856 VM = 0.5 × VI. Fig 7. Waveforms showing the data input (nD) to output (nQ) propagation delays and the output transition times nD input VM tsu tsu th VM LEnn input nQ output th Q=D Q=D 001aab858 The shaded areas indicate when the input is permitted to change for predictable output performance. VM = 0.5 × VI. Fig 8. Waveforms showing the data set-up and hold times for nD input to LEnn input 9397 750 13816 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 12 of 20 74HC75 Philips Semiconductors Quad bistable transparant latch nD input LEnn input VM tW tPHL VM nQ output tPLH nQ output tPLH tTHL tPHL tTLH VM tTLH tTHL 001aab857 VM = 0.5 × VI. Fig 9. Waveforms showing the latch enable input (LEnn) pulse width, the latch enable input to outputs (nQ, nQ) propagation delays and the output transition times VCC PULSE GENERATOR VI VO D.U.T. RT CL mna101 Test data is given in Table 9. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. Fig 10. Load circuitry for switching times Table 9: Test data Supply Input Load VCC VI tr, tf CL 2.0 V VCC 6 ns 50 pF 4.5 V VCC 6 ns 50 pF 6.0 V VCC 6 ns 50 pF 5.0 V VCC 6 ns 15 pF 9397 750 13816 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 13 of 20 74HC75 Philips Semiconductors Quad bistable transparant latch 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 11. Package outline SOT38-4 (DIP16) 9397 750 13816 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 14 of 20 74HC75 Philips Semiconductors Quad bistable transparant latch SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SOT109-1 (SO16) 9397 750 13816 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 15 of 20 74HC75 Philips Semiconductors Quad bistable transparant latch SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC JEITA MO-150 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 13. Package outline SOT338-1 (SSOP16) 9397 750 13816 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 16 of 20 74HC75 Philips Semiconductors Quad bistable transparant latch TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 14. Package outline SOT403-1 (TSSOP16) 9397 750 13816 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 17 of 20 74HC75 Philips Semiconductors Quad bistable transparant latch 14. Revision history Table 10: Revision history Document ID Release date Data sheet status Change notice Doc. number 74HC75_3 20041112 - Modifications: Product data sheet Supersedes 9397 750 13816 74HC_HCT75_CNV_2 • The format of this data sheet has been redesigned to comply with the current presentation and information standard of Philips Semiconductors. • • Removed type number 74HCT75. Inserted family specification. 74HC_HCT75_CNV_2 19970918 Product specification - - 74HC_HCT75_1 74HC_HCT75_1 Product specification - - - 19901201 9397 750 13816 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 18 of 20 74HC75 Philips Semiconductors Quad bistable transparant latch 15. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. Definitions 17. Disclaimers Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 18. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: [email protected] 9397 750 13816 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 19 of 20 74HC75 Philips Semiconductors Quad bistable transparant latch 19. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 5 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information . . . . . . . . . . . . . . . . . . . . 19 © Koninklijke Philips Electronics N.V. 2004 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 12 November 2004 Document number: 9397 750 13816 Published in The Netherlands