74HC4024 7-stage binary ripple counter Rev. 03 — 12 November 2004 Product data sheet 1. General description The 74HC4024 is a high-speed Si-gate CMOS device and is pin compatible with the 4024 of the 4000B series. The 74HC4024 is specified in compliance with JEDEC standard no. 7A. The 74HC4024 is a 7-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. 2. Features ■ Low-power dissipation ■ Complies with JEDEC standard no. 7A ■ ESD protection: ◆ HBM EIA/JESD22-A114-B exceeds 2000 V ◆ MM EIA/JESD22-A115-A exceeds 200 V. ■ Multiple package options ■ Specified from −40 °C to +80 °C and from −40 °C to +125 °C. 3. Applications ■ Frequency dividing circuits ■ Time delay circuits. 74HC4024 Philips Semiconductors 7-stage binary ripple counter 4. Quick reference data Table 1: Quick reference data GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. Symbol Parameter Conditions Min Typ Max Unit tPHL, tPLH propagation delay CP to Q0 CL = 15 pF; VCC = 5 V - 14 - ns fmax maximum clock frequency CL = 15 pF; VCC = 5 V - 90 - MHz CI input capacitance - 3.5 - pF - 25 - pF power dissipation capacitance CPD [1] VI = GND to VCC [1] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 5. Ordering information Table 2: Ordering information Type number Package Temperature range Name Description Version 74HC4024N −40 °C to +125 °C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 74HC4024D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74HC4024DB −40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 74HC4024PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 9397 750 13813 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 2 of 18 74HC4024 Philips Semiconductors 7-stage binary ripple counter 6. Functional diagram Q6 3 Q5 4 Q0 7-STAGE COUNTER Q4 5 1 Q1 CP Q3 6 Q2 Q3 Q2 9 2 Q1 11 Q4 MR Q5 Q0 12 Q6 12 11 9 6 5 4 3 001aab906 CP MR 1 2 001aab908 Fig 1. Functional diagram Fig 2. Logic symbol CTR7 12 0 1 11 + 9 6 CT 2 5 CT = 0 4 3 6 001aab907 Fig 3. IEC logic symbol Q CP T Q FF 1 T Q FF 2 Q T Q RD Q FF 3 T Q RD Q FF 4 T Q RD Q FF 5 T Q RD Q FF 6 T FF 7 Q RD Q RD RD MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 001aab909 Fig 4. Logic diagram 9397 750 13813 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 3 of 18 74HC4024 Philips Semiconductors 7-stage binary ripple counter 7. Pinning information 7.1 Pinning CP 1 14 VCC MR 2 13 n.c. Q6 3 12 Q0 Q5 4 Q4 5 Q3 6 GND 7 4024 11 Q1 10 n.c. 9 Q2 8 n.c. 001aab905 Fig 5. Pin configuration 7.2 Pin description Table 3: Pin description Symbol Pin Description CP 1 clock input (HIGH-to-LOW, edge-triggered) MR 2 master reset input (active HIGH) Q6 3 parallel output 6 Q5 4 parallel output 5 Q4 5 parallel output 4 Q3 6 parallel output 3 GND 7 ground (0 V) n.c. 8 not connected Q2 9 parallel output 2 n.c. 10 not connected Q1 11 parallel output 1 Q0 12 parallel output 0 n.c. 13 not connected VCC 14 positive supply voltage 9397 750 13813 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 4 of 18 74HC4024 Philips Semiconductors 7-stage binary ripple counter 8. Functional description 8.1 Function table Table 4: Function table [1] Input Output MR CP Qn H X L L ↑ no change ↓ count [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH clock transition; ↓ = HIGH-to-LOW clock transition. 9. Limiting values Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage Max Unit −0.5 +7 V IIK input diode current VI < −0.5 V or VI > VCC + 0.5 V - ±20 mA IOK output diode current VO < −0.5 V or VO > VCC + 0.5 V - ±20 mA IO output source or sink current VO = −0.5 V to VCC + 0.5 V - ±25 mA ICC, IGND VCC or GND current - ±50 mA Tstg storage temperature −65 +150 °C Ptot power dissipation DIP14 package [1] - 750 mW SO14, SSOP14 and TSSOP14 packages [2] - 500 mW [1] Above 70 °C: Ptot derates linearly with 12 mW/K. [2] Above 70 °C: Ptot derates linearly with 8 mW/K. 9397 750 13813 Product data sheet Min © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 5 of 18 74HC4024 Philips Semiconductors 7-stage binary ripple counter 10. Recommended operating conditions Table 6: Recommended operating conditions Symbol Parameter VCC Min Typ Max Unit supply voltage 2.0 5.0 6.0 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V tr, tf input rise and fall times VCC = 2.0 V except CP VCC = 4.5 V - - 1000 ns - 6.0 500 ns VCC = 6.0 V - - 400 ns −40 - +125 °C Tamb Conditions ambient temperature 11. Static characteristics Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit HIGH-level input voltage VCC = 2.0 V 1.5 1.2 - V VCC = 4.5 V 3.15 2.4 - V VCC = 6.0 V 4.2 3.2 - V VCC = 2.0 V - 0.8 0.5 V VCC = 4.5 V - 2.1 1.35 V VCC = 6.0 V - 2.8 1.8 V IO = −20 µA; VCC = 2.0 V 1.9 2.0 - V IO = −20 µA; VCC = 4.5 V 4.4 4.5 - V IO = −20 µA; VCC = 6.0 V 5.9 6.0 - V IO = −4 mA; VCC = 4.5 V 3.98 4.32 - V IO = −5.2 mA; VCC = 6.0 V 5.48 5.81 - V IO = 20 µA; VCC = 2.0 V - 0 0.1 V IO = 20 µA; VCC = 4.5 V - 0 0.1 V IO = 20 µA; VCC = 6.0 V - 0 0.1 V Tamb = 25 °C VIH VIL VOH VOL LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL IO = 4 mA; VCC = 4.5 V - 0.15 0.26 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 V ILI input leakage current VI = VCC or GND; VCC = 6.0 V - - ±0.1 µA ICC quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 µA CI input capacitance - 3.5 - pF VCC = 2.0 V 1.5 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V Tamb = −40 °C to +85 °C VIH HIGH-level input voltage 9397 750 13813 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 6 of 18 74HC4024 Philips Semiconductors 7-stage binary ripple counter Table 7: Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VIL LOW-level input voltage VCC = 2.0 V - - 0.5 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V IO = −20 µA; VCC = 2.0 V 1.9 - - V IO = −20 µA; VCC = 4.5 V 4.4 - - V IO = −20 µA; VCC = 6.0 V 5.9 - - V IO = −4 mA; VCC = 4.5 V 3.84 - - V IO = −5.2 mA; VCC = 6.0 V 5.34 - - V VOH VOL HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL IO = 20 µA; VCC = 2.0 V - - 0.1 V IO = 20 µA; VCC = 4.5 V - - 0.1 V IO = 20 µA; VCC = 6.0 V - - 0.1 V IO = 4 mA; VCC = 4.5 V - - 0.33 V IO = 5.2 mA; VCC = 6.0 V - - 0.33 V ILI input leakage current VI = VCC or GND; VCC = 6.0 V - - ±1.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 80 µA VCC = 2.0 V 1.5 - - V VCC = 4.5 V 3.15 - - V VCC = 6.0 V 4.2 - - V VCC = 2.0 V - - 0.5 V VCC = 4.5 V - - 1.35 V VCC = 6.0 V - - 1.8 V IO = −20 µA; VCC = 2.0 V 1.9 - - V IO = −20 µA; VCC = 4.5 V 4.4 - - V IO = −20 µA; VCC = 6.0 V 5.9 - - V IO = −4 mA; VCC = 4.5 V 3.7 - - V IO = −5.2 mA; VCC = 6.0 V 5.2 - - V IO = 20 µA; VCC = 2.0 V - - 0.1 V IO = 20 µA; VCC = 4.5 V - - 0.1 V IO = 20 µA; VCC = 6.0 V - - 0.1 V Tamb = −40 °C to +125 °C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL IO = 4 mA; VCC = 4.5 V - - 0.4 V IO = 5.2 mA; VCC = 6.0 V - - 0.4 V ILI input leakage current VI = VCC or GND; VCC = 6.0 V - - ±1.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 160 µA 9397 750 13813 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 7 of 18 74HC4024 Philips Semiconductors 7-stage binary ripple counter 12. Dynamic characteristics Table 8: Dynamic characteristics GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 7. Symbol Parameter Conditions Min Typ Max Unit VCC = 2.0 V - 47 175 ns VCC = 4.5 V - 17 35 ns VCC = 6.0 V - 14 30 ns VCC = 5.0 V; CL = 15 pF - 14 - ns VCC = 2.0 V - 25 80 ns VCC = 4.5 V - 9 16 ns VCC = 6.0 V - 7 14 ns VCC = 2.0 V - 63 200 ns VCC = 4.5 V - 23 40 ns VCC = 6.0 V - 18 34 ns VCC = 2.0 V - 19 75 ns VCC = 4.5 V - 7 15 ns VCC = 6.0 V - 6 13 ns VCC = 2.0 V 80 17 - ns VCC = 4.5 V 16 6 - ns VCC = 6.0 V 14 5 - ns VCC = 2.0 V 80 22 - ns VCC = 4.5 V 16 8 - ns VCC = 6.0 V 14 6 - ns VCC = 2.0 V 50 6 - ns VCC = 4.5 V 10 2 - ns VCC = 6.0 V 9 2 - ns VCC = 2.0 V 6.0 27 - MHz VCC = 4.5 V 30 82 - MHz Tamb = 25 °C tPHL, tPLH propagation delay CP to Q0 propagation delay Qn to Qn+1 tPHL tTHL, tTLH tW propagation delay MR to Q0 output transition time CP clock pulse width HIGH or LOW MR master reset pulse width HIGH trem fmax CPD removal time MR to CP maximum clock frequency power dissipation capacitance see Figure 6 see Figure 6 see Figure 6 see Figure 6 see Figure 6 see Figure 6 see Figure 6 see Figure 6 VCC = 6.0 V 35 98 - MHz VCC = 5.0 V; CL = 15 pF - 90 - MHz - 25 - pF VI = GND to VCC 9397 750 13813 Product data sheet [1] © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 8 of 18 74HC4024 Philips Semiconductors 7-stage binary ripple counter Table 8: Dynamic characteristics …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 7. Symbol Parameter Conditions Min Typ Max Unit Tamb = −40 °C to +85 °C tPHL, tPLH propagation delay CP to Q0 propagation delay Qn to Qn+1 tPHL tTHL, tTLH tW propagation delay MR to Q0 output transition time CP clock pulse width HIGH or LOW MR master reset pulse width HIGH trem fmax removal time MR to CP maximum clock frequency see Figure 6 VCC = 2.0 V - - 220 ns VCC = 4.5 V - - 44 ns VCC = 6.0 V - - 37 ns see Figure 6 VCC = 2.0 V - - 100 ns VCC = 4.5 V - - 20 ns VCC = 6.0 V - - 17 ns see Figure 6 VCC = 2.0 V - - 250 ns VCC = 4.5 V - - 50 ns VCC = 6.0 V - - 43 ns see Figure 6 VCC = 2.0 V - - 95 ns VCC = 4.5 V - - 19 ns VCC = 6.0 V - - 16 ns see Figure 6 VCC = 2.0 V 100 - - ns VCC = 4.5 V 20 - - ns VCC = 6.0 V 17 - - ns see Figure 6 VCC = 2.0 V 100 - - ns VCC = 4.5 V 20 - - ns VCC = 6.0 V 17 - - ns see Figure 6 VCC = 2.0 V 65 - - ns VCC = 4.5 V 13 - - ns VCC = 6.0 V 11 - - ns see Figure 6 VCC = 2.0 V 4.8 - - MHz VCC = 4.5 V 24 - - MHz VCC = 6.0 V 28 - - MHz 9397 750 13813 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 9 of 18 74HC4024 Philips Semiconductors 7-stage binary ripple counter Table 8: Dynamic characteristics …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 7. Symbol Parameter Conditions Min Typ Max Unit Tamb = −40 °C to +125 °C tPHL, tPLH propagation delay CP to Q0 propagation delay Qn to Qn+1 propagation delay MR to Q0 tPHL tTHL, tTLH output transition time CP clock pulse width HIGH or LOW tW MR master reset pulse width HIGH removal time MR to CP trem maximum clock frequency fmax [1] see Figure 6 VCC = 2.0 V - - 265 ns VCC = 4.5 V - - 53 ns VCC = 6.0 V - - 45 ns see Figure 6 VCC = 2.0 V - - 120 ns VCC = 4.5 V - - 24 ns VCC = 6.0 V - - 20 ns see Figure 6 VCC = 2.0 V - - 300 ns VCC = 4.5 V - - 60 ns VCC = 6.0 V - - 51 ns see Figure 6 VCC = 2.0 V - - 110 ns VCC = 4.5 V - - 22 ns VCC = 6.0 V - - 19 ns see Figure 6 VCC = 2.0 V 120 - - ns VCC = 4.5 V 24 - - ns VCC = 6.0 V 20 - - ns see Figure 6 VCC = 2.0 V 120 - - ns VCC = 4.5 V 24 - - ns VCC = 6.0 V 20 - - ns see Figure 6 VCC = 2.0 V 75 - - ns VCC = 4.5 V 15 - - ns VCC = 6.0 V 13 - - ns see Figure 6 VCC = 2.0 V 4.0 - - MHz VCC = 4.5 V 20 - - MHz VCC = 6.0 V 24 - - MHz CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 9397 750 13813 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 10 of 18 74HC4024 Philips Semiconductors 7-stage binary ripple counter 13. Waveforms MR input VM 1/fmax tW trem VM CP input tPHL tPLH tW tPHL Q0 or Qn output VM tTLH tTHL 001aab910 Also showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (CP) removal time. VM = 0.5 × VI. Fig 6. Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency VCC PULSE GENERATOR VI VO D.U.T. RT CL mna101 Test data is given in Table 9. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. Fig 7. Load circuitry for switching times Table 9: Test data Supply Input Load VCC VI tr, tf CL 2.0 V VCC 6 ns 50 pF 4.5 V VCC 6 ns 50 pF 6.0 V VCC 6 ns 50 pF 5.0 V VCC 6 ns 15 pF 9397 750 13813 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 11 of 18 74HC4024 Philips Semiconductors 7-stage binary ripple counter 14. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.2 inches 0.17 0.02 0.13 0.068 0.044 0.021 0.015 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT27-1 050G04 MO-001 SC-501-14 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Fig 8. Package outline SOT27-1 (DIP14) 9397 750 13813 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 12 of 18 74HC4024 Philips Semiconductors 7-stage binary ripple counter SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 9. Package outline SOT108-1 (SO14) 9397 750 13813 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 13 of 18 74HC4024 Philips Semiconductors 7-stage binary ripple counter SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.4 0.9 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC JEITA MO-150 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT337-1 (SSOP14) 9397 750 13813 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 14 of 18 74HC4024 Philips Semiconductors 7-stage binary ripple counter TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 11. Package outline SOT402-1 (TSSOP14) 9397 750 13813 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 15 of 18 74HC4024 Philips Semiconductors 7-stage binary ripple counter 15. Revision history Table 10: Revision history Document ID Release date 74HC4024_3 20041112 Product data sheet Modifications: Data sheet status Change notice Doc. number Supersedes - 9397 750 13813 74HC_HCT4024_CNV_2 • The format of this data sheet has been redesigned to comply with the current presentation and information standard of Philips Semiconductors. • • Removed type number 74HCT4024. Inserted family specification. 74HC_HCT4024_CNV_2 19970901 Product specification - - 74HC_HCT4024_1 74HC_HCT4024_1 - - 19901201 Product specification - 9397 750 13813 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 16 of 18 74HC4024 Philips Semiconductors 7-stage binary ripple counter 16. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 17. Definitions 18. Disclaimers Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 19. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: [email protected] 9397 750 13813 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 03 — 12 November 2004 17 of 18 74HC4024 Philips Semiconductors 7-stage binary ripple counter 20. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 9 10 11 12 13 14 15 16 17 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information . . . . . . . . . . . . . . . . . . . . 17 © Koninklijke Philips Electronics N.V. 2004 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 12 November 2004 Document number: 9397 750 13813 Published in The Netherlands