74LV4020 14-stage binary ripple counter Rev. 01 — 29 November 2005 Product data sheet 1. General description The 74LV4020 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC4020 and 74HCT4020. The 74LV4020 is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and 12 fully buffered parallel outputs (Q0, and Q3 to Q13). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. 2. Features ■ Optimized for low-voltage applications: 1.0 V to 5.5 V ■ Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V ■ Typical LOW-level output voltage (peak) or output ground bounce: VOL(p) < 0.8 V at VCC = 3.3 V and Tamb = 25 °C ■ Typical HIGH-level output voltage (valley) or output VOH undershoot: VOH(v) > 2 V at VCC = 3.3 V and Tamb = 25 °C ■ ESD protection: ◆ HBM EIA/JESD22-A114-C exceeds 2000 V ◆ MM EIA/JESD22-A115-A exceeds 200 V. ■ Multiple package options ■ Specified from −40 °C to +80 °C and from −40 °C to +125 °C. 3. Applications ■ Frequency dividing circuits ■ Time delay circuits ■ Control counters 74LV4020 Philips Semiconductors 14-stage binary ripple counter 4. Quick reference data Table 1: Quick reference data GND = 0 V; Tamb = 25 °C; tr = tf = 2.5 ns. Symbol Parameter Conditions Min Typ Max Unit tPHL, tPLH CL = 15 pF; VCC = 3.3 V CP to Q0 - 12 - ns Qn to Q(n+1) - 7 - ns - 16 - ns - 100 - MHz - 3.5 - pF - 20 - pF propagation delay propagation delay tPHL CL = 15 pF; VCC = 3.3 V MR to Qn fmax maximum input clock frequency Ci input capacitance power dissipation capacitance CPD [1] CL = 15 pF; VCC = 3.3 V [1] per gate; VI = GND to VCC CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 5. Ordering information Table 2: Ordering information Type number Package Temperature range Name Description 74LV4020N −40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74LV4020D −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74LV4020DB −40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74LV4020PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74LV4020_1 Product data sheet Version © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 29 November 2005 2 of 20 74LV4020 Philips Semiconductors 14-stage binary ripple counter 6. Functional diagram 10 CP T 14-STAGE COUNTER 11 MR CD 9 7 5 4 6 13 12 14 15 1 2 3 Q0 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 001aad722 Fig 1. Functional diagram CTR14 10 11 Q0 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 CP MR 9 7 5 4 6 13 12 14 15 1 2 3 10 11 0 + CT CT 13 001aad723 001aad724 Fig 2. Logic symbol CP FF T 0 Q FF T 1 Q Fig 3. IEC logic symbol FF T 2 Q Q Q FF T 3 Q RD RD 9 7 5 4 6 13 12 14 15 1 2 3 Q FF T 4 Q RD Q FF T 5 Q RD Q FF T 6 Q Q RD Q RD RD MR Q0 FF T 7 Q Q3 FF T 8 Q FF T 9 Q Q Q7 FF T 10 Q RD RD Q FF T 11 Q RD Q8 Q Q4 FF T 12 Q RD Q9 Q Q FF T 13 Q RD Q10 Q6 Q5 Q RD Q11 Q RD Q12 Q13 001aad725 Fig 4. Logic diagram 74LV4020_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 29 November 2005 3 of 20 74LV4020 Philips Semiconductors 14-stage binary ripple counter 7. Pinning information 7.1 Pinning Q11 1 16 VCC Q12 2 15 Q10 Q13 3 14 Q9 Q5 4 13 Q7 4020 Q4 5 12 Q8 Q6 6 11 MR Q3 7 10 CP GND 8 9 Q0 001aad721 Fig 5. Pin configuration DIP16, SO16, SSOP16 and TSSOP16 7.2 Pin description Table 3: Pin description Symbol Pin Description Q11 1 parallel output 11 Q12 2 parallel output 12 Q13 3 parallel output 13 Q5 4 parallel output 5 Q4 5 parallel output 4 Q6 6 parallel output 6 Q3 7 parallel output 3 GND 8 ground (0 V) Q0 9 parallel output 0 CP 10 clock input (HIGH-to-LOW, edge-triggered) MR 11 master reset input (active HIGH) Q8 12 parallel output 8 Q7 13 parallel output 7 Q9 14 parallel output 9 Q10 15 parallel output 10 VCC 16 supply voltage 74LV4020_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 29 November 2005 4 of 20 74LV4020 Philips Semiconductors 14-stage binary ripple counter 8. Functional description 8.1 Function table Function table [1] Table 4: Input Output CP MR Q0, Q3 to Q13 ↑ L no change ↓ L count X H L [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH clock transition; ↓ = HIGH-to-LOW clock transition. 8.1.1 Timing diagram 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384 CP input MR input Q0 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 001aad726 Fig 6. Timing diagram 74LV4020_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 29 November 2005 5 of 20 74LV4020 Philips Semiconductors 14-stage binary ripple counter 9. Limiting values Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage IIK input clamping current VI < −0.5 V or VI > VCC + 0.5 V −0.5 +7 V - ±20 mA IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V - ±50 mA IO output current ICC quiescent supply current VO = −0.5 V to VCC + 0.5 V - ±25 mA - 50 mA IGND ground current - −50 mA Tstg storage temperature −65 +150 °C Ptot total power dissipation Tamb = −40 °C to +125 °C DIP16 package [1] - 750 mW SO16 package [2] - 500 mW SSOP16 and TSSOP16 packages [3] - 400 mW [1] Above Tamb = 70 °C: Ptot derates linearly with 12 mW/K. [2] Above Tamb = 70 °C: Ptot derates linearly with 8 mW/K. [3] Above Tamb = 60 °C: Ptot derates linearly with 5.5 mW/K. 10. Recommended operating conditions Table 6: Recommended operating conditions Symbol Parameter Conditions VCC supply voltage [1] Typ Max Unit 1.0 3.3 5.5 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature −40 - +125 °C ∆t/∆V input transition rise and VCC = 1.0 V to 2.0 V fall rate VCC = 2.0 V to 2.7 V - - 500 ns/V - - 200 ns/V VCC = 2.7 V to 3.6 V - - 100 ns/V VCC = 3.6 V to 5.5 V - - 50 ns/V [1] The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to VCC = 1.0 V (with input levels GND or VCC). 74LV4020_1 Product data sheet Min © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 29 November 2005 6 of 20 74LV4020 Philips Semiconductors 14-stage binary ripple counter 11. Static characteristics Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +85 VIH VIL VOH VOL Conditions Min Typ Max Unit °C [1] HIGH-state input voltage LOW-state input voltage HIGH-state output voltage LOW-state output voltage VCC = 1.2 V 0.9 - - V VCC = 2.0 V 1.4 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 4.5 V to 5.5 V 0.7 × VCC - - V VCC = 1.2 V - - 0.3 V VCC = 2.0 V - - 0.6 V VCC = 2.7 V to 3.6 V - - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3 × VCC V IO = −100 µA; VCC = 1.2 V - 1.2 - V IO = −100 µA; VCC = 2.0 V 1.8 2.0 - V IO = −100 µA; VCC = 2.7 V 2.5 2.7 - V IO = −100 µA; VCC = 3.0 V 2.8 3.0 - V IO = −100 µA; VCC = 4.5 V 4.3 4.5 - V IO = −6 mA; VCC = 3.0 V 2.40 2.82 - V IO = −12 mA; VCC = 4.5 V 3.60 4.20 - V IO = 100 µA; VCC = 1.2 V - 0 - V IO = 100 µA; VCC = 2.0 V - 0 0.2 V IO = 100 µA; VCC = 2.7 V - 0 0.2 V IO = 100 µA; VCC = 3.0 V - 0 0.2 V IO = 100 µA; VCC = 4.5 V - 0 0.2 V IO = 6 mA; VCC = 3.0 V - 0.25 0.40 V IO = 12 mA; VCC = 4.5 V - 0.35 0.55 V VI = VIH or VIL VI = VIH or VIL ILI input leakage current VI = VCC or GND; VCC = 5.5 V - - 1.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 20.0 µA ∆ICC additional quiescent supply current per input; VI = VCC − 0.6 V; VCC = 2.7 V to 3.6 V - - 500 µA Ci input capacitance - 3.5 - pF VCC = 1.2 V 0.9 - - V VCC = 2.0 V 1.4 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 4.5 V to 5.5 V 0.7 × VCC - - V Tamb = −40 °C to +125 °C VIH HIGH-state input voltage 74LV4020_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 29 November 2005 7 of 20 74LV4020 Philips Semiconductors 14-stage binary ripple counter Table 7: Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VIL VCC = 1.2 V - - 0.3 V VCC = 2.0 V - - 0.6 V VCC = 2.7 V to 3.6 V - - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3 × VCC V IO = −100 µA; VCC = 1.2 V - - - V IO = −100 µA; VCC = 2.0 V 1.8 - - V IO = −100 µA; VCC = 2.7 V 2.5 - - V IO = −100 µA; VCC = 3.0 V 2.8 - - V IO = −100 µA; VCC = 4.5 V 4.3 - - V LOW-state input voltage VOH HIGH-state output voltage LOW-state output voltage VOL VI = VIH or VIL IO = −6 mA; VCC = 3.0 V 2.20 - - V IO = −12 mA; VCC = 4.5 V 3.50 - - V IO = 100 µA; VCC = 1.2 V - - - V IO = 100 µA; VCC = 2.0 V - - 0.2 V IO = 100 µA; VCC = 2.7 V - - 0.2 V IO = 100 µA; VCC = 3.0 V - - 0.2 V IO = 100 µA; VCC = 4.5 V - - 0.2 V IO = 6 mA; VCC = 3.0 V - - 0.50 V IO = 12 mA; VCC = 4.5 V - - 0.65 V VI = VIH or VIL ILI input leakage current VI = VCC or GND; VCC = 5.5 V - - 1.0 µA ICC quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 160 µA ∆ICC additional quiescent supply current per input; VI = VCC − 0.6 V; VCC = 2.7 V to 3.6 V - - 850 µA [1] All typical values are measured at Tamb = 25 °C. 74LV4020_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 29 November 2005 8 of 20 74LV4020 Philips Semiconductors 14-stage binary ripple counter 12. Dynamic characteristics Table 8: Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF; for test circuit see Figure 9. Symbol Parameter Tamb = −40 °C to +85 tPHL, tPLH Conditions CP to Q0 Max Unit VCC = 1.2 V - 60 - ns VCC = 2.0 V - 27 43 ns VCC = 2.7 V - 19 31 ns VCC = 3.0 V to 3.6 V - 16 26 ns VCC = 4.5 V to 5.5 V - 11 17 ns VCC = 3.3 V; CL = 15 pF - 12 - ns VCC = 1.2 V - 40 - ns VCC = 2.0 V - 18 29 ns VCC = 2.7 V - 13 21 ns VCC = 3.0 V to 3.6 V - 11 18 ns VCC = 4.5 V to 5.5 V - 7 12 ns VCC = 3.3 V; CL = 15 pF - 7 - ns VCC = 1.2 V - 55 - ns VCC = 2.0 V - 27 44 ns VCC = 2.7 V - 19 31 ns VCC = 3.0 V to 3.6 V - 16 26 ns VCC = 4.5 V to 5.5 V - 11 17 ns VCC = 3.3 V; CL = 15 pF - 16 - ns VCC = 2.0 V 35 7 - ns VCC = 2.7 V 25 5 - ns VCC = 3.0 V to 3.6 V 20 4 - ns VCC = 4.5 V to 5.5 V 15 3 - ns VCC = 2.0 V 35 11 - ns VCC = 2.7 V 25 9 - ns VCC = 3.0 V to 3.6 V 20 8 - ns VCC = 4.5 V to 5.5 V 15 7 - ns see Figure 7 see Figure 7 propagation delay MR to Qn tW Typ propagation delay Qn to Q(n+1) tPHL Min °C [1] see Figure 8 pulse width CP (HIGH and LOW) MR (HIGH) see Figure 7 see Figure 8 74LV4020_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 29 November 2005 9 of 20 74LV4020 Philips Semiconductors 14-stage binary ripple counter Table 8: Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF; for test circuit see Figure 9. Symbol Parameter trec Typ Max Unit maximum input clock frequency see Figure 8 VCC = 1.2 V - 10 - ns VCC = 2.0 V 22 5 - ns VCC = 2.7 V 16 4 - ns VCC = 3.0 V to 3.6 V 13 3 - ns VCC = 4.5 V to 5.5 V 10 2 - ns VCC = 2.0 V 14 60 - MHz VCC = 2.7 V 19 76 - MHz VCC = 3.0 V to 3.6 V 24 94 - MHz VCC = 4.5 V to 5.5 V 36 112 - MHz - 100 - MHz - 20 - pF VCC = 1.2 V - - - ns VCC = 2.0 V - - 54 ns VCC = 2.7 V - - 38 ns VCC = 3.0 V to 3.6 V - - 32 ns VCC = 4.5 V to 5.5 V - - 22 ns VCC = 1.2 V - - - ns VCC = 2.0 V - - 37 ns VCC = 2.7 V - - 26 ns VCC = 3.0 V to 3.6 V - - 22 ns VCC = 4.5 V to 5.5 V - - 15 ns see Figure 7 VCC = 3.3 V; CL = 15 pF CPD Min recovery time MR to CP fmax Conditions power dissipation capacitance per gate; VI = GND to VCC [2] Tamb = −40 °C to +125 °C tPHL, tPLH propagation delay CP to Q0 Qn to Q(n+1) tPHL see Figure 7 see Figure 7 propagation delay MR to Qn see Figure 8 VCC = 1.2 V - - - ns VCC = 2.0 V - - 55 ns VCC = 2.7 V - - 39 ns VCC = 3.0 V to 3.6 V - - 32 ns VCC = 4.5 V to 5.5 V - - 22 ns 74LV4020_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 29 November 2005 10 of 20 74LV4020 Philips Semiconductors 14-stage binary ripple counter Table 8: Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF; for test circuit see Figure 9. Symbol Parameter tW Conditions Min Typ Max Unit pulse width CP (HIGH and LOW) MR (HIGH) see Figure 7 VCC = 2.0 V 41 - - ns VCC = 2.7 V 30 - - ns VCC = 3.0 V to 3.6 V 24 - - ns VCC = 4.5 V to 5.5 V 18 - - ns VCC = 2.0 V 41 - - ns VCC = 2.7 V 30 - - ns VCC = 3.0 V to 3.6 V 24 - - ns VCC = 4.5 V to 5.5 V 18 - - ns VCC = 1.2 V - - - ns VCC = 2.0 V 26 - - ns VCC = 2.7 V 19 - - ns VCC = 3.0 V to 3.6 V 15 - - ns VCC = 4.5 V to 5.5 V 12 - - ns VCC = 2.0 V 12 - - MHz VCC = 2.7 V 16 - - MHz VCC = 3.0 V to 3.6 V 20 - - MHz VCC = 4.5 V to 5.5 V 30 - - MHz see Figure 8 recovery time trec MR to CP maximum input clock frequency fmax see Figure 8 see Figure 7 [1] Typical values are measured at nominal VCC and Tamb = 25 °C. [2] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. 74LV4020_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 29 November 2005 11 of 20 74LV4020 Philips Semiconductors 14-stage binary ripple counter 13. Waveforms 1/fmax VI input CP, Qn VM GND tW t PHL t PLH VOH VM output Q0, Q(n+1) VOL 001aad727 Measurement points: VM = 0.5 × VCC. VOL and VOH are typical output voltage drop that occur with the output load. Fig 7. Propagation delay clock (CP) to output (Qn), clock pulse width and maximum clock frequency VI VM MR input GND tW t rec VI CP input VM GND t PHL VOH VM Qn output VOL 001aad728 Measurement points: VM = 0.5 × VCC. VOL and VOH are typical output voltage drop that occur with the output load. Fig 8. Propagation delay master reset (MR) to output (Qn), pulse width master reset (MR) and removal time master reset (MR) to clock (CP) 74LV4020_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 29 November 2005 12 of 20 74LV4020 Philips Semiconductors 14-stage binary ripple counter VCC PULSE GENERATOR VI VO D.U.T. CL 50 pF RT RL 1 kΩ 001aaa663 Test data is given in Table 9. Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 9. Load circuitry for switching times Table 9: Test data Supply voltage Input Load VCC VI tr, tf CL RL 1.2 V VCC ≤ 2.5 ns 50 pF 1 kΩ tPHL, tPLH 2.0 V VCC ≤ 2.5 ns 50 pF 1 kΩ tPHL, tPLH 2.7 V 2.7 V ≤ 2.5 ns 50 pF 1 kΩ tPHL, tPLH 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF, 15 pF 1 kΩ tPHL, tPLH 4.5 V to 5.5 V VCC ≤ 2.5 ns 50 pF 1 kΩ tPHL, tPLH 74LV4020_1 Product data sheet Test © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 29 November 2005 13 of 20 74LV4020 Philips Semiconductors 14-stage binary ripple counter 14. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 10. Package outline SOT38-1 (DIP16) 74LV4020_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 29 November 2005 14 of 20 74LV4020 Philips Semiconductors 14-stage binary ripple counter SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT109-1 (SO16) 74LV4020_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 29 November 2005 15 of 20 74LV4020 Philips Semiconductors 14-stage binary ripple counter SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC JEITA MO-150 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SOT338-1 (SSOP16) 74LV4020_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 29 November 2005 16 of 20 74LV4020 Philips Semiconductors 14-stage binary ripple counter TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 13. Package outline SOT403-1 (TSSOP16) 74LV4020_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 29 November 2005 17 of 20 74LV4020 Philips Semiconductors 14-stage binary ripple counter 15. Abbreviations Table 10: Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor TTL Transistor Transistor Logic HBM Human Body Model ESD ElectroStatic Discharge MM Machine Model 16. Revision history Table 11: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes 74LV4020_1 20051129 Product data sheet - - - 74LV4020_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 29 November 2005 18 of 20 74LV4020 Philips Semiconductors 14-stage binary ripple counter 17. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 18. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 20. Trademarks 19. Disclaimers Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 21. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: [email protected] 74LV4020_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 29 November 2005 19 of 20 74LV4020 Philips Semiconductors 14-stage binary ripple counter 22. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.1.1 9 10 11 12 13 14 15 16 17 18 19 20 21 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information . . . . . . . . . . . . . . . . . . . . 19 © Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 29 November 2005 Document number: 74LV4020_1 Published in The Netherlands