74CBTLVD3861 10-bit level-shifting bus switch with output enable Rev. 4 — 14 December 2011 Product data sheet 1. General description The 74CBTLVD3861 is a 10-bit 3.3 V to 1.8 V level translating bus switch with one output enable (OE) input. When OE is LOW, the switch is closed and port A is connected to the B port. When OE is HIGH, the switch is disabled. To ensure the high-impedance OFF-state during power-up or power-down, OE should be tied to the VCC through a pull-up resistor. The minimum value of the resistor is determined by the current-sinking capability of the driver. Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 3.0 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. 2. Features and benefits Supply voltage range from 3.0 V to 3.6 V High noise immunity Complies with JEDEC standard: JESD8-B/JESD36 (3.0 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V CDM AEC-Q100-011 revision B exceeds 1000 V 4 switch connection between two ports 3.3 V to 1.8 V level translation CMOS low power consumption Latch-up performance exceeds 250 mA per JESD78B Class I level A IOFF circuitry provides partial Power-down mode operation Multiple package options Specified from 40 C to +85 C and 40 C to +125 C 74CBTLVD3861 NXP Semiconductors 10-bit level-shifting bus switch with output enable 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74CBTLVD3861DK Name 40 C to +125 C SSOP24[1] 74CBTLVD3861PW 40 C to +125 C TSSOP24 74CBTLVD3861BQ [1] Description Version plastic shrink small outline package; 24 leads; body width 3.9 mm; lead pitch 0.635 mm SOT556-1 plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1 40 C to +125 C DHVQFN24 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 5.5 0.85 mm SOT815-1 Also known as QSOP24 package 4. Functional diagram OE A1 A2 A3 A4 A5 A6 A7 A8 2 3 4 5 6 7 8 9 A9 10 A10 11 22 21 20 19 18 17 16 15 14 13 23 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 001aan142 Fig 1. Logic symbol A1 A10 OE Fig 2. 2 22 11 13 B1 B10 23 001aam471 Logic diagram 74CBTLVD3861 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 2 of 19 74CBTLVD3861 NXP Semiconductors 10-bit level-shifting bus switch with output enable 5. Pinning information 5.1 Pinning 74CBTLVD3861 74CBTLVD3861 n.c. 1 24 VCC n.c. 1 24 VCC A1 2 23 OE A1 2 23 OE A2 3 22 B1 A2 3 22 B1 A3 4 21 B2 A3 4 21 B2 A4 5 20 B3 A4 5 20 B3 A5 6 19 B4 A5 6 19 B4 A6 7 18 B5 A6 7 18 B5 A7 8 17 B6 A7 8 17 B6 A8 9 16 B7 A8 9 16 B7 A9 10 15 B8 A9 10 15 B8 A10 11 14 B9 A10 11 14 B9 GND 12 13 B10 GND 12 13 B10 001aan152 Fig 3. 001aan153 Pin configuration for TSSOP24 (SOT355-1) Fig 4. Pin configuration for SSOP24 (SOT556-1) n.c. 24 VCC 74CBTLVD3861 1 terminal 1 index area A1 2 23 OE A2 3 22 B1 A3 4 21 B2 A4 5 20 B2 A5 6 19 B4 A6 7 18 B5 A7 8 17 B6 A8 9 16 B7 A9 10 15 B8 GND(1) B10 13 14 B9 GND 12 A10 11 001aan154 Transparent top view (1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad however if it is soldered the solder land should remain floating or be connected to GND. Fig 5. Pin configuration for DHVQFN24 (SOT815-1) 74CBTLVD3861 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 3 of 19 74CBTLVD3861 NXP Semiconductors 10-bit level-shifting bus switch with output enable 5.2 Pin description Table 2. Pin description Symbol Pin Description nc 1 not connected A1 to A10 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 data input/output (A port) GND 12 ground (0 V) B1 to B10 22, 21, 20, 19, 18, 17, 16, 15, 14, 13 data input/output (B port) OE 23 output enable input (active LOW) VCC 24 positive supply voltage 6. Functional description Table 3. Function selection[1] Input Input/output OE An, Bn L An = Bn H Z [1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Min Max Unit VCC supply voltage VI input voltage [1] 0.5 +4.6 V 0.5 +4.6 VSW switch voltage enable and disable mode [1] V 0.5 VCC + 0.5 V IIK input clamping current VI < 0.5 V 50 - mA ISK switch clamping current ISW switch current VI < 0.5 V 50 - mA VSW = 0 V to VCC - 128 mA ICC supply current - +100 mA IGND ground current 100 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation - 500 mW [1] [2] Conditions Tamb = 40 C to +125 C [2] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. For SSOP24 and TSSOP24 packages: Ptot derates linearly with 5.5 mW/K above 60 C. For DHVQFN24 package: Ptot derates linearly at 4.5 mW/K above 60 C. 74CBTLVD3861 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 4 of 19 74CBTLVD3861 NXP Semiconductors 10-bit level-shifting bus switch with output enable 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC Min Max Unit supply voltage 3.0 3.6 V VI input voltage 0 3.6 V VSW switch voltage 0 VCC V Tamb ambient temperature 40 +125 C - 200 ns/V t/V [1] Conditions enable and disable mode input transition rise and fall rate [1] VCC = 3.0 V to 3.6 V Applies to control signal levels. 9. Static characteristics Table 6. Static characteristics At recommended operating conditions voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit Conditions Min Typ[1] Max Min Max VIH HIGH-level input voltage VCC = 3.0 V to 3.6 V 2.0 - - 2.0 - V VIL LOW-level input voltage VCC = 3.0 V to 3.6 V - - 0.9 - 0.9 V II input leakage current pin OE; VI = GND to VCC; VCC = 3.6 V - - 1 - 20 A Vpass pass voltage VI = VCC; see Figure 8 to Figure 12 - - - - - V IS(OFF) OFF-state VCC = 3.6 V; see Figure 6 leakage current - - 1 - 20 A IS(ON) ON-state VCC = 3.6 V; see Figure 7 leakage current - - 1 - 20 A IOFF power-off VI or VO = 0 V to 3.6 V; leakage current VCC = 0 V - - 10 - 50 A ICC supply current VI = VCC; IO = 0 A; VCC = 3.6 V; VSW = GND or VCC - - 20 - 50 A VI = GND; IO = 0 A; VCC = 3.6 V; VSW = GND or VCC - - 100 - 150 A - - 300 - 2000 A ICC additional supply current pin OE; VI = VCC 0.6 V; VSW = GND or VCC; VCC = 3.6 V CI input capacitance pin OE; VCC = 3.3 V; VI = 0 V to 3.3 V - 0.9 - - - pF CS(OFF) OFF-state capacitance VCC = 3.3 V; VI = 0 V to 3.3 V - 2.5 - - - pF CS(ON) ON-state capacitance VCC = 3.3 V; VI = 0 V to 3.3 V - 9.0 - - - pF [1] All typical values are measured at Tamb = 25 C. [2] One input at 3 V, other inputs at VCC or GND. 74CBTLVD3861 Product data sheet [2] All information provided in this document is subject to legal disclaimers. Rev. 4 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 5 of 19 74CBTLVD3861 NXP Semiconductors 10-bit level-shifting bus switch with output enable 9.1 Test circuits VCC VCC OE VIH A Bn An Is Is A A GND VI OE VIL Is VO An Bn GND VI 001aan147 001aan148 VI = VCC or GND and VO = GND or VCC. Fig 6. VO VI = VCC or GND and VO = open circuit. Test circuit for measuring OFF-state leakage current (one switch) Fig 7. Test circuit for measuring ON-state leakage current (one switch) 9.2 Typical pass voltage graphs 001aam102 1.90 Vpass (V) 1.85 20 μA 1.90 Vpass (V) 1.85 1.80 100 μA 1.80 001aam103 20 μA 100 μA 1.75 1.75 1.70 1.70 2 mA 1.65 4 mA 2 mA 1.65 4 mA 1.60 1.55 3.0 3.2 1.60 3.4 3.6 1.55 3.0 VCC (V) Fig 8. Product data sheet 3.4 3.6 VCC (V) Pass voltage versus supply voltage; Tamb = 125 C (typical) 74CBTLVD3861 3.2 Fig 9. Pass voltage versus supply voltage; Tamb = 85 C (typical) All information provided in this document is subject to legal disclaimers. Rev. 4 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 6 of 19 74CBTLVD3861 NXP Semiconductors 10-bit level-shifting bus switch with output enable 001aam104 1.90 Vpass (V) 1.85 20 μA 1.90 Vpass (V) 1.85 1.80 100 μA 1.80 001aam105 20 μA 100 μA 1.75 1.75 1.70 1.70 2 mA 2 mA 4 mA 1.65 1.65 1.60 1.55 3.0 4 mA 1.60 3.2 3.4 1.55 3.0 3.6 3.2 VCC (V) 3.4 3.6 VCC (V) Fig 10. Pass voltage versus supply voltage; Tamb = 25 C (typical) Fig 11. Pass voltage versus supply voltage; Tamb = 0 C (typical) 001aam106 1.90 Vpass (V) 1.85 1.80 20 μA 1.75 100 μA 1.70 1.65 2 mA 4 mA 1.60 1.55 3.0 3.2 3.4 3.6 VCC (V) Fig 12. Pass voltage versus supply voltage; Tamb = 40 C (typical) 74CBTLVD3861 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 7 of 19 74CBTLVD3861 NXP Semiconductors 10-bit level-shifting bus switch with output enable 9.3 ON resistance Table 7. Resistance RON At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13. Symbol Parameter RON Tamb = 40 C to +85 C Conditions Tamb = 40 C to +125 C Unit Min Typ[1] Max Min Max ISW = 64 mA; VI = 0 V - 3.7 7.0 - 10.0 ISW = 24 mA; VI = 0 V - 3.7 7.0 - 10.0 ISW = 15 mA; VI = 1.2 V - 4.7 10.0 - 12.0 [2] ON resistance VCC = 3.0 V to 3.6 V [1] Typical values are measured at Tamb = 25 C and nominal VCC. [2] Measured by the voltage drop between the An and Bn terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (An or Bn) terminals. 9.4 ON resistance test circuit VSW V VCC OE VIL An VI Bn GND ISW 001aan149 RON = VSW / ISW. Fig 13. Test circuit for measuring ON resistance (one switch) 74CBTLVD3861 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 8 of 19 74CBTLVD3861 NXP Semiconductors 10-bit level-shifting bus switch with output enable 10. Dynamic characteristics Table 8. Dynamic characteristics GND = 0 V; for test circuit see Figure 16 Symbol Parameter Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit Conditions VCC = 3.0 V to 3.6 V enable time ten disable time Max Min Max - - 0.11 - 0.22 ns 1.5 2.9 5.0 1.5 6.0 ns 0.8 3.3 7.0 0.8 8.0 ns [4] OE to An or Bn; see Figure 15 VCC = 3.0 V to 3.6 V tdis Typ[1] [2][3] propagation delay An to Bn or Bn to An; see Figure 14 tpd Min [5] OE to An or Bn; see Figure 15 VCC = 3.0 V to 3.6 V [1] All typical values are measured at Tamb = 25 C and at nominal VCC. [2] The propagation delay is the calculated RC time constant of the on-state resistance of the switch and the load capacitance, when driven by an ideal voltage source (zero output impedance). [3] tpd is the same as tPLH and tPHL. [4] ten is the same as tPZH and tPZL. [5] tdis is the same as tPHZ and tPLZ. 10.1 Waveforms VI input VM VM 0V tPHL tPLH VOH output VM VM VOL 001aai367 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 14. The data input (An, Bn) to output (Bn, An) propagation delay times Table 9. Measurement points Supply voltage Input VCC VM VI tr = tf VM VX VY 3.0 V to 3.6 V 0.5VCC VCC 2.0 ns 0.9 V VOL + 0.15 V VOH 0.15 V 74CBTLVD3861 Product data sheet Output All information provided in this document is subject to legal disclaimers. Rev. 4 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 9 of 19 74CBTLVD3861 NXP Semiconductors 10-bit level-shifting bus switch with output enable VI OE input VM VM GND tPZL tPLZ 1.8 V output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ VOH tPZH VY output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs disabled outputs enabled 001aan155 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 15. Enable and disable times 74CBTLVD3861 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 10 of 19 74CBTLVD3861 NXP Semiconductors 10-bit level-shifting bus switch with output enable VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC VI RL VO G DUT RT RL CL 001aae331 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 16. Test circuit for measuring switching times Table 10. Test data Supply voltage Load VCC CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 3.0 V to 3.6 V 30 pF 1 k open GND 3.6 V 74CBTLVD3861 Product data sheet VEXT All information provided in this document is subject to legal disclaimers. Rev. 4 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 11 of 19 74CBTLVD3861 NXP Semiconductors 10-bit level-shifting bus switch with output enable 10.2 Additional dynamic characteristics Table 11. Additional dynamic characteristics GND = 0 V. Symbol Parameter f(3dB) [1] 3 dB frequency response Tamb = 25 C Conditions VCC = 3.3 V; RL = 50 ; see Figure 17 Unit Min Typ Max - 575 - [1] MHz fi is biased at 0.5VCC. 10.3 Test circuit VCC 0.5VCC OE VIL RL Bn fi An GND dB 001aan156 Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads 3 dB. Fig 17. Test circuit for measuring the frequency response when channel is in ON-state 74CBTLVD3861 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 12 of 19 74CBTLVD3861 NXP Semiconductors 10-bit level-shifting bus switch with output enable 11. Package outline SSOP24: plastic shrink small outline package; 24 leads; body width 3.9 mm; lead pitch 0.635 mm D E SOT556-1 A X c y HE v M A Z 13 24 A2 A (A 3) A1 θ Lp L 12 1 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.73 0.25 0.10 1.55 1.40 0.25 0.31 0.20 0.25 0.18 8.8 8.6 4.0 3.8 0.635 6.2 5.8 1 0.89 0.41 0.25 0.18 0.1 1.05 0.66 8o o 0 inches 0.068 0.0098 0.061 0.0040 0.055 0.01 0.012 0.0098 0.344 0.157 0.244 0.035 0.025 0.041 0.008 0.0075 0.337 0.150 0.228 0.016 0.01 0.007 0.004 0.040 0.026 8o o 0 Note 1. Plastic or metal protrusions of 0.2 mm (0.008 inch) maximum per side are not included. OUTLINE VERSION SOT556-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-137 Fig 18. Package outline SOT556-1 (SSOP24) 74CBTLVD3861 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 13 of 19 74CBTLVD3861 NXP Semiconductors 10-bit level-shifting bus switch with output enable TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm D SOT355-1 E A X c HE y v M A Z 13 24 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 12 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 7.9 7.7 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT355-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 19. Package outline SOT355-1 (TSSOP24) 74CBTLVD3861 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 14 of 19 74CBTLVD3861 NXP Semiconductors 10-bit level-shifting bus switch with output enable DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm B D SOT815-1 A A E A1 c detail X terminal 1 index area C e1 terminal 1 index area e y1 C v M C A B w M C b 2 y 11 L 12 1 e2 Eh 24 13 23 14 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 e2 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 5.6 5.4 4.25 3.95 3.6 3.4 2.25 1.95 0.5 4.5 1.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT815-1 --- --- --- EUROPEAN PROJECTION ISSUE DATE 03-04-29 Fig 20. Package outline SOT815-1 (DHVQFN24) 74CBTLVD3861 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 15 of 19 74CBTLVD3861 NXP Semiconductors 10-bit level-shifting bus switch with output enable 12. Abbreviations Table 12. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model 13. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes 74CBTLVD3861 v.4 20111214 Product data sheet - 74CBTLVD3861 v.3 Modifications: • Legal pages updated. 74CBTLVD3861 v.3 20111020 Product data sheet - 74CBTLVD3861 v.2 74CBTLVD3861 v.2 20110117 Product data sheet - 74CBTLVD3861 v.1 74CBTLVD3861 v.1 20101206 Product data sheet - - 74CBTLVD3861 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 16 of 19 74CBTLVD3861 NXP Semiconductors 10-bit level-shifting bus switch with output enable 14. Legal information 14.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. 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Export might require a prior authorization from competent authorities. 74CBTLVD3861 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 17 of 19 74CBTLVD3861 NXP Semiconductors 10-bit level-shifting bus switch with output enable Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 15. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74CBTLVD3861 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 14 December 2011 © NXP B.V. 2011. All rights reserved. 18 of 19 74CBTLVD3861 NXP Semiconductors 10-bit level-shifting bus switch with output enable 16. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 9.1 9.2 9.3 9.4 10 10.1 10.2 10.3 11 12 13 14 14.1 14.2 14.3 14.4 15 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Typical pass voltage graphs . . . . . . . . . . . . . . . 6 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ON resistance test circuit . . . . . . . . . . . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Additional dynamic characteristics . . . . . . . . . 12 Test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 14 December 2011 Document identifier: 74CBTLVD3861