74LVCV2G66
Overvoltage tolerant bilateral switch
Rev. 3 — 16 June 2010
Product data sheet
1. General description
The 74LVCV2G66 is a low-power, low-voltage, high-speed Si-gate CMOS device.
The 74LVCV2G66 provides two single pole single throw analog or digital switches. Each
switch includes an overvoltage tolerant input/output terminal (pin nZ), an output/input
terminal (pin nY) and low-power active HIGH enable input (pin nE).
The overvoltage tolerant switch terminals allow the switching of signals in excess of VCC.
The low-power enable input eliminates the necessity of using current limiting resistors in
portable applications when using control logic signals much lower than VCC. These inputs
are also overvoltage tolerant.
2. Features and benefits
Wide supply voltage range from 2.3 V to 5.5 V
Ultra low-power operation
Very low ON resistance:
8.0 Ω (typical) at VCC = 2.7 V
7.5 Ω (typical) at VCC = 3.3 V
7.3 Ω (typical) at VCC = 5.0 V.
5 V tolerant input for interfacing with 5 V logic
High noise immunity
Switch handling capability of 32 mA
CMOS low-power consumption
Latch-up performance exceeds 250 mA
Incorporates overvoltage tolerant analog switch technology
Switch accepts voltages up to 5.5 V independent of VCC
Multiple package options
Specified from −40 °C to +85 °C and −40 °C to +125 °C
74LVCV2G66
NXP Semiconductors
Overvoltage tolerant bilateral switch
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74LVCV2G66DP −40 °C to +125 °C
TSSOP8
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
SOT505-2
74LVCV2G66DC −40 °C to +125 °C
VSSOP8
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
74LVCV2G66GD −40 °C to +125 °C
XSON8U
plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 × 2 × 0.5 mm
SOT996-2
4. Marking
Table 2.
Marking codes
Type number
Marking code[1]
74LVCV2G66DP
Y66
74LVCV2G66DC
Y66
74LVCV2G66GD
Y66
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1Y
1Z
1
1E
7 #
2Z
2Y
5
3 #
2E
1
1
2
X1
1
1
6
X1
001aaa530
001aaa531
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Z
Y
E
VCC
001aaa532
Fig 3. Logic diagram (one switch)
74LVCV2G66
Product data sheet
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Rev. 3 — 16 June 2010
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74LVCV2G66
NXP Semiconductors
Overvoltage tolerant bilateral switch
6. Pinning information
6.1 Pinning
74LVCV2G66
1Z
1
8
VCC
1Y
2
7
1E
2E
3
6
2Y
GND
4
5
2Z
74LVCV2G66
1Z
1
8
VCC
1Y
2
7
1E
2E
3
6
2Y
GND
4
5
2Z
001aai214
Transparent top view
001aai213
Fig 4.
Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8)
Fig 5.
Pin configuration SOT996-2 (XSON8U)
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
1Y, 2Y
2, 6
independent input or output
1Z, 2Z
1, 5
independent input or output (overvoltage tolerance)
GND
4
ground (0 V)
1E, 2E
7, 3
enable input (active HIGH)
VCC
8
supply voltage
7. Functional description
Table 4:
Function table[1]
Input nE
Switch
L
OFF-state
H
ON-state
[1]
H = HIGH voltage level; L = LOW voltage level.
74LVCV2G66
Product data sheet
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Rev. 3 — 16 June 2010
© NXP B.V. 2010. All rights reserved.
3 of 23
74LVCV2G66
NXP Semiconductors
Overvoltage tolerant bilateral switch
8. Limiting values
Table 5:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
VI
input voltage
IIK
input clamping current
ISK
Min
Max
Unit
−0.5
+6.5
V
−0.5
+6.5
V
VI < −0.5 V or VI > 6.5 V
−50
-
mA
switch clamping current
VI < −0.5 V or VI > 6.5 V
-
±50
mA
VSW
switch voltage
enable and disable mode
−0.5
+6.5
V
ISW
switch current
VSW > −0.5 V or VSW < 6.5 V
-
±50
mA
ICC
supply current
-
100
mA
IGND
ground current
−100
-
mA
Tstg
storage temperature
−65
+150
°C
Ptot
total power dissipation
-
250
mW
Max
Unit
[1]
[2]
Conditions
[1]
Tamb = −40 °C to +125 °C
[2]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K.
For XSON8U package: above 118 °C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6:
Recommended operating conditions
Symbol
Parameter
VCC
supply voltage
2.3
-
5.5
V
VI
input voltage
0
-
5.5
V
VSW
switch voltage
0
-
5.5
V
Tamb
ambient temperature
Δt/ΔV
Conditions
input transition rise and fall rate
Min
Typ
enable and disable mode
[1]
−40
-
+125
°C
VCC = 2.3 V to 2.7 V
[2]
-
-
20
ns/V
VCC = 2.7 V to 5.5 V
[2]
-
-
10
ns/V
[1]
To avoid sinking GND current from terminal nZ when switch current flows in terminal nY, the voltage drop across the bidirectional switch
must not exceed 0.4 V. If the switch current flows into terminal nZ, no GND current will flow from terminal nY. In this case, there is no
limit for the voltage drop across the switch.
[2]
Applies to control signal levels.
74LVCV2G66
Product data sheet
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Rev. 3 — 16 June 2010
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74LVCV2G66
NXP Semiconductors
Overvoltage tolerant bilateral switch
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VIH
−40 °C to +85 °C
Conditions
Min
Max
Min
Max
HIGH-level
VCC = 2.3 V to 2.7 V
input voltage V = 3.0 V to 3.6 V
CC
0.6VCC
-
-
0.6VCC
-
V
2.0
-
-
2.0
-
V
VCC = 4.5 V to 5.5 V
0.55VCC
-
-
0.55VCC
-
V
-
-
0.1VCC
-
0.1VCC
V
-
-
0.5
-
0.5
V
LOW-level
VCC = 2.3 V to 2.7 V
input voltage V = 3.0 V to 3.6 V
CC
VIL
−40 °C to +125 °C Unit
Typ[1]
VCC = 4.5 V to 5.5 V
-
-
0.15VCC
-
[2]
0.15VCC V
-
±0.1
±5
-
±5
μA
II
input leakage pin nE; VI = 5.5 V or GND;
current
VCC = 0 V to 5.5 V
IS(OFF)
OFF-state
leakage
current
VCC = 2.3 V to 5.5 V; see Figure 6
[2][3]
-
±0.1
±10
-
±10
μA
IS(ON)
ON-state
leakage
current
VCC = 2.3 V to 5.5 V; see Figure 7
[2][3]
-
±0.1
±10
-
±10
μA
ICC
supply
current
VI = 5.5 V or GND;
VSW = GND or VCC;
VCC = 2.3 V to 5.5 V
[2]
-
0.1
10
-
40
μA
ΔICC
additional
supply
current
pin nE; VI = VCC − 0.6 V;
VSW = GND or VCC;
VCC = 3.0 V to 5.5 V
[2]
-
0.1
5
-
50
μA
CI
input
capacitance
-
2.5
-
-
-
pF
CS(OFF)
OFF-state
capacitance
-
8.0
-
-
-
pF
CS(ON)
ON-state
capacitance
-
16
-
-
-
pF
[1]
All typical values are measured at Tamb = 25 °C.
[2]
These typical values are measured at VCC = 3.3 V.
[3]
For overvoltage signals (VSW > VCC) the condition VY < VZ must be observed.
74LVCV2G66
Product data sheet
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Rev. 3 — 16 June 2010
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74LVCV2G66
NXP Semiconductors
Overvoltage tolerant bilateral switch
10.1 Test circuits
VCC
VCC
nE
VIL
nZ
VI
nE
VIH
nY
IS
GND
IS
VO
nZ
nY
GND
VI
001aag488
VO
001aag489
VI = GND and VO = GND or 5.5 V.
VI = 5.5 V or GND and VO = open circuit.
Fig 6. Test circuit for measuring OFF-state leakage
current
Fig 7. Test circuit for measuring ON-state leakage
current
10.2 ON resistance
Table 8.
Resistance RON
At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 9 and Figure 10.
Symbol
RON(peak)
RON(rail)
Parameter
ON resistance
(peak)
ON resistance (rail)
−40 °C to +85 °C
Conditions
−40 °C to +125 °C Unit
Min
Typ[1]
Max
Min
Max
ISW = 8 mA; VCC = 2.3 V to 2.7 V
-
13
30
-
30
Ω
ISW = 12 mA; VCC = 2.7 V
-
10
25
-
25
Ω
ISW = 24 mA; VCC = 3.0 V to 3.6 V
-
8.3
20
-
20
Ω
ISW = 32 mA; VCC = 4.5 V to 5.5 V
-
7.4
15
-
15
Ω
ISW = 8 mA; VCC = 2.3 V to 2.7 V
-
8.5
20
-
20
Ω
ISW = 12 mA; VCC = 2.7 V
-
8.0
18
-
18
Ω
ISW = 24 mA; VCC = 3.0 V to 3.6 V
-
7.5
15
-
15
Ω
ISW = 32 mA; VCC = 4.5 V to 5.5 V
-
7.3
10
-
10
Ω
ISW = 8 mA; VCC = 2.3 V to 2.7 V
-
8.5
20
-
20
Ω
ISW = 12 mA; VCC = 2.7 V
-
7.2
18
-
18
Ω
ISW = 24 mA; VCC = 3.0 V to 3.6 V
-
6.5
15
-
15
Ω
-
5.7
10
-
10
Ω
ISW = 8 mA; VCC = 2.5 V
-
17
-
-
-
Ω
ISW = 12 mA; VCC = 2.7 V
-
10
-
-
-
Ω
ISW = 24 mA; VCC = 3.3 V
-
5
-
-
-
Ω
ISW = 32 mA; VCC = 5.0 V
-
3
-
-
-
Ω
VSW = GND to VCC; VI = VIH;
see Figure 8
VSW = GND; VI = VIH; see Figure 8
VSW = VCC; VI = VIH
ISW = 32 mA; VCC = 4.5 V to 5.5 V
RON(flat)
ON resistance
(flatness)
VSW = GND to VCC; VI = VIH
[2]
[1]
All typical values are measured at Tamb = 25 °C and nominal VCC.
[2]
Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and
temperature.
74LVCV2G66
Product data sheet
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Rev. 3 — 16 June 2010
© NXP B.V. 2010. All rights reserved.
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74LVCV2G66
NXP Semiconductors
Overvoltage tolerant bilateral switch
10.3 ON resistance test circuit and graphs
001aaa536
16
RON
(Ω)
VCC = 2.5 V
2.7 V
3.3 V
5.0 V
12
VSW
8
VCC
nE
VIH
nY
VI
4
nZ
GND
ISW
0
0
2
4
VI = GND to 5.5 V; Tamb = 25 °C.
VI = GND to 5.5 V; RON = VSW / ISW.
Fig 8.
Test circuit for measuring ON resistance
74LVCV2G66
Product data sheet
6
VI (V)
001aag490
Fig 9.
Typical ON resistance as a function of input
voltage
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74LVCV2G66
NXP Semiconductors
Overvoltage tolerant bilateral switch
001aaa537
16
Tamb = +85 °C
+25 °C
−40 °C
+125 °C
RON
(Ω)
12
001aaa538
16
RON
(Ω)
Tamb = +85 °C
+25 °C
−40 °C
+125 °C
12
8
8
4
4
0
0
0
2
4
6
0
2
4
VI (V)
6
VI (V)
a. VCC = 2.5 V
b. VCC = 2.7 V
001aaa539
16
001aaa540
16
RON
(Ω)
RON
(Ω)
Tamb = +85 °C
+25 °C
−40 °C
+125 °C
12
12
8
8
4
4
0
Tamb = +85 °C
+25 °C
−40 °C
+125 °C
0
0
2
4
6
0
VI (V)
c. VCC = 3.3 V
2
4
6
VI (V)
d. VCC = 5.0 V
Fig 10. ON resistance as a function of input voltage at various supply voltages
74LVCV2G66
Product data sheet
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74LVCV2G66
NXP Semiconductors
Overvoltage tolerant bilateral switch
11. Dynamic characteristics
Table 9.
Dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter
−40 °C to +85 °C
Conditions
Min
Max
Min
Max
VCC = 2.3 V to 2.7 V
-
0.4
1.2
-
2.0
VCC = 2.7 V
-
0.4
1.0
-
1.5
ns
VCC = 3.0 V to 3.6 V
-
0.3
0.8
-
1.5
ns
-
0.2
0.6
-
1.0
ns
VCC = 2.3 V to 2.7 V
1.0
4.7
12
1.0
15
ns
VCC = 2.7 V
1.0
4.4
8.5
1.0
11
ns
VCC = 3.0 V to 3.6 V
1.0
3.8
7.5
1.0
9.5
ns
1.0
2.7
5.0
1.0
6.5
ns
VCC = 2.3 V to 2.7 V
1.0
6.0
16
1.0
20
ns
VCC = 2.7 V
1.0
7.9
15
1.0
19
ns
VCC = 3.0 V to 3.6 V
1.0
6.5
13.5
1.0
17
ns
1.0
4.4
9.0
1.0
11.5
ns
VCC = 2.5 V
-
9.7
-
-
-
pF
VCC = 3.3 V
-
10.3
-
-
-
pF
VCC = 5.0 V
-
11.3
-
-
-
pF
[2][3]
propagation delay nY to nZ or nZ to nY;
see Figure 11
tpd
VCC = 4.5 V to 5.5 V
enable time
ten
nE to nY or nZ;
see Figure 12
[5]
nE to nY or nZ;
see Figure 12
VCC = 4.5 V to 5.5 V
power dissipation
capacitance
CPD
ns
[4]
VCC = 4.5 V to 5.5 V
disable time
tdis
−40 °C to +125 °C Unit
Typ[1]
CL = 50 pF; fi = 10 MHz;
VI = GND to 5.5 V
[6]
[1]
Typical values are measured at Tamb = 25 °C and nominal VCC.
[2]
tpd is the same as tPLH and tPHL.
[3]
Propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified capacitance when
driven by an ideal voltage source (zero output impedance).
[4]
ten is the same as tPZH and tPZL.
[5]
tdis is the same as tPLZ and tPHZ.
[6]
CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC2 × fi × N + Σ{(CL + CS(ON)) × VCC2 × fo} where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
CS(ON) = maximum ON-state switch capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ{(CL + CS(ON)) × VCC2 × fo} = sum of the outputs.
74LVCV2G66
Product data sheet
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Rev. 3 — 16 June 2010
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74LVCV2G66
NXP Semiconductors
Overvoltage tolerant bilateral switch
11.1 Waveforms and test circuit
VI
nY or nZ
input
VM
VM
GND
t PLH
t PHL
VOH
nZ or nY
output
VM
VM
VOL
001aaa541
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 11. Input (nY or nZ) to output (nZ or nY) propagation delays
VI
nE input
VM
GND
t PLZ
t PZL
VCC
output
LOW-to-OFF
OFF-to-LOW
nY or nZ
VM
VX
VOL
t PZH
t PHZ
nY or nZ
output
HIGH-to-OFF
OFF-to-HIGH
VOH
VY
VM
GND
switch
enabled
switch
disabled
switch
enabled
001aaa542
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 12. Enable and disable times
Table 10.
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
2.3 V to 2.7 V
0.5VCC
0.5VCC
VOL + 0.1VCC
VOH − 0.1VCC
2.7 V
1.5 V
1.5 V
VOL + 0.3 V
VOH − 0.3 V
3.0 V to 3.6 V
1.5 V
1.5 V
VOL + 0.3 V
VOH − 0.3 V
4.5 V to 5.5 V
0.5VCC
0.5VCC
VOL + 0.3 V
VOH − 0.3 V
74LVCV2G66
Product data sheet
VX
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Rev. 3 — 16 June 2010
VY
© NXP B.V. 2010. All rights reserved.
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74LVCV2G66
NXP Semiconductors
Overvoltage tolerant bilateral switch
VEXT
VCC
VI
RL
VO
G
DUT
RT
RL
CL
mna616
Test data is given in Table 11.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
VEXT = External voltage for measuring switching times.
Fig 13. Load circuit for measuring switching times
Table 11.
Test data
Supply voltage
Input
Load
VEXT
VCC
VI
tr, tf
CL
RL
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
2.3 V to 2.7 V
VCC
≤ 2.0 ns
30 pF
500 Ω
open
GND
2VCC
2.7 V
2.7 V
≤ 2.5 ns
50 pF
500 Ω
open
GND
6.0 V
3.0 V to 3.6 V
2.7 V
≤ 2.5 ns
50 pF
500 Ω
open
GND
6.0 V
4.5 V to 5.5 V
VCC
≤ 2.5 ns
50 pF
500 Ω
open
GND
2VCC
11.2 Additional dynamic characteristics
Table 12. Additional dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 °C.
Symbol
Parameter
Conditions
THD
total harmonic distortion
fi = 1 kHz; RL = 10 kΩ; CL = 50 pF;
see Figure 14
Min
Typ
Max
Unit
VCC = 2.3 V
-
0.42
-
%
VCC = 3.0 V
-
0.36
-
%
VCC = 4.5 V
-
0.47
-
%
fi = 10 kHz; RL = 10 kΩ; CL = 50 pF;
see Figure 14
74LVCV2G66
Product data sheet
VCC = 2.3 V
-
0.11
-
%
VCC = 3.0 V
-
0.07
-
%
VCC = 4.5 V
-
0.01
-
%
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74LVCV2G66
NXP Semiconductors
Overvoltage tolerant bilateral switch
Table 12. Additional dynamic characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 °C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
f(−3dB)
−3 dB frequency response
RL = 600 Ω; CL = 50 pF;
see Figure 15
VCC = 2.3 V
-
160
-
MHz
VCC = 3.0 V
-
200
-
MHz
VCC = 4.5 V
-
210
-
MHz
VCC = 2.3 V
-
180
-
MHz
VCC = 3.0 V
-
180
-
MHz
VCC = 4.5 V
-
180
-
MHz
VCC = 2.3 V
-
−65
-
dB
VCC = 3.0 V
-
−65
-
dB
VCC = 4.5 V
-
−62
-
dB
VCC = 2.3 V
-
−37
-
dB
VCC = 3.0 V
-
−36
-
dB
VCC = 4.5 V
-
−36
-
dB
VCC = 2.3 V
-
91
-
mV
VCC = 3.0 V
-
119
-
mV
VCC = 4.5 V
-
205
-
mV
VCC = 2.3 V
-
−56
-
dB
VCC = 3.0 V
-
−55
-
dB
VCC = 4.5 V
-
−55
-
dB
VCC = 2.3 V
-
−29
-
dB
VCC = 3.0 V
-
−28
-
dB
VCC = 4.5 V
-
−28
-
dB
RL = 50 Ω; CL = 5 pF; see Figure 15
αiso
isolation (OFF-state)
RL = 600 Ω; CL = 50 pF; fi = 1 MHz;
see Figure 16
RL = 50 Ω; CL = 5 pF; fi = 1 MHz;
see Figure 16
Vct
Xtalk
crosstalk voltage
crosstalk
between digital inputs and switch;
RL = 600 Ω; CL = 50 pF; fi = 1 MHz;
tr = tf = 2 ns; see Figure 17
between switches; RL = 600 Ω;
CL = 50 pF; fi = 1 MHz; see Figure 18
between switches; RL = 50 Ω;
CL = 5 pF; fi = 1 MHz; see Figure 18
Qinj
charge injection
74LVCV2G66
Product data sheet
CL = 0.1 nF; Vgen = 0 V; Rgen = 0 Ω;
fi = 1 MHz; RL = 1 MΩ; see Figure 19
VCC = 2.5 V
-
< 0.003 -
pC
VCC = 3.3 V
-
0.003
-
pC
VCC = 4.5 V
-
0.0035
-
pC
VCC = 5.5 V
-
0.0035
-
pC
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Rev. 3 — 16 June 2010
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74LVCV2G66
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Overvoltage tolerant bilateral switch
11.3 Test circuits
VCC
0.5VCC
nE
VIH
RL
nY/nZ
10 μF
nZ/nY
VO
600 Ω
fi
D
CL
001aag492
Test conditions:
VCC = 2.3 V: Vi = 2 V (p-p).
VCC = 3 V: Vi = 2.5 V (p-p).
VCC = 4.5 V: Vi = 4 V (p-p).
Fig 14. Test circuit for measuring total harmonic distortion
VCC
nE
VIH
0.1 μF
fi
0.5VCC
RL
nY/nZ
nZ/nY
VO
50 Ω
CL
dB
001aag491
Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads −3 dB.
Fig 15. Test circuit for measuring the frequency response when switch is in ON-state
0.5VCC
VCC
RL VIL
0.1 μF
fi
0.5VCC
nE
nY/nZ
RL
nZ/nY
50 Ω
VO
CL dB
001aag493
Adjust fi voltage to obtain 0 dBm level at input.
Fig 16. Test circuit for measuring isolation (OFF-state)
74LVCV2G66
Product data sheet
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74LVCV2G66
NXP Semiconductors
Overvoltage tolerant bilateral switch
VCC
nE
nY/nZ
G
logic
input
50 Ω
nZ/nY
600 Ω
VO
RL
0.5VCC
CL
0.5VCC
001aag494
Fig 17. Test circuit for measuring crosstalk voltage (between digital inputs and switch)
0.5VCC
1E
VIH
0.1 μF
Ri
1Y or 1Z
600 Ω
fi
RL
1Z or 1Y
CHANNEL
ON
50 Ω
CL
50 pF
VO1
0.5VCC
2E
VIL
RL
2Y or 2Z
2Z or 2Y
CHANNEL
OFF
Ri
600 Ω
CL
50 pF
VO2
001aag496
20 log10 (VO2 / VO1) or 20 log10 (VO1 / VO2).
Fig 18. Test circuit for measuring crosstalk between switches
74LVCV2G66
Product data sheet
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© NXP B.V. 2010. All rights reserved.
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74LVCV2G66
NXP Semiconductors
Overvoltage tolerant bilateral switch
VCC
nE
Rgen
G
logic
input
nY/nZ
nZ/nY
VO
RL
1 MΩ
Vgen
CL
0.1 nF
001aag495
a. Test circuit
logic
input (nE)
off
on
off
ΔVO
VO
mna675
b. Input and output pulse definitions
Qinj = ΔVO × CL.
ΔVO = output voltage variation.
Rgen = generator resistance.
Vgen = generator voltage.
Fig 19. Test circuit for measuring charge injection
74LVCV2G66
Product data sheet
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74LVCV2G66
NXP Semiconductors
Overvoltage tolerant bilateral switch
12. Application information
Use the 74LVCV2G66 to reduce component count and footprint in low-power portable
applications.
Typical ‘66’ devices do not have low-power enable inputs causing a high ΔICC. To reduce
power consumption in portable (battery) applications, a current limiting resistor is used.
(see Figure 20a). The low-power enable inputs of the 74LVCV2G66 have much lower
ΔICC, eliminating the necessity of the current limiting resistor (see Figure 20b).
5V
5V
1 MΩ
VCC
VCC
3V
nE
3V
nZ
nY
'66' device
(a)
nE
nZ
nY
74LVCV2G66
(b)
001aaa550
Fig 20. Application example
74LVCV2G66
Product data sheet
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Rev. 3 — 16 June 2010
© NXP B.V. 2010. All rights reserved.
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74LVCV2G66
NXP Semiconductors
Overvoltage tolerant bilateral switch
13. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
D
E
A
SOT505-2
X
c
HE
y
v M A
Z
5
8
A
A2
(A3)
A1
pin 1 index
θ
Lp
L
1
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(1)
e
HE
L
Lp
v
w
y
Z(1)
θ
mm
1.1
0.15
0.00
0.95
0.75
0.25
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
0.65
4.1
3.9
0.5
0.47
0.33
0.2
0.13
0.1
0.70
0.35
8°
0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT505-2
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-01-16
---
Fig 21. Package outline SOT505-2 (TSSOP8)
74LVCV2G66
Product data sheet
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74LVCV2G66
NXP Semiconductors
Overvoltage tolerant bilateral switch
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
D
E
SOT765-1
A
X
c
y
HE
v M A
Z
5
8
Q
A
A2
A1
pin 1 index
(A3)
θ
Lp
1
4
e
L
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(2)
e
HE
L
Lp
Q
v
w
y
Z(1)
θ
mm
1
0.15
0.00
0.85
0.60
0.12
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
0.5
3.2
3.0
0.4
0.40
0.15
0.21
0.19
0.2
0.13
0.1
0.4
0.1
8°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT765-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-06-07
MO-187
Fig 22. Package outline SOT765-1 (VSSOP8)
74LVCV2G66
Product data sheet
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Rev. 3 — 16 June 2010
© NXP B.V. 2010. All rights reserved.
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74LVCV2G66
NXP Semiconductors
Overvoltage tolerant bilateral switch
XSON8U: plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 x 2 x 0.5 mm
B
D
SOT996-2
A
A
E
A1
detail X
terminal 1
index area
e1
v
w
b
e
L1
1
4
8
5
C
C A B
C
M
M
y
y1 C
L2
L
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
b
D
E
e
e1
L
L1
L2
v
w
y
y1
mm
0.5
0.05
0.00
0.35
0.15
2.1
1.9
3.1
2.9
0.5
1.5
0.5
0.3
0.15
0.05
0.6
0.4
0.1
0.05
0.05
0.1
REFERENCES
OUTLINE
VERSION
IEC
SOT996-2
---
JEDEC
JEITA
---
EUROPEAN
PROJECTION
ISSUE DATE
07-12-18
07-12-21
Fig 23. Package outline SOT996-2 (XSON8U)
74LVCV2G66
Product data sheet
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Rev. 3 — 16 June 2010
© NXP B.V. 2010. All rights reserved.
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Overvoltage tolerant bilateral switch
14. Abbreviations
Table 13.
Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
15. Revision history
Table 14:
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LVCV2G66 v.3
20100616
Product data sheet
-
74LVCV2G66_2
-
74LVCV2G66_1
Modifications:
74LVCV2G66_2
Modifications:
74LVCV2G66_1
74LVCV2G66
Product data sheet
•
Conditions for ICC and ΔICC corrected.
20080703
Product data sheet
•
The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
Added type number 74LVCV2G66GD (XSON8U package).
20040402
Product data sheet
-
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 16 June 2010
-
© NXP B.V. 2010. All rights reserved.
20 of 23
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NXP Semiconductors
Overvoltage tolerant bilateral switch
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. The product is not designed, authorized or warranted to be
74LVCV2G66
Product data sheet
suitable for use in medical, military, aircraft, space or life support equipment,
nor in applications where failure or malfunction of an NXP Semiconductors
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. NXP Semiconductors accepts no
liability for inclusion and/or use of NXP Semiconductors products in such
equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 16 June 2010
© NXP B.V. 2010. All rights reserved.
21 of 23
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NXP Semiconductors
Overvoltage tolerant bilateral switch
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74LVCV2G66
Product data sheet
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Rev. 3 — 16 June 2010
© NXP B.V. 2010. All rights reserved.
22 of 23
74LVCV2G66
NXP Semiconductors
Overvoltage tolerant bilateral switch
18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
10.1
10.2
10.3
11
11.1
11.2
11.3
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ON resistance test circuit and graphs. . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Waveforms and test circuit . . . . . . . . . . . . . . . 10
Additional dynamic characteristics . . . . . . . . . 11
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Application information. . . . . . . . . . . . . . . . . . 16
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20
Legal information. . . . . . . . . . . . . . . . . . . . . . . 21
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Contact information. . . . . . . . . . . . . . . . . . . . . 22
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 16 June 2010
Document identifier: 74LVCV2G66