INTEGRATED CIRCUITS PCA8550 4-bit multiplexed/1-bit latched 5-bit I2C EEPROM Product specification 1998 Sep 29 Philips Semiconductors Product specification 4-bit multiplexed/1-bit latched 5-bit I2C EEPROM FEATURES PCA8550 PIN CONFIGURATION •4-bit 2-to-1 multiplexer, 1-bit latch •5-bit internal non-volatile register •Override input forces all outputs to logic 0 •Internal non-volatile register write/readable via I2C bus •Write-protect pin enables/disables I2C writes to register •2.5V multiplexed outputs •3.3V non-multiplexed output (latched) •5V tolerant inputs •Useful for ’jumperless’ configuration of PC motherboards •Designed for use in Pentium Pro/Pentium II systems 2 I C SCL 1 16 VCC I2C SDA 2 15 WP 14 NON_MUXED_OUT OVERRIDE# 3 MUX_IN A 4 13 MUX_SELECT MUX_IN B 5 12 MUX_OUT A MUX_IN C 6 11 MUX_OUT B MUX_IN D 7 10 MUX_OUT C GND 8 9 MUX_OUT D SW00216 Pentium II is a registered trademark of Intel Corporation DESCRIPTION The primary function of the 4-bit 2-to-1 I2C multiplexer is to select either a 4-bit input or data from a non-volatile register and drive this value onto the output pins. One additional non-multiplexed register output is also provided. The non-multiplexed output is latched to prevent output value changes during I2C writes to the non-volatile register. A write protect input is provided to enable/disable the ability to write to the non-volatile register. An ‘‘override” input feature forces all outputs to logic 0. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DRAWING NUMBER 16-Pin Plastic SO 0°C to +70°C PCA8550D PCA8550D SOT109-1 16-Pin Plastic SSOP 0°C to +70°C PCA8550DB PCA8550DB SOT338-1 16-Pin Plastic TSSOP 0°C to +70°C PCA8550PW PCA8550PW DH SOT403-1 The write protect (WP) input is used to control the ability to write the contents of the 5-bit non-volatile register. If the WP signal is logic 0, the I2C bus will be able to write the contents of the non-volatile register. If the WP signal is logic 1, data will not be allowed to be written into the non-volatile register. FUNCTIONAL DESCRIPTION When the MUX_SELECT signal is logic 0, the multiplexer will select the data from the non-volatile register to drive on the MUX_OUT pins. When the MUX_SELECT signal is logic 1, the multiplexer will select the MUX_IN lines to drive on the MUX_OUT pins. The MUX_SELECT signal is also used to latch the NON_MUXED_OUT signal which outputs data from the non-volatile register. The NON_MUXED_OUT signal latch is transparent when MUX_SELECT is in a logic 0 state, and will latch data when MUX_SELECT is in a logic 1 state. When the active-LOW OVERRIDE# signal is set to logic 0 and the MUX_SELECT signal is at a logic 0, all outputs will be driven to logic 0. This information is summarized in Table 1. 1998 Sep 29 The factory default for the contents of the non-volatile register are all logic 0. These stored values can be read or written using the I2C bus (described in the next section). The OVERRIDE#, WP, MUX_IN, and MUX_SELECT signals have internal pullup resistors. See the DC and AC Characteristics for hysteresis and signal spike suppression figures. 2 853-2015 20105 Philips Semiconductors Product specification 4-bit multiplexed/1-bit latched 5-bit I2C EEPROM PIN DESCRIPTION PCA8550 FUNCTION TABLE PIN NUMBER SYMBOL 1 I2C SCL I2C bus clock 2 I2C SDA Bi-directional I2C bus data 3 OVERRIDE# Forces all outputs to logic 0 4 MUX_IN A 5 MUX_IN B Table 1. Function table FUNCTION External in inputs uts to multiplexer multi lexer 6 MUX_IN C 7 MUX_IN D 8 GND 9 MUX_OUT D 10 MUX_OUT C 11 MUX_OUT B 12 MUX_OUT A 13 MUX_SELECT 14 NON_MUXED_OUT TTL-level output from non-volatile memory 15 WP Non-volatile register write-protect 16 VCC Positive voltage rail OVERRIDE # MUX_SELECT MUX_OUT OUTPUTS NON_MUXED_OUT OUTPUT 0 0 All 0’s All 0’s 0 1 MUX_IN inputs NON_MUXED_OUT1 1 0 From nonvolatile register From non-volatile register 1 1 MUX_IN inputs From non-volatile register Common ground voltage rail Latched NOTE 1. Latched NON_MIXED_OUT state will be the value present on the NON_MUXED_OUT output at the time of the MUX_SELECT input transitioned from a logic 0 to a logic 1 state. 2 5V multi 2.5V multiplexed lexed output out ut Selects MUX_IN inputs or register contents for MUX_OUT outputs I2C Interface Communicating with this device is initiated by sending a valid address on the I2C bus. The address format (see FIgure 1) is a fixed unique 7-bit value followed by a 1-bit read/write value which determines the direction of the data transfer. MSB LSB 1 0 0 1 1 1 0 R/W# SW00218 Figure 1. I2C Address Byte Following the address and acknowledge bit are 8 data bits which, depending on the read/write bit in the address, will read data from or write data to the non-volatile register. Data will be written to the register if the read/write bit is logic 0 and the WP input is logic 0. Data will be read from the register if the bit is logic 1. The three high-order bits (see FIgure 2) are logic 0. The next bit is data which is non-multiplexed. The low four bits are the data which will be multiplexed. A write with any of the first three bits non-zero will be aborted. NOTE: 1. To ensure data integrity, the non-volatile register must be internally write protected when VCC to the I2C bus is powered down or VCC to the component is dropped below normal operating levels. 1998 Sep 29 3 Philips Semiconductors Product specification 4-bit multiplexed/1-bit latched 5-bit I2C EEPROM PCA8550 MSB LSB 0 0 0 NONMUXED DATA MUX DATA D MUX DATA C MUX DATA B MUX DATA A SW00219 Figure 2. I2C Data Byte BLOCK DIAGRAM 10–30k Ω 13 3 CRESET# MUX_SELECT OVERRIDE# 5-BIT EEPROM VCC3.3 = 16 GND = 8 LATCH NMO 100–150k Ω SCL I2C CLOCK CHIP SET 2 SDA I2C DATA 15 4 WRITE 3.3V OE# PROTECT A20M# MUX_IN A 5 6 7 2.5V A20M# 12 MUX_OUT A /FSBM0 3.3V 2.5V IGNNE# 11 MUX_OUT B /FSBM1 3.3V 2.5V LINT0/INTR PENTIUM PRO/ PENTIUM II 10 PROCESSORS MUX_OUT C /FSBM2 IGNNE# MUX_IN B 3.3V LINT0/INTR 2.5V LINT1/NMI 9 MUX_OUT D /FSBM3 MUX_IN C LINT1/NMI MUX_IN D 14 NON_MUX_OUT 0 4-BIT 2-to-1 MULTIPLEXER 10–30k Ω 2 I C iNTERFACE LOGIC 1 SELECT 1 10–30k Ω SW00347 1998 Sep 29 4 Philips Semiconductors Product specification 4-bit multiplexed/1-bit latched 5-bit I2C EEPROM PCA8550 ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) PARAMETER SYMBOL VCC VI VOUT Tstg CONDITIONS DC supply voltage RATING UNIT –0.5 to +4.6 V DC input voltage Note 3 –1.5 to VCC +1.5 V DC output voltage Note 3 –0.5 to VCC +0.5 V –60 to +150 °C Storage temperature range NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER CONDITIONS UNIT MIN MAX 3.0 3.6 V –0.5 2.7 0.9 4.0 0.4 V –0.5 2.0 0.8 4.0 V 2.0 –2.0 mA VCC DC supply voltage SCL, SDA VIL VIH VOL OVERRIDE#, MUX_IN, MUX_SELECT VIL VIH MUX_OUT, NON_MUXED_OUT IOL IOH dt/dv Input transition rise or fall time 0 10 ns/V TA Operating temperature 0 70 °C 1998 Sep 29 IOL= 3mA 5 Philips Semiconductors Product specification 4-bit multiplexed/1-bit latched 5-bit I2C EEPROM PCA8550 DC CHARACTERISTICS LIMITS SYMBOL PARAMETER Temp = 0°C to +70°C 3.0V < VCC ≤ 3.6V UNIT MIN MAX 0 0.6 3.0 6.0 –32 –12 V mA mA µA µA V SCL, SDA VOL IOL (VOL = 0.4V) IOL (VOL = 0.6V) IIL (VIL = 0.4V) IIH (VIH = 2.4V) VHYS1 –7 –1.5 0.19 OVERRIDE#, WP, MUX_SELECT IIL IIH –86 –20 –267 –100 µA MUX A ⇒ D IIL (VIL = 0.4V) IIH (VIH = 2.4V) –0.72 –0.166 –2.0 –0.75 mA MUX_OUT VOL (IOL = 100µA) VOL (IOL = 2.0mA) VOH (IOH = –100µA) VOH (IOH = –1.0mA) –0.3 –0.3 2.0 1.7 0.4 0.7 2.625 2.625 V NON_MUXED_OUT VOL (IOL = 100µA) VOL (IOL = 2.0mA) VOH (IOH = –100µA) VOH (IOH = –2.0mA) –0.5 –0.5 2.4 2.0 0.4 0.7 3.6 3.6 V ICC Quiescent supply current (VCC = 3.3V) VI = 0V to VCC 10 mA ICC Quiescent supply current VI = VCC 500 µA CIN All inputs 10 pF ESD protection 2.0 KV Input diode clamp voltage –1.5 V NOTES: 1. VHYS is the hysteresis of Schmitt-Trigger inputs 2. Human body model NON-VOLATILE STORAGE SPECIFICATIONS Parameter 1998 Sep 29 Specification Memory cell data retention 10 years min Number of memory cell write cycles 1,000 cycles min 6 Philips Semiconductors Product specification 4-bit multiplexed/1-bit latched 5-bit I2C EEPROM PCA8550 AC CHARACTERISTICS LIMITS SYMBOL PARAMETER TMPD MIN MAX UNIT Mux input to output propagation delay 20.0 ns TSOV MUX_SELECT to output valid 22 ns TOVN OVERRIDE# to NON_MUX output delay 15.0 ns TOVM OVERRIDE# to mux output delay 25.0 ns TR Output rise time 1.0 3.0 ns/V TF Output fall time 1.0 3.0 ns/V CL Test load capacitance on Muxed/Non-Muxed outputs 15 pF 400 KHz I2C BUS fSCL I2C clock frequency 10 TSCH I2C clock high time 600 clock low time 1.3 ns TSCL I2C TDSP I2C data spike time 0 TSDS I2C data setup time 100 ns I2C data hold time 0 ns TSDH ns 50 ns TICR I2C input rise time (10–400pF bus) 20 300 ns TICF I2C input fall time (10–400pF bus) 20 300 ns TBUF I2C bus free time between start and stop 1.3 ns TSTS I2C repeated start condition setup 600 ns TSTH I2C repeated start condition hold 600 ns TSPS I2C stop condition setup 600 ns CB TW I2C bus capacitive load Write cycle 400 time1 TYPICAL = 15 NOTE: 1. WRITE CYCLE time can only be measured indirectly during write cycle. The device will not acknowledge its I2C address. 1998 Sep 29 7 pF ms Philips Semiconductors Product specification 4-bit multiplexed/1-bit latched 5-bit I2C EEPROM SO16: plastic small outline package; 16 leads; body width 3.9 mm 1998 Sep 29 8 PCA8550 SOT109-1 Philips Semiconductors Product specification 4-bit multiplexed/1-bit latched 5-bit I2C EEPROM SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm 1998 Sep 29 9 PCA8550 SOT338-1 Philips Semiconductors Product specification 4-bit multiplexed/1-bit latched 5-bit I2C EEPROM TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm 1998 Sep 29 10 PCA8550 SOT403-1 Philips Semiconductors Product specification 4-bit multiplexed/1-bit latched 5-bit I2C EEPROM NOTES 1998 Sep 29 11 PCA8550 Philips Semiconductors Product specification 4-bit multiplexed/1-bit latched 5-bit I2C EEPROM PCA8550 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 03-98 Document order number: 1998 Sep 29 12 9397-750-04606