INTEGRATED CIRCUITS PCK2057 70 – 190 MHz I2C differential 1:10 clock driver Product data Supersedes data of 2001 May 09 File under Integrated Circuits, ICL03 2001 Jun 12 Philips Semiconductors Product data 70 – 190 MHz I2C differential 1:10 clock driver FEATURES PCK2057 PIN CONFIGURATION • Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications supporting DDR 200/266/300/333 GND 1 • Full DDR solution provided when used with PCK2002P or 48 GND 47 Y5 46 Y5 Y0 2 Y0 3 PCK2002PL, and PCK2022RA VDDQ 4 Y1 5 • 1-to-10 differential clock distribution • Very low jitter (< 100 ps) • Operation from 2.2 V to 2.7 V AVDD and 2.3 V to 2.7 V VDD • SSTL_2 interface clock inputs and outputs • HCSL to SSTL_2 input conversion • Test mode enables buffers while disabling PLL • Tolerant of Spread Spectrum input clock • 3.3 V I2C support with 3.3 V VDDI2C • 2.5 V I2C support with 2.5 V VDDI2C • Form, fit, and function compatible with CDCV850 45 VDDQ 44 Y6 43 Y6 Y1 6 GND 7 42 GND GND 8 41 GND 40 Y7 39 Y7 Y2 9 Y2 10 VDDQ 11 38 VDDQ SCL 12 37 SDA 36 FBIN CLK 13 35 FBIN CLK 14 VDDI2C 15 AVDD 16 34 VDDQ 33 FBOUT AGND 17 GND 18 32 FBOUT 31 GND Y3 19 30 Y8 Y3 20 29 Y8 28 VDDQ VDDQ 21 DESCRIPTION Y4 22 The PCK2057 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs and one differential pair of feedback clock outputs. The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), the 2-line serial interface (SDA, SCL), and the analog power input (AVDD). The two-line serial interface (I2C) can put the individual output clock pairs in a high-impedance state. When AVDD is tied to GND, the PLL is turned off and bypassed for test purposes. Y4 23 27 Y9 26 Y9 25 GND GND 24 SW00506 PIN DESCRIPTION The device provides a standard mode (100 kbits) I2C interface for device control. The implementation is as a slave/receiver. The serial inputs (SDA, SCL) provide integrated pull-up resistors (typically 100 kΩ). Two 8-bit, 2-line serial registers provide individual enable control for each output pair. All outputs default to enabled at power-up. Each output pair can be placed in a high-impedance mode, when a low-level control bit is written to the control register. The registers must be accessed in sequential order (i.e., random access of the registers is not supported). The I2C interface circuit can be supplied with either 2.5 V or 3.3 V (VDDI2C). Since the PCK2057 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power-up. PINS SYMBOL 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 GND DESCRIPTION Ground 2, 3, 5, 6, 9, 10, 19, 20, 22, 23, 26, 27, 29, 30, 32, 33, 39, 40, 43, 44, 46, 47 Yn, Yn, FBOUT, FBOUT 4, 11, 21, 28, 34, 38, 45 VDDQ 13, 14, 35, 36 CLK, CLK, FBIN, FBIN Buffered output copies of input clock, CLK 2.5 V supply Differential clock inputs and feedback differential clock inputs 16 AVDD Analog power 17 AGND Analog ground 37 SDA Serial data 12 SCL Serial clock 15 VDD I2C I2C power ORDERING INFORMATION PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER 48-Pin Plastic TSSOP 0 to +70 °C PCK2057DGG SOT362-1 2001 Jun 12 2 853–2253 26485 Philips Semiconductors Product data 70 – 190 MHz I2C differential 1:10 clock driver PCK2057 FUNCTION TABLE OUTPUTS1 INPUTS AVDD CLK CLK Y Y GND L GND H H L L H 2.5 V (nom.) L 2.5 V (nom.) H H L L H PLL ON/OFF FBOUT FBOUT H L H Bypassed/OFF L H L Bypassed/OFF H L H ON L H L ON NOTES: H = HIGH voltage level L = LOW voltage level 1. Each output pair (except FBOUT and FBOUT) can be put into a high-impedance state through the 2-line serial interface. BLOCK DIAGRAM SDA CONTROL LOGIC Y0 Y0 SCL Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 CLK CLK PLL FBIN FBIN AVDD Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9 Y9 FBOUT FBOUT SW00507 2001 Jun 12 3 Philips Semiconductors Product data 70 – 190 MHz I2C differential 1:10 clock driver PCK2057 I2C ADDRESS 1 1 0 1 0 0 1 R/W su01394 I2C CONSIDERATIONS I2C has been chosen as the serial bus interface to control the PCK2057. I2C was chosen to support the JEDEC proposal JC-42.5 168 Pin Unbuffered SDRAM DIMM. All vendors are required to determine the legal issues associated with the manufacture of I2C devices. 1) Address assignment: The clock driver in this specification uses the single, 7-bit address shown below. All devices can use the address if only one master clock driver is used in a design. The address can be re-used for the CKBF device if no other conflicting I2C clock driver is used in the system. The following address was confirmed by Philips on 09/04/96. A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 1 0 0 1 0 NOTE: The R/W bit is used by the I2C controller as a data direction bit. A ‘zero’ indicates a transmission (WRITE) to the clock device. A ‘one’ indicates a request for data (READ) from the clock driver. Since the definition of the clock buffer only allows the controller to WRITE data; the R/W bit of the address will always be seen as ‘zero’. Optimal address decoding of this bit is left to the vendor. 2) Data Transfer Rate: 100 kbits/s (standard mode) is the base functionality required. Fast mode (400 kbits/s) functionality is optional. 3) Logic Levels: I2C logic levels are based on a percentage of VDD for the controller and other devices on the bus. Assume all devices are based on a 3.3 Volt supply. 4) Data Byte Format: Byte format is 8 Bits as described in the following appendices. 5) Data Protocol: To simplify the clock I2C interface, the clock driver serial protocol was specified to use only block writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. Indexed bytes are not allowed. However, the SMBus controller has a more specific format than the generic I2C protocol. The clock driver must meet this protocol which is more rigorous than previously stated I2C protocol. Treat the description from the viewpoint of controller. The controller “writes” to the clock driver. 1 bit 7 bits 1 1 8 bits 1 Start bit Slave Address R/W Ack DUMMY Ack DUMMY 1 bit 8 bits 1 8 bits 1 1 Ack Data Byte 1 Ack Data Byte 2 Ack Stop SW00911 NOTE: The acknowledgement bit is returned by the slave/receiver (the clock driver). 6) Electrical Characteristics: All electrical characteristics must meet the standard mode specifications found in section 15 of the I2C specification. a) Pull-Up Resistors: Any internal resistors pull-ups on the SDATA and SCLOCK inputs must be stated in the individual datasheet. The use of internal pull-ups on these pins of below 100 kΩ is discouraged. Assume that the board designer will use a single external pull-up resistor for each line and that these values are in the 5–6 kΩ range. Assume one I2C device per DIMM (serial presence detect), one I2C controller, one clock driver plus one/two more I2C devices on the platform for capacitive loading purposes. (b) Input Glitch Filters: Only fast mode I2C devices require input glitch filters to suppress bus noise. The clock driver is specified as a standard mode device and is not required to support this feature. For specific I2C information, consult the Philips I2C Peripherals Data Handbook IC12 (1997). 2001 Jun 12 4 Philips Semiconductors Product data 70 – 190 MHz I2C differential 1:10 clock driver PCK2057 SERIAL CONFIGURATION MAP The serial bits will be read by the clock buffer in the following order: Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0 All unused register bits (Reserved and “—”) should be designed as “Don’t Care”. It is expected that the controller will force all of these bits to a “0” level. All register bits labeled “Initialize to 0” must be written to zero during initialization. Failure to do so may result in a higher than normal operating current. Byte 0: Active/inactive register 1 = enable; 0 = disable BIT PIN# NAME INITIAL VALUE DESCRIPTION 7 2, 3 CLK0, CLK0 1 Enable/Disable Outputs 6 5, 6 CLK1, CLK1 1 Enable/Disable Outputs 5 9, 10 CLK2, CLK2 1 Enable/Disable Outputs 4 19, 20 CLK3, CLK3 1 Enable/Disable Outputs 3 22, 23 CLK4, CLK4 1 Enable/Disable Outputs 2 47, 46 CLK5, CLK5 1 Enable/Disable Outputs 1 44, 43 CLK6, CLK6 1 Enable/Disable Outputs 0 40, 39 CLK7, CLK7 1 Enable/Disable Outputs NOTE: 1. Inactive means outputs are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. Byte 1: Active/inactive register 1 = enable; 0 = disable BIT PIN# NAME INITIAL VALUE DESCRIPTION 7 30, 29 CLK8, CLK8 1 Enable/Disable Outputs 6 27, 26 CLK9, CLK9 1 Enable/Disable Outputs 5 — — 0 Reserved 4 — — 0 Reserved 3 — — 0 Reserved 2 — — 0 Reserved 1 — — 0 Power-Down Mode Disable/Enable 0 — — 0 HCSL Enable/Disable NOTE: 1. Inactive means outputs are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2001 Jun 12 5 Philips Semiconductors Product data 70 – 190 MHz I2C differential 1:10 clock driver PCK2057 ABSOLUTE MAXIMUM RATINGS (see Note 1) Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). SYMBOL VDDQ/AVDD VDDI2C PARAMETER LIMITS TEST CONDITIONS MAX Supply voltage range 0.5 3.6 V I2C supply voltage range 0.5 4.6 V VI Input voltage range VO Output voltage range IIK Input clamp current IOK Output clamp current IO Continuous output current except SCL and SDA see Notes 2 and 3 –0.5 VDDQ + 0.5 V SCL and SDA see Notes 2 and 3 –0.5 VDDI2C + 0.5 V see Notes 2 and 3 –0.5 VDDQ + 0.5 V VI < 0 or VI > VDDQ — ±50 mA VO < 0 or VO > VDDQ — ±50 mA VO = 0 to VDDQ — ±50 mA — ±100 mA –65 +150 °C Continuous current to GND or VDDQ Tstg UNIT MIN Storage temperature range NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. This value is limited to 3.6 V maximum. RECOMMENDED OPERATING CONDITIONS (see Note 1) SYMBOL PARAMETER Supply voltage TEST CONDITIONS MAX VDDQ 2.3 — 2.7 V AVDD 2.2 — 2.7 V 2.3 — 3.6 V — 0 0.24 V –0.3 — VDDQ – 0.4 V FBIN, FBIN — — VDDQ/2 – 0.18 V SDA, SCL — — 0.3 × VDDI2C V 0.66 0.71 — V see Note 2 CLK, CLK, HCSL buffer only LOW-level input voltage g CLK, CLK CLK, CLK, HCSL buffer only VIH HIGH-level input voltage g CLK, CLK 0.4 — VDDQ + 0.3 V FBIN, FBIN VDDQ/2 + 0.18 — — V SDA, SCL 0.7 × VDDI2C — — V see Note 3 –0.3 — VDDQ + 0.3 V DC: CLK, FBIN see Note 4 0.36 — VDDQ + 0.6 V AC: CLK, FBIN see Note 4 0.2 — VDDQ + 0.6 V see Note 5 0.45 × (VIH – VIL) — 0.55 × (VIH – VIL) V — — –12 mA — — 12 mA — — 3 mA DC input signal voltage VID Differential input signal g voltage VIX Input differential pair cross-voltage IOH HIGH-level output current IOL O LOW level output current LOW-level SR Input slew rate Tamb UNIT TYP VDDI2C VIL LIMITS MIN SDA 1 — 4 V/ns SSC modulation frequency see Figure 3 30 — 33.3 kHz SSC clock input frequency deviation 0 — –0.50 % Operating free-air temperature 0 — +70 °C NOTES: 1. Unused inputs must be held HIGH or LOW to prevent them from floating. 2. All devices on the I2C-bus, with input levels related to VDDI2C, must have one common supply line to which the pull-up resistor is connected. 3. DC input signal voltage specifies the allowable DC execution of differential input. 4. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level, and VCP is the complementary input level. 5. Differential cross-point voltage is expected to track variations of VDD and is the voltage at which the differential signals must be crossing. 2001 Jun 12 6 Philips Semiconductors Product data 70 – 190 MHz I2C differential 1:10 clock driver PCK2057 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. LIMITS SYMBOL VIK VOH O VOL PARAMETER Input voltage TEST CONDITIONS All inputs HIGH level output voltage HIGH-level LOW level output voltage LOW-level SDA VOX II IOZ IDDPD IDD AIDD IDD I2C CI MIN TYP1 MAX UNIT VDDQ = 2.3 V; II = –18 mA — — –1.2 V VDDQ = min to max; IOH = –1 mA VDDQ – 0.1 — — V VDDQ = 2.3 V; IOH = –12 mA 1.7 — — V VDDQ = min to max; IOL = 1 mA — — 0.1 V VDDQ = 2.3 V; IOL = 12 mA — — 0.6 V VDDI2C = 3.0 V; IOL = 3 mA — — 0.4 V Output differential cross voltage VDDQ/2 – 0.2 VDDQ/2 VDDQ/2 + 0.2 V VDDQ = 2.7 V; VI = 0 V to 2.7 V — — ±10 µA High impedance state output current VDDQ = 2.7 V; VO = VDDQ or GND — — ±10 µA Power-down current on VDDQ + AVDD CLK at 0 MHz; Σ of IDD and AIDD — 150 250 µA CLK at 0 MHz; VDDQ = 3.6 V — 3 20 µA fO = 100 MHz — 205 230 mA Input current CLK, FBIN Power-down current on VDDI2C Dynamic current on VDDQ Supply current on AVDD Supply current on VDD fO = 100 MHz — 4 6 mA VDDI2C = 3.6 V; SCL and SDA = 3.6V — 1 2 mA VDDQ = 2.5 V; VI = VDDQ or GND 2 2.8 3 pF I2C Input capacitance NOTES: 1. All typical values are at respective nominal VDDQ. TIMING REQUIREMENTS Over recommended ranges of supply voltage and operating free-air temperature. LIMITS SYMBOL fCLK PARAMETER UNIT MIN MAX Clock frequency 70 190 MHz Input clock duty cycle 40 60 % — 100 µs Stabilization time 1 NOTE: 1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application. TIMING REQUIREMENTS FOR THE I2C INTERFACE Over recommended ranges of operating free-air temperature and VDDI2C from 3.3 V to 3.6 V.. STANDARD-MODE I2C-BUS SYMBOL PARAMETER MIN MAX UNIT fSCL SCL clock frequency — 100 kHz tBUF Bus free time between a STOP and START condition 4.7 — µs tSU;STA Set-up time for a repeated START condition 4.7 — µs tHD;STA Hold time (repeated) START condition. After this period, the first clock is generated. 4.0 — µs tLOW LOW period of the SCL clock 4.7 — µs tHIGH HIGH period of the SCL clock 4.0 — µs tr Rise time of both SDA and SCL signals — 1000 ns tf Fall time of both SDA and SCL signals — 300 ns 250 — ns tSU;DAT DATA set-up time tHD;DAT DATA hold time 0 — ns tSU;STO Set-up time for STOP condition 4 — µs 2001 Jun 12 7 Philips Semiconductors Product data 70 – 190 MHz I2C differential 1:10 clock driver PCK2057 AC CHARACTERISTICS LIMITS SYMBOL tPD tPHL PARAMETER TEST CONDITIONS Propagation delay time Test mode/CLK to any output UNIT MIN TYP MAX — 3.7 — ns — ns 1 HIGH-to-LOW level propagation delay time SCL to SDA (acknowledge) — 500 ten Output enable time Test mode/SDA to Y output — 85 — ns tdis Output disable time Test mode/SDA to Y output — 35 — ns tjit(per) Jitter (period); see Figure 4 100 MHz to 167 MHz –75 — 75 ps tjit(cc) Jitter (cycle-to-cycle); see Figure 5 100 MHz to 167 MHz –75 — 75 ps tjit(hper) t∅ Half-period jitter; see Figure 6 Static phase offset; see Figure 1 tslr(o) Output clock slew rate; see Figure 3 tsk(o) Output skew; see Figure 2 100 MHz to 167 MHz –90 — 90 ps 133 MHz/VID on CLK = 0.71 V 220 — 450 ps 167 MHz/VID on CLK = 0.71 V 140 — 270 ps terminated with 120 Ω/14 pF 1 — 2 V/ns — — 75 ps 30 — 33.3 kHz 0.00 — –0.50 % SSC modulation frequency SSC clock input frequency deviation NOTE: 1. This time is for a PLL frequency of 100 MHz. AC WAVEFORMS CLK CLK FBIN FBIN t(O)n t(O) = Σ t(O)n + 1 n =N t(O)n 1 N (N is a large number of samples) SW00882 Figure 1. Static phase offset Yx Yx Yx, FBOUT Yx, FBOUT tsk(O) SW00883 Figure 2. Output skew 2001 Jun 12 8 Philips Semiconductors Product data 70 – 190 MHz I2C differential 1:10 clock driver PCK2057 80% 80% VID, VOD 20% 20% CLOCK INPUTS AND OUTPUTS tSLR(I), tSLR(O) tSLR(I), tSLR(O) SW00886 Figure 3. Input and output slew rates Yx, FBOUT Yx, FBOUT tcycle n Yx, FBOUT Yx, FBOUT 1 fO tJIT(PER) = tcycle n – 1 fO SW00884 Figure 4. Period jitter tcycle n + 1 tcycle n Yx, FBOUT Yx, FBOUT tJIT(CC) = tcycle n – t cycle n+1 SW00881 Figure 5. Cycle-to-cycle jitter 2001 Jun 12 9 Philips Semiconductors Product data 70 – 190 MHz I2C differential 1:10 clock driver PCK2057 Yx, FBOUT Yx, FBOUT thalf period n thalf period n + 1 1 fO tJIT(HPER) = thalf period n – 1 2*fO SW00885 Figure 6. Half-period jitter TEST CIRCUIT VDD/2 PCK2057 C = 14 pf Z = 60 Ω SCOPE –VDD/2 R = 10 Ω Z = 50 Ω R = 50 Ω Z = 60 Ω R = 10 Ω VTT Z = 50 Ω R = 50 Ω C = 14 pf –VDD/2 VTT NOTE: VTT = GND –VDD/2 SW00912 Figure 7. Output load test measurement 2001 Jun 12 10 Philips Semiconductors Product data 70 – 190 MHz I2C differential 1:10 clock driver TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm 2001 Jun 12 11 PCK2057 SOT362-1 Philips Semiconductors Product data 70 – 190 MHz I2C differential 1:10 clock driver PCK2057 Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011. Data sheet status Data sheet status [1] Product status [2] Definitions Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. [1] Please consult the most recently issued datasheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 2001 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Date of release: 06-01 Document order number: 2001 Jun 12 12 9397 750 08476